[PATCH v3 0/2] Implement endianess swap macros for RISC-V

Ignacio Encinas posted 2 patches 10 months, 1 week ago
There is a newer version of this series
arch/riscv/include/asm/swab.h   | 43 +++++++++++++++++++++++++++++++++++++++++
include/uapi/asm-generic/swab.h | 32 ++++++++++++++++++++++++++++++
include/uapi/linux/swab.h       | 33 +------------------------------
3 files changed, 76 insertions(+), 32 deletions(-)
[PATCH v3 0/2] Implement endianess swap macros for RISC-V
Posted by Ignacio Encinas 10 months, 1 week ago
Motivated by [1]. A couple of things to note:

RISC-V needs a default implementation to fall back on. There is one
available in include/uapi/linux/swab.h but that header can't be included
from arch/riscv/include/asm/swab.h. Therefore, the first patch in this
series moves the default implementation into asm-generic.

Tested with crc_kunit as pointed out here [2]. I can't provide
performance numbers as I don't have RISC-V hardware yet.

[1] https://lore.kernel.org/all/20250302220426.GC2079@quark.localdomain/
[2] https://lore.kernel.org/all/20250216225530.306980-1-ebiggers@kernel.org/

Signed-off-by: Ignacio Encinas <ignacio@iencinas.com>
---
Changes in v3:

PATCH 2:
  Use if(riscv_has_extension_likely) instead of asm goto (Eric). It 
  looks like both versions generate the same assembly. Perhaps we should 
  do the same change in other places such as arch/riscv/include/asm/bitops.h

- Link to v2: https://lore.kernel.org/r/20250319-riscv-swab-v2-0-d53b6d6ab915@iencinas.com

Arnd, I tried your suggestion but couldn't make it work. Let me know if
I missed something in my response.

Changes in v2:
- Introduce first patch factoring out the default implementation into
  asm-generic
- Remove blank line to make checkpatch happy
- Link to v1: https://lore.kernel.org/r/20250310-riscv-swab-v1-1-34652ef1ee96@iencinas.com

---
Ignacio Encinas (2):
      include/uapi/linux/swab.h: move default implementation for swab macros into asm-generic
      riscv: introduce asm/swab.h

 arch/riscv/include/asm/swab.h   | 43 +++++++++++++++++++++++++++++++++++++++++
 include/uapi/asm-generic/swab.h | 32 ++++++++++++++++++++++++++++++
 include/uapi/linux/swab.h       | 33 +------------------------------
 3 files changed, 76 insertions(+), 32 deletions(-)
---
base-commit: a7f2e10ecd8f18b83951b0bab47ddaf48f93bf47
change-id: 20250307-riscv-swab-b81b94a9ac1b

Best regards,
-- 
Ignacio Encinas <ignacio@iencinas.com>
Re: [PATCH v3 0/2] Implement endianess swap macros for RISC-V
Posted by Ben Dooks 10 months, 1 week ago
On 03/04/2025 21:34, Ignacio Encinas wrote:
> Motivated by [1]. A couple of things to note:
> 
> RISC-V needs a default implementation to fall back on. There is one
> available in include/uapi/linux/swab.h but that header can't be included
> from arch/riscv/include/asm/swab.h. Therefore, the first patch in this
> series moves the default implementation into asm-generic.
> 
> Tested with crc_kunit as pointed out here [2]. I can't provide
> performance numbers as I don't have RISC-V hardware yet.
> 
> [1] https://lore.kernel.org/all/20250302220426.GC2079@quark.localdomain/
> [2] https://lore.kernel.org/all/20250216225530.306980-1-ebiggers@kernel.org/
> 
> Signed-off-by: Ignacio Encinas <ignacio@iencinas.com>

I'll try and get these tested with my big-endian riscv qemu and verify
if they work there.

-- 
Ben Dooks				http://www.codethink.co.uk/
Senior Engineer				Codethink - Providing Genius

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