Add virtio-spi.h header for virtio SPI.
Signed-off-by: Haixu Cui <quic_haixcui@quicinc.com>
---
include/uapi/linux/virtio_spi.h | 185 ++++++++++++++++++++++++++++++++
1 file changed, 185 insertions(+)
create mode 100644 include/uapi/linux/virtio_spi.h
diff --git a/include/uapi/linux/virtio_spi.h b/include/uapi/linux/virtio_spi.h
new file mode 100644
index 000000000000..1cb6da912345
--- /dev/null
+++ b/include/uapi/linux/virtio_spi.h
@@ -0,0 +1,185 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Copyright (C) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+#ifndef _LINUX_VIRTIO_VIRTIO_SPI_H
+#define _LINUX_VIRTIO_VIRTIO_SPI_H
+
+#include <linux/types.h>
+#include <linux/virtio_config.h>
+#include <linux/virtio_ids.h>
+#include <linux/virtio_types.h>
+
+/* Sample data on trailing clock edge */
+#define VIRTIO_SPI_CPHA (1 << 0)
+/* Clock is high when IDLE */
+#define VIRTIO_SPI_CPOL (1 << 1)
+/* Chip Select is active high */
+#define VIRTIO_SPI_CS_HIGH (1 << 2)
+/* Transmit LSB first */
+#define VIRTIO_SPI_MODE_LSB_FIRST (1 << 3)
+/* Loopback mode */
+#define VIRTIO_SPI_MODE_LOOP (1 << 4)
+
+/*
+ * All config fields are read-only for the Virtio SPI driver
+ *
+ * @cs_max_number: maximum number of chipselect the host SPI controller
+ * supports.
+ * @cs_change_supported: indicates if the host SPI controller supports to toggle
+ * chipselect after each transfer in one message:
+ * 0: unsupported, chipselect will be kept in active state throughout the
+ * message transaction;
+ * 1: supported.
+ * Note: Message here contains a sequence of SPI transfers.
+ * @tx_nbits_supported: indicates the supported number of bit for writing:
+ * bit 0: DUAL (2-bit transfer), 1 for supported
+ * bit 1: QUAD (4-bit transfer), 1 for supported
+ * bit 2: OCTAL (8-bit transfer), 1 for supported
+ * other bits are reserved as 0, 1-bit transfer is always supported.
+ * @rx_nbits_supported: indicates the supported number of bit for reading:
+ * bit 0: DUAL (2-bit transfer), 1 for supported
+ * bit 1: QUAD (4-bit transfer), 1 for supported
+ * bit 2: OCTAL (8-bit transfer), 1 for supported
+ * other bits are reserved as 0, 1-bit transfer is always supported.
+ * @bits_per_word_mask: mask indicating which values of bits_per_word are
+ * supported. If not set, no limitation for bits_per_word.
+ * @mode_func_supported: indicates the following features are supported or not:
+ * bit 0-1: CPHA feature
+ * 0b00: invalid, should support as least one CPHA setting
+ * 0b01: supports CPHA=0 only
+ * 0b10: supports CPHA=1 only
+ * 0b11: supports CPHA=0 and CPHA=1.
+ * bit 2-3: CPOL feature
+ * 0b00: invalid, should support as least one CPOL setting
+ * 0b01: supports CPOL=0 only
+ * 0b10: supports CPOL=1 only
+ * 0b11: supports CPOL=0 and CPOL=1.
+ * bit 4: chipselect active high feature, 0 for unsupported and 1 for
+ * supported, chipselect active low should always be supported.
+ * bit 5: LSB first feature, 0 for unsupported and 1 for supported,
+ * MSB first should always be supported.
+ * bit 6: loopback mode feature, 0 for unsupported and 1 for supported,
+ * normal mode should always be supported.
+ * @max_freq_hz: the maximum clock rate supported in Hz unit, 0 means no
+ * limitation for transfer speed.
+ * @max_word_delay_ns: the maximum word delay supported in ns unit,
+ * 0 means word delay feature is unsupported.
+ * Note: Just as one message contains a sequence of transfers,
+ * one transfer may contain a sequence of words.
+ * @max_cs_setup_ns: the maximum delay supported after chipselect is asserted,
+ * in ns unit, 0 means delay is not supported to introduce after chipselect is
+ * asserted.
+ * @max_cs_hold_ns: the maximum delay supported before chipselect is deasserted,
+ * in ns unit, 0 means delay is not supported to introduce before chipselect
+ * is deasserted.
+ * @max_cs_incative_ns: maximum delay supported after chipselect is deasserted,
+ * in ns unit, 0 means delay is not supported to introduce after chipselect is
+ * deasserted.
+ */
+struct virtio_spi_config {
+ /* # of /dev/spidev<bus_num>.CS with CS=0..chip_select_max_number -1 */
+ __u8 cs_max_number;
+ __u8 cs_change_supported;
+#define VIRTIO_SPI_RX_TX_SUPPORT_DUAL (1 << 0)
+#define VIRTIO_SPI_RX_TX_SUPPORT_QUAD (1 << 1)
+#define VIRTIO_SPI_RX_TX_SUPPORT_OCTAL (1 << 2)
+ __u8 tx_nbits_supported;
+ __u8 rx_nbits_supported;
+ __le32 bits_per_word_mask;
+#define VIRTIO_SPI_MF_SUPPORT_CPHA_0 (1 << 0)
+#define VIRTIO_SPI_MF_SUPPORT_CPHA_1 (1 << 1)
+#define VIRTIO_SPI_MF_SUPPORT_CPOL_0 (1 << 2)
+#define VIRTIO_SPI_MF_SUPPORT_CPOL_1 (1 << 3)
+#define VIRTIO_SPI_MF_SUPPORT_CS_HIGH (1 << 4)
+#define VIRTIO_SPI_MF_SUPPORT_LSB_FIRST (1 << 5)
+#define VIRTIO_SPI_MF_SUPPORT_LOOPBACK (1 << 6)
+ __le32 mode_func_supported;
+ __le32 max_freq_hz;
+ __le32 max_word_delay_ns;
+ __le32 max_cs_setup_ns;
+ __le32 max_cs_hold_ns;
+ __le32 max_cs_inactive_ns;
+};
+
+/*
+ * @chip_select_id: chipselect index the SPI transfer used.
+ *
+ * @bits_per_word: the number of bits in each SPI transfer word.
+ *
+ * @cs_change: whether to deselect device after finishing this transfer
+ * before starting the next transfer, 0 means cs keep asserted and
+ * 1 means cs deasserted then asserted again.
+ *
+ * @tx_nbits: bus width for write transfer.
+ * 0,1: bus width is 1, also known as SINGLE
+ * 2 : bus width is 2, also known as DUAL
+ * 4 : bus width is 4, also known as QUAD
+ * 8 : bus width is 8, also known as OCTAL
+ * other values are invalid.
+ *
+ * @rx_nbits: bus width for read transfer.
+ * 0,1: bus width is 1, also known as SINGLE
+ * 2 : bus width is 2, also known as DUAL
+ * 4 : bus width is 4, also known as QUAD
+ * 8 : bus width is 8, also known as OCTAL
+ * other values are invalid.
+ *
+ * @reserved: for future use.
+ *
+ * @mode: SPI transfer mode.
+ * bit 0: CPHA, determines the timing (i.e. phase) of the data
+ * bits relative to the clock pulses.For CPHA=0, the
+ * "out" side changes the data on the trailing edge of the
+ * preceding clock cycle, while the "in" side captures the data
+ * on (or shortly after) the leading edge of the clock cycle.
+ * For CPHA=1, the "out" side changes the data on the leading
+ * edge of the current clock cycle, while the "in" side
+ * captures the data on (or shortly after) the trailing edge of
+ * the clock cycle.
+ * bit 1: CPOL, determines the polarity of the clock. CPOL=0 is a
+ * clock which idles at 0, and each cycle consists of a pulse
+ * of 1. CPOL=1 is a clock which idles at 1, and each cycle
+ * consists of a pulse of 0.
+ * bit 2: CS_HIGH, if 1, chip select active high, else active low.
+ * bit 3: LSB_FIRST, determines per-word bits-on-wire, if 0, MSB
+ * first, else LSB first.
+ * bit 4: LOOP, loopback mode.
+ *
+ * @freq: the transfer speed in Hz.
+ *
+ * @word_delay_ns: delay to be inserted between consecutive words of a
+ * transfer, in ns unit.
+ *
+ * @cs_setup_ns: delay to be introduced after CS is asserted, in ns
+ * unit.
+ *
+ * @cs_delay_hold_ns: delay to be introduced before CS is deasserted
+ * for each transfer, in ns unit.
+ *
+ * @cs_change_delay_inactive_ns: delay to be introduced after CS is
+ * deasserted and before next asserted, in ns unit.
+ */
+struct spi_transfer_head {
+ __u8 chip_select_id;
+ __u8 bits_per_word;
+ __u8 cs_change;
+ __u8 tx_nbits;
+ __u8 rx_nbits;
+ __u8 reserved[3];
+ __le32 mode;
+ __le32 freq;
+ __le32 word_delay_ns;
+ __le32 cs_setup_ns;
+ __le32 cs_delay_hold_ns;
+ __le32 cs_change_delay_inactive_ns;
+};
+
+struct spi_transfer_result {
+#define VIRTIO_SPI_TRANS_OK 0
+#define VIRTIO_SPI_PARAM_ERR 1
+#define VIRTIO_SPI_TRANS_ERR 2
+ u8 result;
+};
+
+#endif /* #ifndef _LINUX_VIRTIO_VIRTIO_SPI_H */
--
2.34.1On Tue, Apr 01, 2025 at 11:36:20AM +0800, Haixu Cui wrote: > Add virtio-spi.h header for virtio SPI. ... > +/* All comments look like kernel-doc, but miss the proper annotation. Why? > + * All config fields are read-only for the Virtio SPI driver > + * > + * @cs_max_number: maximum number of chipselect the host SPI controller > + * supports. > + * @cs_change_supported: indicates if the host SPI controller supports to toggle > + * chipselect after each transfer in one message: > + * 0: unsupported, chipselect will be kept in active state throughout the > + * message transaction; > + * 1: supported. > + * Note: Message here contains a sequence of SPI transfers. > + * @tx_nbits_supported: indicates the supported number of bit for writing: > + * bit 0: DUAL (2-bit transfer), 1 for supported > + * bit 1: QUAD (4-bit transfer), 1 for supported > + * bit 2: OCTAL (8-bit transfer), 1 for supported > + * other bits are reserved as 0, 1-bit transfer is always supported. > + * @rx_nbits_supported: indicates the supported number of bit for reading: > + * bit 0: DUAL (2-bit transfer), 1 for supported > + * bit 1: QUAD (4-bit transfer), 1 for supported > + * bit 2: OCTAL (8-bit transfer), 1 for supported > + * other bits are reserved as 0, 1-bit transfer is always supported. > + * @bits_per_word_mask: mask indicating which values of bits_per_word are > + * supported. If not set, no limitation for bits_per_word. > + * @mode_func_supported: indicates the following features are supported or not: > + * bit 0-1: CPHA feature > + * 0b00: invalid, should support as least one CPHA setting > + * 0b01: supports CPHA=0 only > + * 0b10: supports CPHA=1 only > + * 0b11: supports CPHA=0 and CPHA=1. > + * bit 2-3: CPOL feature > + * 0b00: invalid, should support as least one CPOL setting > + * 0b01: supports CPOL=0 only > + * 0b10: supports CPOL=1 only > + * 0b11: supports CPOL=0 and CPOL=1. > + * bit 4: chipselect active high feature, 0 for unsupported and 1 for > + * supported, chipselect active low should always be supported. > + * bit 5: LSB first feature, 0 for unsupported and 1 for supported, > + * MSB first should always be supported. > + * bit 6: loopback mode feature, 0 for unsupported and 1 for supported, > + * normal mode should always be supported. > + * @max_freq_hz: the maximum clock rate supported in Hz unit, 0 means no > + * limitation for transfer speed. > + * @max_word_delay_ns: the maximum word delay supported in ns unit, > + * 0 means word delay feature is unsupported. > + * Note: Just as one message contains a sequence of transfers, > + * one transfer may contain a sequence of words. > + * @max_cs_setup_ns: the maximum delay supported after chipselect is asserted, > + * in ns unit, 0 means delay is not supported to introduce after chipselect is > + * asserted. > + * @max_cs_hold_ns: the maximum delay supported before chipselect is deasserted, > + * in ns unit, 0 means delay is not supported to introduce before chipselect > + * is deasserted. > + * @max_cs_incative_ns: maximum delay supported after chipselect is deasserted, > + * in ns unit, 0 means delay is not supported to introduce after chipselect is > + * deasserted. > + */ ... > + u8 result; Shouldn't all types in UAPI be double underscored? -- With Best Regards, Andy Shevchenko
On 4/1/2025 9:06 AM, Haixu Cui wrote:
> Add virtio-spi.h header for virtio SPI.
>
> Signed-off-by: Haixu Cui <quic_haixcui@quicinc.com>
> ---
> include/uapi/linux/virtio_spi.h | 185 ++++++++++++++++++++++++++++++++
> 1 file changed, 185 insertions(+)
> create mode 100644 include/uapi/linux/virtio_spi.h
>
> diff --git a/include/uapi/linux/virtio_spi.h b/include/uapi/linux/virtio_spi.h
> new file mode 100644
> index 000000000000..1cb6da912345
> --- /dev/null
> +++ b/include/uapi/linux/virtio_spi.h
> @@ -0,0 +1,185 @@
> +/* SPDX-License-Identifier: BSD-3-Clause */
> +/*
> + * Copyright (C) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +#ifndef _LINUX_VIRTIO_VIRTIO_SPI_H
> +#define _LINUX_VIRTIO_VIRTIO_SPI_H
> +
> +#include <linux/types.h>
> +#include <linux/virtio_config.h>
> +#include <linux/virtio_ids.h>
> +#include <linux/virtio_types.h>
> +
> +/* Sample data on trailing clock edge */
> +#define VIRTIO_SPI_CPHA (1 << 0)
> +/* Clock is high when IDLE */
> +#define VIRTIO_SPI_CPOL (1 << 1)
> +/* Chip Select is active high */
> +#define VIRTIO_SPI_CS_HIGH (1 << 2)
> +/* Transmit LSB first */
> +#define VIRTIO_SPI_MODE_LSB_FIRST (1 << 3)
> +/* Loopback mode */
> +#define VIRTIO_SPI_MODE_LOOP (1 << 4)
> +
> +/*
> + * All config fields are read-only for the Virtio SPI driver
> + *
> + * @cs_max_number: maximum number of chipselect the host SPI controller
> + * supports.
> + * @cs_change_supported: indicates if the host SPI controller supports to toggle
> + * chipselect after each transfer in one message:
> + * 0: unsupported, chipselect will be kept in active state throughout the
> + * message transaction;
> + * 1: supported.
> + * Note: Message here contains a sequence of SPI transfers.
> + * @tx_nbits_supported: indicates the supported number of bit for writing:
> + * bit 0: DUAL (2-bit transfer), 1 for supported
> + * bit 1: QUAD (4-bit transfer), 1 for supported
> + * bit 2: OCTAL (8-bit transfer), 1 for supported
> + * other bits are reserved as 0, 1-bit transfer is always supported.
> + * @rx_nbits_supported: indicates the supported number of bit for reading:
> + * bit 0: DUAL (2-bit transfer), 1 for supported
> + * bit 1: QUAD (4-bit transfer), 1 for supported
> + * bit 2: OCTAL (8-bit transfer), 1 for supported
> + * other bits are reserved as 0, 1-bit transfer is always supported.
> + * @bits_per_word_mask: mask indicating which values of bits_per_word are
> + * supported. If not set, no limitation for bits_per_word.
> + * @mode_func_supported: indicates the following features are supported or not:
> + * bit 0-1: CPHA feature
> + * 0b00: invalid, should support as least one CPHA setting
> + * 0b01: supports CPHA=0 only
> + * 0b10: supports CPHA=1 only
> + * 0b11: supports CPHA=0 and CPHA=1.
> + * bit 2-3: CPOL feature
> + * 0b00: invalid, should support as least one CPOL setting
> + * 0b01: supports CPOL=0 only
> + * 0b10: supports CPOL=1 only
> + * 0b11: supports CPOL=0 and CPOL=1.
> + * bit 4: chipselect active high feature, 0 for unsupported and 1 for
> + * supported, chipselect active low should always be supported.
> + * bit 5: LSB first feature, 0 for unsupported and 1 for supported,
> + * MSB first should always be supported.
> + * bit 6: loopback mode feature, 0 for unsupported and 1 for supported,
> + * normal mode should always be supported.
> + * @max_freq_hz: the maximum clock rate supported in Hz unit, 0 means no
> + * limitation for transfer speed.
> + * @max_word_delay_ns: the maximum word delay supported in ns unit,
> + * 0 means word delay feature is unsupported.
> + * Note: Just as one message contains a sequence of transfers,
> + * one transfer may contain a sequence of words.
Instead of adding "Note:", can we update it like this?
@max_word_delay_ns: Maximum word delay supported, in nanoseconds.
A value of 0 indicates that word delay is unsupported.
Each transfer may consist of a sequence of words.
> + * @max_cs_setup_ns: the maximum delay supported after chipselect is asserted,
> + * in ns unit, 0 means delay is not supported to introduce after chipselect is
> + * asserted.
> + * @max_cs_hold_ns: the maximum delay supported before chipselect is deasserted,
> + * in ns unit, 0 means delay is not supported to introduce before chipselect
> + * is deasserted.
> + * @max_cs_incative_ns: maximum delay supported after chipselect is deasserted,
> + * in ns unit, 0 means delay is not supported to introduce after chipselect is
> + * deasserted.
> + */
> +struct virtio_spi_config {
> + /* # of /dev/spidev<bus_num>.CS with CS=0..chip_select_max_number -1 */
> + __u8 cs_max_number;
> + __u8 cs_change_supported;
> +#define VIRTIO_SPI_RX_TX_SUPPORT_DUAL (1 << 0)
> +#define VIRTIO_SPI_RX_TX_SUPPORT_QUAD (1 << 1)
> +#define VIRTIO_SPI_RX_TX_SUPPORT_OCTAL (1 << 2)
> + __u8 tx_nbits_supported;
> + __u8 rx_nbits_supported;
> + __le32 bits_per_word_mask;
> +#define VIRTIO_SPI_MF_SUPPORT_CPHA_0 (1 << 0)
> +#define VIRTIO_SPI_MF_SUPPORT_CPHA_1 (1 << 1)
> +#define VIRTIO_SPI_MF_SUPPORT_CPOL_0 (1 << 2)
> +#define VIRTIO_SPI_MF_SUPPORT_CPOL_1 (1 << 3)
> +#define VIRTIO_SPI_MF_SUPPORT_CS_HIGH (1 << 4)
> +#define VIRTIO_SPI_MF_SUPPORT_LSB_FIRST (1 << 5)
> +#define VIRTIO_SPI_MF_SUPPORT_LOOPBACK (1 << 6)
> + __le32 mode_func_supported;
> + __le32 max_freq_hz;
> + __le32 max_word_delay_ns;
> + __le32 max_cs_setup_ns;
> + __le32 max_cs_hold_ns;
> + __le32 max_cs_inactive_ns;
> +};
> +
> +/*
> + * @chip_select_id: chipselect index the SPI transfer used.
> + *
> + * @bits_per_word: the number of bits in each SPI transfer word.
> + *
> + * @cs_change: whether to deselect device after finishing this transfer
> + * before starting the next transfer, 0 means cs keep asserted and
> + * 1 means cs deasserted then asserted again.
> + *
> + * @tx_nbits: bus width for write transfer.
> + * 0,1: bus width is 1, also known as SINGLE
Do you mean to say that a value of 0 defaults to SINGLE?> + * 2 :
bus width is 2, also known as DUAL
> + * 4 : bus width is 4, also known as QUAD
> + * 8 : bus width is 8, also known as OCTAL
> + * other values are invalid.
> + *
> + * @rx_nbits: bus width for read transfer.
> + * 0,1: bus width is 1, also known as SINGLE
> + * 2 : bus width is 2, also known as DUAL
> + * 4 : bus width is 4, also known as QUAD
> + * 8 : bus width is 8, also known as OCTAL
> + * other values are invalid.
> + *
> + * @reserved: for future use.
> + *
> + * @mode: SPI transfer mode.
> + * bit 0: CPHA, determines the timing (i.e. phase) of the data
> + * bits relative to the clock pulses.For CPHA=0, the
> + * "out" side changes the data on the trailing edge of the
> + * preceding clock cycle, while the "in" side captures the data
> + * on (or shortly after) the leading edge of the clock cycle.
> + * For CPHA=1, the "out" side changes the data on the leading
> + * edge of the current clock cycle, while the "in" side
> + * captures the data on (or shortly after) the trailing edge of
> + * the clock cycle.
> + * bit 1: CPOL, determines the polarity of the clock. CPOL=0 is a
> + * clock which idles at 0, and each cycle consists of a pulse
> + * of 1. CPOL=1 is a clock which idles at 1, and each cycle
> + * consists of a pulse of 0.
> + * bit 2: CS_HIGH, if 1, chip select active high, else active low.
> + * bit 3: LSB_FIRST, determines per-word bits-on-wire, if 0, MSB
> + * first, else LSB first.
> + * bit 4: LOOP, loopback mode.
> + *
> + * @freq: the transfer speed in Hz.
> + *
> + * @word_delay_ns: delay to be inserted between consecutive words of a
> + * transfer, in ns unit.
> + *
> + * @cs_setup_ns: delay to be introduced after CS is asserted, in ns
> + * unit.
> + *
> + * @cs_delay_hold_ns: delay to be introduced before CS is deasserted
> + * for each transfer, in ns unit.
> + *
> + * @cs_change_delay_inactive_ns: delay to be introduced after CS is
> + * deasserted and before next asserted, in ns unit.
> + */
> +struct spi_transfer_head {
> + __u8 chip_select_id;
> + __u8 bits_per_word;
> + __u8 cs_change;
> + __u8 tx_nbits;
> + __u8 rx_nbits;
> + __u8 reserved[3];
> + __le32 mode;
> + __le32 freq;
> + __le32 word_delay_ns;
> + __le32 cs_setup_ns;
> + __le32 cs_delay_hold_ns;
> + __le32 cs_change_delay_inactive_ns;
> +};
> +
> +struct spi_transfer_result {
> +#define VIRTIO_SPI_TRANS_OK 0
> +#define VIRTIO_SPI_PARAM_ERR 1
> +#define VIRTIO_SPI_TRANS_ERR 2
> + u8 result;
> +};
> +
> +#endif /* #ifndef _LINUX_VIRTIO_VIRTIO_SPI_H */
Hi Joythi,
Thanks for your feedback, please refer to my below response.
> Instead of adding "Note:", can we update it like this?
>
> @max_word_delay_ns: Maximum word delay supported, in nanoseconds.
> A value of 0 indicates that word delay is unsupported.
> Each transfer may consist of a sequence of words.
>
Yes, will update as you suggestion.
>> + *
>> + * @tx_nbits: bus width for write transfer.
>> + * 0,1: bus width is 1, also known as SINGLE
> Do you mean to say that a value of 0 defaults to SINGLE?> + * 2 :
> bus width is 2, also known as DUAL
Yes, a value of 0 or 1 both indicate single-line transfer.
Regards
Haixu Cui
Thanks Haixu ! Important changes.
On 4/1/2025 9:06 AM, Haixu Cui wrote:
[...]
> +/*
> + * All config fields are read-only for the Virtio SPI driver
> + *
> + * @cs_max_number: maximum number of chipselect the host SPI controller
> + * supports.
> + * @cs_change_supported: indicates if the host SPI controller supports to toggle
> + * chipselect after each transfer in one message:
> + * 0: unsupported, chipselect will be kept in active state throughout the
> + * message transaction;
> + * 1: supported.
> + * Note: Message here contains a sequence of SPI transfers.
> + * @tx_nbits_supported: indicates the supported number of bit for writing:
> + * bit 0: DUAL (2-bit transfer), 1 for supported
> + * bit 1: QUAD (4-bit transfer), 1 for supported
> + * bit 2: OCTAL (8-bit transfer), 1 for supported
> + * other bits are reserved as 0, 1-bit transfer is always supported.
> + * @rx_nbits_supported: indicates the supported number of bit for reading:
> + * bit 0: DUAL (2-bit transfer), 1 for supported
> + * bit 1: QUAD (4-bit transfer), 1 for supported
> + * bit 2: OCTAL (8-bit transfer), 1 for supported
> + * other bits are reserved as 0, 1-bit transfer is always supported.
> + * @bits_per_word_mask: mask indicating which values of bits_per_word are
> + * supported. If not set, no limitation for bits_per_word.
> + * @mode_func_supported: indicates the following features are supported or not:
mode_func_supported[b'6-0] : something like this may help to know size
of this variable.
> + * bit 0-1: CPHA feature
> + * 0b00: invalid, should support as least one CPHA setting
> + * 0b01: supports CPHA=0 only
> + * 0b10: supports CPHA=1 only
> + * 0b11: supports CPHA=0 and CPHA=1.
> + * bit 2-3: CPOL feature
> + * 0b00: invalid, should support as least one CPOL setting
> + * 0b01: supports CPOL=0 only
> + * 0b10: supports CPOL=1 only
> + * 0b11: supports CPOL=0 and CPOL=1.
> + * bit 4: chipselect active high feature, 0 for unsupported and 1 for
> + * supported, chipselect active low should always be supported.
You mean to say "chipselect active low is default supported" ?
Just thinking instead of keeping always supported, can we mentione as
default supported ?
> + * bit 5: LSB first feature, 0 for unsupported and 1 for supported,
> + * MSB first should always be supported.
MSB first is default supported ?
> + * bit 6: loopback mode feature, 0 for unsupported and 1 for supported,
> + * normal mode should always be supported.
we can reverse the write up for all "always be supported"
bit 6: if not specified, normal mode is supported by default. if set 1,
specifies loopback mode.
> + * @max_freq_hz: the maximum clock rate supported in Hz unit, 0 means no
> + * limitation for transfer speed.
> + * @max_word_delay_ns: the maximum word delay supported in ns unit,
> + * 0 means word delay feature is unsupported.
> + * Note: Just as one message contains a sequence of transfers,
> + * one transfer may contain a sequence of words.
> + * @max_cs_setup_ns: the maximum delay supported after chipselect is asserted,
> + * in ns unit, 0 means delay is not supported to introduce after chipselect is
> + * asserted.
> + * @max_cs_hold_ns: the maximum delay supported before chipselect is deasserted,
> + * in ns unit, 0 means delay is not supported to introduce before chipselect
> + * is deasserted.
> + * @max_cs_incative_ns: maximum delay supported after chipselect is deasserted,
> + * in ns unit, 0 means delay is not supported to introduce after chipselect is
> + * deasserted.
> + */
> +struct virtio_spi_config {
> + /* # of /dev/spidev<bus_num>.CS with CS=0..chip_select_max_number -1 */
> + __u8 cs_max_number;
> + __u8 cs_change_supported;
> +#define VIRTIO_SPI_RX_TX_SUPPORT_DUAL (1 << 0)
> +#define VIRTIO_SPI_RX_TX_SUPPORT_QUAD (1 << 1)
> +#define VIRTIO_SPI_RX_TX_SUPPORT_OCTAL (1 << 2)
Can use BIT(x) ?
> + __u8 tx_nbits_supported;
> + __u8 rx_nbits_supported;
> + __le32 bits_per_word_mask;
> +#define VIRTIO_SPI_MF_SUPPORT_CPHA_0 (1 << 0)
> +#define VIRTIO_SPI_MF_SUPPORT_CPHA_1 (1 << 1)
> +#define VIRTIO_SPI_MF_SUPPORT_CPOL_0 (1 << 2)
> +#define VIRTIO_SPI_MF_SUPPORT_CPOL_1 (1 << 3)
> +#define VIRTIO_SPI_MF_SUPPORT_CS_HIGH (1 << 4)
> +#define VIRTIO_SPI_MF_SUPPORT_LSB_FIRST (1 << 5)
> +#define VIRTIO_SPI_MF_SUPPORT_LOOPBACK (1 << 6)
All with BIT(x) ?
> + __le32 mode_func_supported;
> + __le32 max_freq_hz;
> + __le32 max_word_delay_ns;
> + __le32 max_cs_setup_ns;
> + __le32 max_cs_hold_ns;
> + __le32 max_cs_inactive_ns;
> +};
[...]
> +
> +#endif /* #ifndef _LINUX_VIRTIO_VIRTIO_SPI_H */
On Tue, Apr 22, 2025 at 11:33:42AM +0530, Mukesh Kumar Savaliya wrote:
> On 4/1/2025 9:06 AM, Haixu Cui wrote:
[...]
> > +struct virtio_spi_config {
> > + /* # of /dev/spidev<bus_num>.CS with CS=0..chip_select_max_number -1 */
> > + __u8 cs_max_number;
> > + __u8 cs_change_supported;
> > +#define VIRTIO_SPI_RX_TX_SUPPORT_DUAL (1 << 0)
> > +#define VIRTIO_SPI_RX_TX_SUPPORT_QUAD (1 << 1)
> > +#define VIRTIO_SPI_RX_TX_SUPPORT_OCTAL (1 << 2)
> Can use BIT(x) ?
No.
> > + __u8 tx_nbits_supported;
> > + __u8 rx_nbits_supported;
> > + __le32 bits_per_word_mask;
> > +#define VIRTIO_SPI_MF_SUPPORT_CPHA_0 (1 << 0)
> > +#define VIRTIO_SPI_MF_SUPPORT_CPHA_1 (1 << 1)
> > +#define VIRTIO_SPI_MF_SUPPORT_CPOL_0 (1 << 2)
> > +#define VIRTIO_SPI_MF_SUPPORT_CPOL_1 (1 << 3)
> > +#define VIRTIO_SPI_MF_SUPPORT_CS_HIGH (1 << 4)
> > +#define VIRTIO_SPI_MF_SUPPORT_LSB_FIRST (1 << 5)
> > +#define VIRTIO_SPI_MF_SUPPORT_LOOPBACK (1 << 6)
> All with BIT(x) ?
No. There is no such macro in UAPI. There is another one available, though.
Check the spi.h UAPI header for the details.
> > + __le32 mode_func_supported;
> > + __le32 max_freq_hz;
> > + __le32 max_word_delay_ns;
> > + __le32 max_cs_setup_ns;
> > + __le32 max_cs_hold_ns;
> > + __le32 max_cs_inactive_ns;
> > +};
--
With Best Regards,
Andy Shevchenko
Hi Mukesh, >> + * @mode_func_supported: indicates the following features are >> supported or not: > mode_func_supported[b'6-0] : something like this may help to know size > of this variable. I noticed the suggestion to use [b'6-0] to indicate the actual size of the mode_func_supported variable. However I haven't seen notation like [b'6-0] used in Linux kernel. And I think the definition of its bitfield below could clearly indicates that 7 bits of mode_func_supported are used. Could we keep the current description as it is? >> + * bit 0-1: CPHA feature >> + * 0b00: invalid, should support as least one CPHA setting >> + * 0b01: supports CPHA=0 only >> + * 0b10: supports CPHA=1 only >> + * 0b11: supports CPHA=0 and CPHA=1. >> + * bit 2-3: CPOL feature >> + * 0b00: invalid, should support as least one CPOL setting >> + * 0b01: supports CPOL=0 only >> + * 0b10: supports CPOL=1 only >> + * 0b11: supports CPOL=0 and CPOL=1. >> + * bit 4: chipselect active high feature, 0 for unsupported and 1 for >> + * supported, chipselect active low should always be supported. > You mean to say "chipselect active low is default supported" ? > > Just thinking instead of keeping always supported, can we mentione as > default supported ? Yes, will update as "chipselect active low is supported by default". > >> + * bit 5: LSB first feature, 0 for unsupported and 1 for supported, >> + * MSB first should always be supported. > MSB first is default supported ? Yes. >> + * bit 6: loopback mode feature, 0 for unsupported and 1 for >> supported, >> + * normal mode should always be supported. > we can reverse the write up for all "always be supported" > > bit 6: if not specified, normal mode is supported by default. if set 1, > specifies loopback mode. Sure, your statement is indeed clearer and more accurate, I will update in next patch. >> +#define VIRTIO_SPI_RX_TX_SUPPORT_DUAL (1 << 0) >> +#define VIRTIO_SPI_RX_TX_SUPPORT_QUAD (1 << 1) >> +#define VIRTIO_SPI_RX_TX_SUPPORT_OCTAL (1 << 2) > Can use BIT(x) ? Will update the code accordingly: #define VIRTIO_SPI_RX_TX_SUPPORT_DUAL BIT(0) #define VIRTIO_SPI_RX_TX_SUPPORT_QUAD BIT(1) Really Appreciate. Best Regards Haixu Cui
On Fri, Apr 25, 2025 at 04:24:25PM +0800, Haixu Cui wrote: ... 1 > > > +#define VIRTIO_SPI_RX_TX_SUPPORT_DUAL (1 << 0) > > > +#define VIRTIO_SPI_RX_TX_SUPPORT_QUAD (1 << 1) > > > +#define VIRTIO_SPI_RX_TX_SUPPORT_OCTAL (1 << 2) > > Can use BIT(x) ? > Will update the code accordingly: > #define VIRTIO_SPI_RX_TX_SUPPORT_DUAL BIT(0) > #define VIRTIO_SPI_RX_TX_SUPPORT_QUAD BIT(1) Please, do not do this. I explained more in the previous reply why. -- With Best Regards, Andy Shevchenko
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