Hi all,

This set addresses two issues in the current MI300A solution.

Patch 1:
The row retirement flow is updated to iterate over an additional bit.
Without this, only half of the affected addresses are calculated.

Patch 2:
The record keeping flow is updated to match only on unique address bits
of interest. Without this, multiple records can be created for the same
event. For example, for row retirement, there will be a record that
includes column bit 0, another record for column bit 1, etc., even
though these are part of the same row retirement event.

Thanks,
Yazen
 

---
Yazen Ghannam (2):
      RAS/AMD/ATL: Include row[13] bit in row retirement
      RAS/AMD/{ATL,FMPM}: Get masked address

 drivers/ras/amd/atl/umc.c | 33 ++++++++++++++++++++++++++++++++-
 drivers/ras/amd/fmpm.c    |  2 +-
 include/linux/ras.h       |  2 ++
 3 files changed, 35 insertions(+), 2 deletions(-)
---
base-commit: ff719e243db5de2ca595bf4e2ab6ad530a08f378
change-id: 20250308-fix-fmpm-extra-records-de44d3956d9d