The description is similar to the one used with the new CPSW driver.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
---
Changes for v2:
- Remove properties which are common for the imx28(7) SoC
- Use mdio properties to perform L2 switch reset (avoid using
  deprecated properties)

Changes for v3:
- Replace IRQ_TYPE_EDGE_FALLING with IRQ_TYPE_LEVEL_LOW
- Update comment regarding PHY interrupts s/AND/OR/g
---
 arch/arm/boot/dts/nxp/mxs/imx28-xea.dts | 54 +++++++++++++++++++++++++
 1 file changed, 54 insertions(+)

diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-xea.dts b/arch/arm/boot/dts/nxp/mxs/imx28-xea.dts
index 6c5e6856648a..8642578fddf3 100644
--- a/arch/arm/boot/dts/nxp/mxs/imx28-xea.dts
+++ b/arch/arm/boot/dts/nxp/mxs/imx28-xea.dts
@@ -5,6 +5,7 @@
  */
 
 /dts-v1/;
+#include<dt-bindings/interrupt-controller/irq.h>
 #include "imx28-lwe.dtsi"
 
 / {
@@ -90,6 +91,59 @@ &reg_usb_5v {
 	gpio = <&gpio0 2 0>;
 };
 
+&eth_switch {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mac0_pins_a>, <&mac1_pins_a>;
+	phy-supply = <&reg_fec_3v3>;
+	status = "okay";
+
+	ethernet-ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		mtip_port1: port@1 {
+			reg = <1>;
+			label = "lan0";
+			local-mac-address = [ 00 00 00 00 00 00 ];
+			phy-mode = "rmii";
+			phy-handle = <&ethphy0>;
+		};
+
+		mtip_port2: port@2 {
+			reg = <2>;
+			label = "lan1";
+			local-mac-address = [ 00 00 00 00 00 00 ];
+			phy-mode = "rmii";
+			phy-handle = <&ethphy1>;
+		};
+	};
+
+	mdio_sw: mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		reset-gpios = <&gpio3 21 0>;
+		reset-delay-us = <25000>;
+		reset-post-delay-us = <10000>;
+
+		ethphy0: ethernet-phy@0 {
+			reg = <0>;
+			smsc,disable-energy-detect;
+			/* Both PHYs (i.e. 0,1) have the same, single GPIO, */
+			/* line to handle both, their interrupts (OR'ed) */
+			interrupt-parent = <&gpio4>;
+			interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
+		};
+
+		ethphy1: ethernet-phy@1 {
+			reg = <1>;
+			smsc,disable-energy-detect;
+			interrupt-parent = <&gpio4>;
+			interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
+		};
+	};
+};
+
 &spi2_pins_a {
 	fsl,pinmux-ids = <
 		MX28_PAD_SSP2_SCK__SSP2_SCK
-- 
2.39.5

Hi,

Am 31.03.25 um 12:31 schrieb Lukasz Majewski:
> The description is similar to the one used with the new CPSW driver.
>
> Signed-off-by: Lukasz Majewski <lukma@denx.de>
> ---
> Changes for v2:
> - Remove properties which are common for the imx28(7) SoC
> - Use mdio properties to perform L2 switch reset (avoid using
>    deprecated properties)
>
> Changes for v3:
> - Replace IRQ_TYPE_EDGE_FALLING with IRQ_TYPE_LEVEL_LOW
> - Update comment regarding PHY interrupts s/AND/OR/g
> ---
>   arch/arm/boot/dts/nxp/mxs/imx28-xea.dts | 54 +++++++++++++++++++++++++
>   1 file changed, 54 insertions(+)
>
> diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-xea.dts b/arch/arm/boot/dts/nxp/mxs/imx28-xea.dts
> index 6c5e6856648a..8642578fddf3 100644
> --- a/arch/arm/boot/dts/nxp/mxs/imx28-xea.dts
> +++ b/arch/arm/boot/dts/nxp/mxs/imx28-xea.dts
> @@ -5,6 +5,7 @@
>    */
>
>   /dts-v1/;
> +#include<dt-bindings/interrupt-controller/irq.h>
>   #include "imx28-lwe.dtsi"
>
>   / {
> @@ -90,6 +91,59 @@ &reg_usb_5v {
>   	gpio = <&gpio0 2 0>;
>   };
>
> +&eth_switch {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&mac0_pins_a>, <&mac1_pins_a>;
> +	phy-supply = <&reg_fec_3v3>;
> +	status = "okay";
> +
> +	ethernet-ports {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		mtip_port1: port@1 {
> +			reg = <1>;
> +			label = "lan0";
> +			local-mac-address = [ 00 00 00 00 00 00 ];
> +			phy-mode = "rmii";
> +			phy-handle = <&ethphy0>;
> +		};
> +
> +		mtip_port2: port@2 {
> +			reg = <2>;
> +			label = "lan1";
> +			local-mac-address = [ 00 00 00 00 00 00 ];
> +			phy-mode = "rmii";
> +			phy-handle = <&ethphy1>;
> +		};
> +	};
> +
> +	mdio_sw: mdio {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		reset-gpios = <&gpio3 21 0>;
i'm a huge fan of the polarity defines, which makes it easier to understand.

Btw since you introduced the compatible in the DTS of a i.MX28 board, it
would be nice to also enable the driver in mxs_defconfig.

Regards
> +		reset-delay-us = <25000>;
> +		reset-post-delay-us = <10000>;
> +
> +		ethphy0: ethernet-phy@0 {
> +			reg = <0>;
> +			smsc,disable-energy-detect;
> +			/* Both PHYs (i.e. 0,1) have the same, single GPIO, */
> +			/* line to handle both, their interrupts (OR'ed) */
> +			interrupt-parent = <&gpio4>;
> +			interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
> +		};
> +
> +		ethphy1: ethernet-phy@1 {
> +			reg = <1>;
> +			smsc,disable-energy-detect;
> +			interrupt-parent = <&gpio4>;
> +			interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
> +		};
> +	};
> +};
> +
>   &spi2_pins_a {
>   	fsl,pinmux-ids = <
>   		MX28_PAD_SSP2_SCK__SSP2_SCK

Hi Stefan,

> Hi,
> 
> Am 31.03.25 um 12:31 schrieb Lukasz Majewski:
> > The description is similar to the one used with the new CPSW driver.
> >
> > Signed-off-by: Lukasz Majewski <lukma@denx.de>
> > ---
> > Changes for v2:
> > - Remove properties which are common for the imx28(7) SoC
> > - Use mdio properties to perform L2 switch reset (avoid using
> >    deprecated properties)
> >
> > Changes for v3:
> > - Replace IRQ_TYPE_EDGE_FALLING with IRQ_TYPE_LEVEL_LOW
> > - Update comment regarding PHY interrupts s/AND/OR/g
> > ---
> >   arch/arm/boot/dts/nxp/mxs/imx28-xea.dts | 54
> > +++++++++++++++++++++++++ 1 file changed, 54 insertions(+)
> >
> > diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-xea.dts
> > b/arch/arm/boot/dts/nxp/mxs/imx28-xea.dts index
> > 6c5e6856648a..8642578fddf3 100644 ---
> > a/arch/arm/boot/dts/nxp/mxs/imx28-xea.dts +++
> > b/arch/arm/boot/dts/nxp/mxs/imx28-xea.dts @@ -5,6 +5,7 @@
> >    */
> >
> >   /dts-v1/;
> > +#include<dt-bindings/interrupt-controller/irq.h>
> >   #include "imx28-lwe.dtsi"
> >
> >   / {
> > @@ -90,6 +91,59 @@ &reg_usb_5v {
> >   	gpio = <&gpio0 2 0>;
> >   };
> >
> > +&eth_switch {
> > +	pinctrl-names = "default";
> > +	pinctrl-0 = <&mac0_pins_a>, <&mac1_pins_a>;
> > +	phy-supply = <&reg_fec_3v3>;
> > +	status = "okay";
> > +
> > +	ethernet-ports {
> > +		#address-cells = <1>;
> > +		#size-cells = <0>;
> > +
> > +		mtip_port1: port@1 {
> > +			reg = <1>;
> > +			label = "lan0";
> > +			local-mac-address = [ 00 00 00 00 00 00 ];
> > +			phy-mode = "rmii";
> > +			phy-handle = <&ethphy0>;
> > +		};
> > +
> > +		mtip_port2: port@2 {
> > +			reg = <2>;
> > +			label = "lan1";
> > +			local-mac-address = [ 00 00 00 00 00 00 ];
> > +			phy-mode = "rmii";
> > +			phy-handle = <&ethphy1>;
> > +		};
> > +	};
> > +
> > +	mdio_sw: mdio {
> > +		#address-cells = <1>;
> > +		#size-cells = <0>;
> > +
> > +		reset-gpios = <&gpio3 21 0>;  
> i'm a huge fan of the polarity defines, which makes it easier to
> understand.
> 

Ok.

> Btw since you introduced the compatible in the DTS of a i.MX28 board,
> it would be nice to also enable the driver in mxs_defconfig.

Yes, thanks for the tip.

> 
> Regards
> > +		reset-delay-us = <25000>;
> > +		reset-post-delay-us = <10000>;
> > +
> > +		ethphy0: ethernet-phy@0 {
> > +			reg = <0>;
> > +			smsc,disable-energy-detect;
> > +			/* Both PHYs (i.e. 0,1) have the same,
> > single GPIO, */
> > +			/* line to handle both, their interrupts
> > (OR'ed) */
> > +			interrupt-parent = <&gpio4>;
> > +			interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
> > +		};
> > +
> > +		ethphy1: ethernet-phy@1 {
> > +			reg = <1>;
> > +			smsc,disable-energy-detect;
> > +			interrupt-parent = <&gpio4>;
> > +			interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
> > +		};
> > +	};
> > +};
> > +
> >   &spi2_pins_a {
> >   	fsl,pinmux-ids = <
> >   		MX28_PAD_SSP2_SCK__SSP2_SCK  
> 


Best regards,

Lukasz Majewski

--

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