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[PATCH v2 4/4] PCI: j721e: Add support to build as a loadable module

Siddharth Vadapalli posted 4 patches 8 months, 3 weeks ago
There is a newer version of this series
[PATCH v2 4/4] PCI: j721e: Add support to build as a loadable module
Posted by Siddharth Vadapalli 8 months, 3 weeks ago 
The 'pci-j721e.c' driver is the application/glue/wrapper driver for the
Cadence PCIe Controllers on TI SoCs. Implement support for building it as a
loadable module.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---

v1:
https://lore.kernel.org/r/20250307103128.3287497-5-s-vadapalli@ti.com/
Changes since v1:
- Based on feedback from Thomas at:
  https://lore.kernel.org/r/88b3ecbe-32b6-4310-afb9-da19a2d0506a@bootlin.com/
  the "check" for a non-NULL "pcie-refclk" in j721e_pcie_remove() has been
  dropped.

Regards,
Siddharth.

 drivers/pci/controller/cadence/Kconfig     |  6 ++--
 drivers/pci/controller/cadence/pci-j721e.c | 33 +++++++++++++++++++++-
 2 files changed, 35 insertions(+), 4 deletions(-)

diff --git a/drivers/pci/controller/cadence/Kconfig b/drivers/pci/controller/cadence/Kconfig
index 82b58096eea0..72d7d264d6c3 100644
--- a/drivers/pci/controller/cadence/Kconfig
+++ b/drivers/pci/controller/cadence/Kconfig
@@ -43,10 +43,10 @@ config PCIE_CADENCE_PLAT_EP
 	  different vendors SoCs.
 
 config PCI_J721E
-	bool
+	tristate
 
 config PCI_J721E_HOST
-	bool "TI J721E PCIe controller (host mode)"
+	tristate "TI J721E PCIe controller (host mode)"
 	depends on ARCH_K3 || COMPILE_TEST
 	depends on OF
 	select PCIE_CADENCE_HOST
@@ -57,7 +57,7 @@ config PCI_J721E_HOST
 	  core.
 
 config PCI_J721E_EP
-	bool "TI J721E PCIe controller (endpoint mode)"
+	tristate "TI J721E PCIe controller (endpoint mode)"
 	depends on ARCH_K3 || COMPILE_TEST
 	depends on OF
 	depends on PCI_ENDPOINT
diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c
index ef1cfdae33bb..8bffcd31729c 100644
--- a/drivers/pci/controller/cadence/pci-j721e.c
+++ b/drivers/pci/controller/cadence/pci-j721e.c
@@ -15,6 +15,7 @@
 #include <linux/irqchip/chained_irq.h>
 #include <linux/irqdomain.h>
 #include <linux/mfd/syscon.h>
+#include <linux/module.h>
 #include <linux/of.h>
 #include <linux/pci.h>
 #include <linux/platform_device.h>
@@ -27,6 +28,7 @@
 #define cdns_pcie_to_rc(p) container_of(p, struct cdns_pcie_rc, pcie)
 
 #define ENABLE_REG_SYS_2	0x108
+#define ENABLE_CLR_REG_SYS_2	0x308
 #define STATUS_REG_SYS_2	0x508
 #define STATUS_CLR_REG_SYS_2	0x708
 #define LINK_DOWN		BIT(1)
@@ -116,6 +118,15 @@ static irqreturn_t j721e_pcie_link_irq_handler(int irq, void *priv)
 	return IRQ_HANDLED;
 }
 
+static void j721e_pcie_disable_link_irq(struct j721e_pcie *pcie)
+{
+	u32 reg;
+
+	reg = j721e_pcie_intd_readl(pcie, ENABLE_CLR_REG_SYS_2);
+	reg |= pcie->linkdown_irq_regfield;
+	j721e_pcie_intd_writel(pcie, ENABLE_CLR_REG_SYS_2, reg);
+}
+
 static void j721e_pcie_config_link_irq(struct j721e_pcie *pcie)
 {
 	u32 reg;
@@ -633,9 +644,25 @@ static void j721e_pcie_remove(struct platform_device *pdev)
 	struct j721e_pcie *pcie = platform_get_drvdata(pdev);
 	struct cdns_pcie *cdns_pcie = pcie->cdns_pcie;
 	struct device *dev = &pdev->dev;
+	struct cdns_pcie_ep *ep;
+	struct cdns_pcie_rc *rc;
+
+	if (pcie->mode == PCI_MODE_RC) {
+		rc = container_of(cdns_pcie, struct cdns_pcie_rc, pcie);
+		cdns_pcie_host_disable(rc);
+	} else {
+		ep = container_of(cdns_pcie, struct cdns_pcie_ep, pcie);
+		cdns_pcie_ep_disable(ep);
+	}
+
+	if (pcie->reset_gpio) {
+		msleep(PCIE_T_PVPERL_MS);
+		gpiod_set_value_cansleep(pcie->reset_gpio, 1);
+	}
 
 	clk_disable_unprepare(pcie->refclk);
 	cdns_pcie_disable_phy(cdns_pcie);
+	j721e_pcie_disable_link_irq(pcie);
 	pm_runtime_put(dev);
 	pm_runtime_disable(dev);
 }
@@ -730,4 +757,8 @@ static struct platform_driver j721e_pcie_driver = {
 		.pm	= pm_sleep_ptr(&j721e_pcie_pm_ops),
 	},
 };
-builtin_platform_driver(j721e_pcie_driver);
+module_platform_driver(j721e_pcie_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("PCIe controller driver for TI's J721E and related SoCs");
+MODULE_AUTHOR("Kishon Vijay Abraham I <kishon@ti.com>");
-- 
2.34.1
Re: [PATCH v2 4/4] PCI: j721e: Add support to build as a loadable module
Posted by Manivannan Sadhasivam 8 months, 2 weeks ago 
On Sun, Mar 30, 2025 at 02:09:14PM +0530, Siddharth Vadapalli wrote:
> The 'pci-j721e.c' driver is the application/glue/wrapper driver for the
> Cadence PCIe Controllers on TI SoCs. Implement support for building it as a
> loadable module.
> 
> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
> ---
> 
> v1:
> https://lore.kernel.org/r/20250307103128.3287497-5-s-vadapalli@ti.com/
> Changes since v1:
> - Based on feedback from Thomas at:
>   https://lore.kernel.org/r/88b3ecbe-32b6-4310-afb9-da19a2d0506a@bootlin.com/
>   the "check" for a non-NULL "pcie-refclk" in j721e_pcie_remove() has been
>   dropped.
> 
> Regards,
> Siddharth.
> 
>  drivers/pci/controller/cadence/Kconfig     |  6 ++--
>  drivers/pci/controller/cadence/pci-j721e.c | 33 +++++++++++++++++++++-
>  2 files changed, 35 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/pci/controller/cadence/Kconfig b/drivers/pci/controller/cadence/Kconfig
> index 82b58096eea0..72d7d264d6c3 100644
> --- a/drivers/pci/controller/cadence/Kconfig
> +++ b/drivers/pci/controller/cadence/Kconfig
> @@ -43,10 +43,10 @@ config PCIE_CADENCE_PLAT_EP
>  	  different vendors SoCs.
>  
>  config PCI_J721E
> -	bool
> +	tristate
>  
>  config PCI_J721E_HOST
> -	bool "TI J721E PCIe controller (host mode)"
> +	tristate "TI J721E PCIe controller (host mode)"
>  	depends on ARCH_K3 || COMPILE_TEST
>  	depends on OF
>  	select PCIE_CADENCE_HOST
> @@ -57,7 +57,7 @@ config PCI_J721E_HOST
>  	  core.
>  
>  config PCI_J721E_EP
> -	bool "TI J721E PCIe controller (endpoint mode)"
> +	tristate "TI J721E PCIe controller (endpoint mode)"
>  	depends on ARCH_K3 || COMPILE_TEST
>  	depends on OF
>  	depends on PCI_ENDPOINT
> diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c
> index ef1cfdae33bb..8bffcd31729c 100644
> --- a/drivers/pci/controller/cadence/pci-j721e.c
> +++ b/drivers/pci/controller/cadence/pci-j721e.c
> @@ -15,6 +15,7 @@
>  #include <linux/irqchip/chained_irq.h>
>  #include <linux/irqdomain.h>
>  #include <linux/mfd/syscon.h>
> +#include <linux/module.h>
>  #include <linux/of.h>
>  #include <linux/pci.h>
>  #include <linux/platform_device.h>
> @@ -27,6 +28,7 @@
>  #define cdns_pcie_to_rc(p) container_of(p, struct cdns_pcie_rc, pcie)
>  
>  #define ENABLE_REG_SYS_2	0x108
> +#define ENABLE_CLR_REG_SYS_2	0x308
>  #define STATUS_REG_SYS_2	0x508
>  #define STATUS_CLR_REG_SYS_2	0x708
>  #define LINK_DOWN		BIT(1)
> @@ -116,6 +118,15 @@ static irqreturn_t j721e_pcie_link_irq_handler(int irq, void *priv)
>  	return IRQ_HANDLED;
>  }
>  
> +static void j721e_pcie_disable_link_irq(struct j721e_pcie *pcie)
> +{
> +	u32 reg;
> +
> +	reg = j721e_pcie_intd_readl(pcie, ENABLE_CLR_REG_SYS_2);
> +	reg |= pcie->linkdown_irq_regfield;
> +	j721e_pcie_intd_writel(pcie, ENABLE_CLR_REG_SYS_2, reg);
> +}
> +
>  static void j721e_pcie_config_link_irq(struct j721e_pcie *pcie)
>  {
>  	u32 reg;
> @@ -633,9 +644,25 @@ static void j721e_pcie_remove(struct platform_device *pdev)
>  	struct j721e_pcie *pcie = platform_get_drvdata(pdev);
>  	struct cdns_pcie *cdns_pcie = pcie->cdns_pcie;
>  	struct device *dev = &pdev->dev;
> +	struct cdns_pcie_ep *ep;
> +	struct cdns_pcie_rc *rc;
> +
> +	if (pcie->mode == PCI_MODE_RC) {
> +		rc = container_of(cdns_pcie, struct cdns_pcie_rc, pcie);
> +		cdns_pcie_host_disable(rc);
> +	} else {
> +		ep = container_of(cdns_pcie, struct cdns_pcie_ep, pcie);
> +		cdns_pcie_ep_disable(ep);
> +	}
> +
> +	if (pcie->reset_gpio) {
> +		msleep(PCIE_T_PVPERL_MS);

There is no point in adding a delay before PERST# assertion.

> +		gpiod_set_value_cansleep(pcie->reset_gpio, 1);

This is not PERST# assert, isn't it? Typo?

- Mani

-- 
மணிவண்ணன் சதாசிவம்
Re: [PATCH v2 4/4] PCI: j721e: Add support to build as a loadable module
Posted by Siddharth Vadapalli 8 months, 2 weeks ago 
On Wed, Apr 09, 2025 at 12:06:35PM +0530, Manivannan Sadhasivam wrote:

Hello Mani,

> On Sun, Mar 30, 2025 at 02:09:14PM +0530, Siddharth Vadapalli wrote:
> > The 'pci-j721e.c' driver is the application/glue/wrapper driver for the
> > Cadence PCIe Controllers on TI SoCs. Implement support for building it as a
> > loadable module.
> > 
> > Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
> > ---
> > 
> > v1:
> > https://lore.kernel.org/r/20250307103128.3287497-5-s-vadapalli@ti.com/
> > Changes since v1:
> > - Based on feedback from Thomas at:
> >   https://lore.kernel.org/r/88b3ecbe-32b6-4310-afb9-da19a2d0506a@bootlin.com/
> >   the "check" for a non-NULL "pcie-refclk" in j721e_pcie_remove() has been
> >   dropped.
> > 
> > Regards,
> > Siddharth.
> > 
> >  drivers/pci/controller/cadence/Kconfig     |  6 ++--
> >  drivers/pci/controller/cadence/pci-j721e.c | 33 +++++++++++++++++++++-
> >  2 files changed, 35 insertions(+), 4 deletions(-)
> > 
> > diff --git a/drivers/pci/controller/cadence/Kconfig b/drivers/pci/controller/cadence/Kconfig
> > index 82b58096eea0..72d7d264d6c3 100644
> > --- a/drivers/pci/controller/cadence/Kconfig
> > +++ b/drivers/pci/controller/cadence/Kconfig
> > @@ -43,10 +43,10 @@ config PCIE_CADENCE_PLAT_EP
> >  	  different vendors SoCs.
> >  
> >  config PCI_J721E
> > -	bool
> > +	tristate
> >  
> >  config PCI_J721E_HOST
> > -	bool "TI J721E PCIe controller (host mode)"
> > +	tristate "TI J721E PCIe controller (host mode)"
> >  	depends on ARCH_K3 || COMPILE_TEST
> >  	depends on OF
> >  	select PCIE_CADENCE_HOST
> > @@ -57,7 +57,7 @@ config PCI_J721E_HOST
> >  	  core.
> >  
> >  config PCI_J721E_EP
> > -	bool "TI J721E PCIe controller (endpoint mode)"
> > +	tristate "TI J721E PCIe controller (endpoint mode)"
> >  	depends on ARCH_K3 || COMPILE_TEST
> >  	depends on OF
> >  	depends on PCI_ENDPOINT
> > diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c
> > index ef1cfdae33bb..8bffcd31729c 100644
> > --- a/drivers/pci/controller/cadence/pci-j721e.c
> > +++ b/drivers/pci/controller/cadence/pci-j721e.c
> > @@ -15,6 +15,7 @@
> >  #include <linux/irqchip/chained_irq.h>
> >  #include <linux/irqdomain.h>
> >  #include <linux/mfd/syscon.h>
> > +#include <linux/module.h>
> >  #include <linux/of.h>
> >  #include <linux/pci.h>
> >  #include <linux/platform_device.h>
> > @@ -27,6 +28,7 @@
> >  #define cdns_pcie_to_rc(p) container_of(p, struct cdns_pcie_rc, pcie)
> >  
> >  #define ENABLE_REG_SYS_2	0x108
> > +#define ENABLE_CLR_REG_SYS_2	0x308
> >  #define STATUS_REG_SYS_2	0x508
> >  #define STATUS_CLR_REG_SYS_2	0x708
> >  #define LINK_DOWN		BIT(1)
> > @@ -116,6 +118,15 @@ static irqreturn_t j721e_pcie_link_irq_handler(int irq, void *priv)
> >  	return IRQ_HANDLED;
> >  }
> >  
> > +static void j721e_pcie_disable_link_irq(struct j721e_pcie *pcie)
> > +{
> > +	u32 reg;
> > +
> > +	reg = j721e_pcie_intd_readl(pcie, ENABLE_CLR_REG_SYS_2);
> > +	reg |= pcie->linkdown_irq_regfield;
> > +	j721e_pcie_intd_writel(pcie, ENABLE_CLR_REG_SYS_2, reg);
> > +}
> > +
> >  static void j721e_pcie_config_link_irq(struct j721e_pcie *pcie)
> >  {
> >  	u32 reg;
> > @@ -633,9 +644,25 @@ static void j721e_pcie_remove(struct platform_device *pdev)
> >  	struct j721e_pcie *pcie = platform_get_drvdata(pdev);
> >  	struct cdns_pcie *cdns_pcie = pcie->cdns_pcie;
> >  	struct device *dev = &pdev->dev;
> > +	struct cdns_pcie_ep *ep;
> > +	struct cdns_pcie_rc *rc;
> > +
> > +	if (pcie->mode == PCI_MODE_RC) {
> > +		rc = container_of(cdns_pcie, struct cdns_pcie_rc, pcie);
> > +		cdns_pcie_host_disable(rc);
> > +	} else {
> > +		ep = container_of(cdns_pcie, struct cdns_pcie_ep, pcie);
> > +		cdns_pcie_ep_disable(ep);
> > +	}
> > +
> > +	if (pcie->reset_gpio) {
> > +		msleep(PCIE_T_PVPERL_MS);
> 
> There is no point in adding a delay before PERST# assertion.

True :)

> 
> > +		gpiod_set_value_cansleep(pcie->reset_gpio, 1);
> 
> This is not PERST# assert, isn't it? Typo?

It is PERST# assert. As you rightly pointed out above, a delay isn't
required when asserting it. It can be dropped. I will fix this in the v3
series. Thank you for reviewing this patch.

Regards,
Siddharth.
Re: [PATCH v2 4/4] PCI: j721e: Add support to build as a loadable module
Posted by Manivannan Sadhasivam 8 months, 1 week ago 
On Wed, Apr 09, 2025 at 12:12:27PM +0530, Siddharth Vadapalli wrote:
> On Wed, Apr 09, 2025 at 12:06:35PM +0530, Manivannan Sadhasivam wrote:
> 
> Hello Mani,
> 
> > On Sun, Mar 30, 2025 at 02:09:14PM +0530, Siddharth Vadapalli wrote:
> > > The 'pci-j721e.c' driver is the application/glue/wrapper driver for the
> > > Cadence PCIe Controllers on TI SoCs. Implement support for building it as a
> > > loadable module.
> > > 
> > > Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
> > > ---
> > > 
> > > v1:
> > > https://lore.kernel.org/r/20250307103128.3287497-5-s-vadapalli@ti.com/
> > > Changes since v1:
> > > - Based on feedback from Thomas at:
> > >   https://lore.kernel.org/r/88b3ecbe-32b6-4310-afb9-da19a2d0506a@bootlin.com/
> > >   the "check" for a non-NULL "pcie-refclk" in j721e_pcie_remove() has been
> > >   dropped.
> > > 
> > > Regards,
> > > Siddharth.
> > > 
> > >  drivers/pci/controller/cadence/Kconfig     |  6 ++--
> > >  drivers/pci/controller/cadence/pci-j721e.c | 33 +++++++++++++++++++++-
> > >  2 files changed, 35 insertions(+), 4 deletions(-)
> > > 
> > > diff --git a/drivers/pci/controller/cadence/Kconfig b/drivers/pci/controller/cadence/Kconfig
> > > index 82b58096eea0..72d7d264d6c3 100644
> > > --- a/drivers/pci/controller/cadence/Kconfig
> > > +++ b/drivers/pci/controller/cadence/Kconfig
> > > @@ -43,10 +43,10 @@ config PCIE_CADENCE_PLAT_EP
> > >  	  different vendors SoCs.
> > >  
> > >  config PCI_J721E
> > > -	bool
> > > +	tristate
> > >  
> > >  config PCI_J721E_HOST
> > > -	bool "TI J721E PCIe controller (host mode)"
> > > +	tristate "TI J721E PCIe controller (host mode)"
> > >  	depends on ARCH_K3 || COMPILE_TEST
> > >  	depends on OF
> > >  	select PCIE_CADENCE_HOST
> > > @@ -57,7 +57,7 @@ config PCI_J721E_HOST
> > >  	  core.
> > >  
> > >  config PCI_J721E_EP
> > > -	bool "TI J721E PCIe controller (endpoint mode)"
> > > +	tristate "TI J721E PCIe controller (endpoint mode)"
> > >  	depends on ARCH_K3 || COMPILE_TEST
> > >  	depends on OF
> > >  	depends on PCI_ENDPOINT
> > > diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c
> > > index ef1cfdae33bb..8bffcd31729c 100644
> > > --- a/drivers/pci/controller/cadence/pci-j721e.c
> > > +++ b/drivers/pci/controller/cadence/pci-j721e.c
> > > @@ -15,6 +15,7 @@
> > >  #include <linux/irqchip/chained_irq.h>
> > >  #include <linux/irqdomain.h>
> > >  #include <linux/mfd/syscon.h>
> > > +#include <linux/module.h>
> > >  #include <linux/of.h>
> > >  #include <linux/pci.h>
> > >  #include <linux/platform_device.h>
> > > @@ -27,6 +28,7 @@
> > >  #define cdns_pcie_to_rc(p) container_of(p, struct cdns_pcie_rc, pcie)
> > >  
> > >  #define ENABLE_REG_SYS_2	0x108
> > > +#define ENABLE_CLR_REG_SYS_2	0x308
> > >  #define STATUS_REG_SYS_2	0x508
> > >  #define STATUS_CLR_REG_SYS_2	0x708
> > >  #define LINK_DOWN		BIT(1)
> > > @@ -116,6 +118,15 @@ static irqreturn_t j721e_pcie_link_irq_handler(int irq, void *priv)
> > >  	return IRQ_HANDLED;
> > >  }
> > >  
> > > +static void j721e_pcie_disable_link_irq(struct j721e_pcie *pcie)
> > > +{
> > > +	u32 reg;
> > > +
> > > +	reg = j721e_pcie_intd_readl(pcie, ENABLE_CLR_REG_SYS_2);
> > > +	reg |= pcie->linkdown_irq_regfield;
> > > +	j721e_pcie_intd_writel(pcie, ENABLE_CLR_REG_SYS_2, reg);
> > > +}
> > > +
> > >  static void j721e_pcie_config_link_irq(struct j721e_pcie *pcie)
> > >  {
> > >  	u32 reg;
> > > @@ -633,9 +644,25 @@ static void j721e_pcie_remove(struct platform_device *pdev)
> > >  	struct j721e_pcie *pcie = platform_get_drvdata(pdev);
> > >  	struct cdns_pcie *cdns_pcie = pcie->cdns_pcie;
> > >  	struct device *dev = &pdev->dev;
> > > +	struct cdns_pcie_ep *ep;
> > > +	struct cdns_pcie_rc *rc;
> > > +
> > > +	if (pcie->mode == PCI_MODE_RC) {
> > > +		rc = container_of(cdns_pcie, struct cdns_pcie_rc, pcie);
> > > +		cdns_pcie_host_disable(rc);
> > > +	} else {
> > > +		ep = container_of(cdns_pcie, struct cdns_pcie_ep, pcie);
> > > +		cdns_pcie_ep_disable(ep);
> > > +	}
> > > +
> > > +	if (pcie->reset_gpio) {
> > > +		msleep(PCIE_T_PVPERL_MS);
> > 
> > There is no point in adding a delay before PERST# assertion.
> 
> True :)
> 
> > 
> > > +		gpiod_set_value_cansleep(pcie->reset_gpio, 1);
> > 
> > This is not PERST# assert, isn't it? Typo?
> 
> It is PERST# assert.

Since the reset-gpios polarity is defined as GPIO_ACTIVE_HIGH in DT (which is
wrong unless you have an external component that changes polarity), for PERST#
assert, you need to set 0. If you set 1, then PERST# will be signalled as
deassert.

- Mani

-- 
மணிவண்ணன் சதாசிவம்
Re: [PATCH v2 4/4] PCI: j721e: Add support to build as a loadable module
Posted by Siddharth Vadapalli 8 months, 1 week ago 
On Sun, Apr 13, 2025 at 07:43:05PM +0530, Manivannan Sadhasivam wrote:
> On Wed, Apr 09, 2025 at 12:12:27PM +0530, Siddharth Vadapalli wrote:
> > On Wed, Apr 09, 2025 at 12:06:35PM +0530, Manivannan Sadhasivam wrote:
> > 
> > Hello Mani,
> > 
> > > On Sun, Mar 30, 2025 at 02:09:14PM +0530, Siddharth Vadapalli wrote:
> > > > The 'pci-j721e.c' driver is the application/glue/wrapper driver for the
> > > > Cadence PCIe Controllers on TI SoCs. Implement support for building it as a
> > > > loadable module.
> > > > 
> > > > Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
> > > > ---
> > > > 
> > > > v1:
> > > > https://lore.kernel.org/r/20250307103128.3287497-5-s-vadapalli@ti.com/
> > > > Changes since v1:
> > > > - Based on feedback from Thomas at:
> > > >   https://lore.kernel.org/r/88b3ecbe-32b6-4310-afb9-da19a2d0506a@bootlin.com/
> > > >   the "check" for a non-NULL "pcie-refclk" in j721e_pcie_remove() has been
> > > >   dropped.
> > > > 
> > > > Regards,
> > > > Siddharth.
> > > > 
> > > >  drivers/pci/controller/cadence/Kconfig     |  6 ++--
> > > >  drivers/pci/controller/cadence/pci-j721e.c | 33 +++++++++++++++++++++-
> > > >  2 files changed, 35 insertions(+), 4 deletions(-)
> > > > 
> > > > diff --git a/drivers/pci/controller/cadence/Kconfig b/drivers/pci/controller/cadence/Kconfig
> > > > index 82b58096eea0..72d7d264d6c3 100644
> > > > --- a/drivers/pci/controller/cadence/Kconfig
> > > > +++ b/drivers/pci/controller/cadence/Kconfig
> > > > @@ -43,10 +43,10 @@ config PCIE_CADENCE_PLAT_EP
> > > >  	  different vendors SoCs.
> > > >  
> > > >  config PCI_J721E
> > > > -	bool
> > > > +	tristate
> > > >  
> > > >  config PCI_J721E_HOST
> > > > -	bool "TI J721E PCIe controller (host mode)"
> > > > +	tristate "TI J721E PCIe controller (host mode)"
> > > >  	depends on ARCH_K3 || COMPILE_TEST
> > > >  	depends on OF
> > > >  	select PCIE_CADENCE_HOST
> > > > @@ -57,7 +57,7 @@ config PCI_J721E_HOST
> > > >  	  core.
> > > >  
> > > >  config PCI_J721E_EP
> > > > -	bool "TI J721E PCIe controller (endpoint mode)"
> > > > +	tristate "TI J721E PCIe controller (endpoint mode)"
> > > >  	depends on ARCH_K3 || COMPILE_TEST
> > > >  	depends on OF
> > > >  	depends on PCI_ENDPOINT
> > > > diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c
> > > > index ef1cfdae33bb..8bffcd31729c 100644
> > > > --- a/drivers/pci/controller/cadence/pci-j721e.c
> > > > +++ b/drivers/pci/controller/cadence/pci-j721e.c
> > > > @@ -15,6 +15,7 @@
> > > >  #include <linux/irqchip/chained_irq.h>
> > > >  #include <linux/irqdomain.h>
> > > >  #include <linux/mfd/syscon.h>
> > > > +#include <linux/module.h>
> > > >  #include <linux/of.h>
> > > >  #include <linux/pci.h>
> > > >  #include <linux/platform_device.h>
> > > > @@ -27,6 +28,7 @@
> > > >  #define cdns_pcie_to_rc(p) container_of(p, struct cdns_pcie_rc, pcie)
> > > >  
> > > >  #define ENABLE_REG_SYS_2	0x108
> > > > +#define ENABLE_CLR_REG_SYS_2	0x308
> > > >  #define STATUS_REG_SYS_2	0x508
> > > >  #define STATUS_CLR_REG_SYS_2	0x708
> > > >  #define LINK_DOWN		BIT(1)
> > > > @@ -116,6 +118,15 @@ static irqreturn_t j721e_pcie_link_irq_handler(int irq, void *priv)
> > > >  	return IRQ_HANDLED;
> > > >  }
> > > >  
> > > > +static void j721e_pcie_disable_link_irq(struct j721e_pcie *pcie)
> > > > +{
> > > > +	u32 reg;
> > > > +
> > > > +	reg = j721e_pcie_intd_readl(pcie, ENABLE_CLR_REG_SYS_2);
> > > > +	reg |= pcie->linkdown_irq_regfield;
> > > > +	j721e_pcie_intd_writel(pcie, ENABLE_CLR_REG_SYS_2, reg);
> > > > +}
> > > > +
> > > >  static void j721e_pcie_config_link_irq(struct j721e_pcie *pcie)
> > > >  {
> > > >  	u32 reg;
> > > > @@ -633,9 +644,25 @@ static void j721e_pcie_remove(struct platform_device *pdev)
> > > >  	struct j721e_pcie *pcie = platform_get_drvdata(pdev);
> > > >  	struct cdns_pcie *cdns_pcie = pcie->cdns_pcie;
> > > >  	struct device *dev = &pdev->dev;
> > > > +	struct cdns_pcie_ep *ep;
> > > > +	struct cdns_pcie_rc *rc;
> > > > +
> > > > +	if (pcie->mode == PCI_MODE_RC) {
> > > > +		rc = container_of(cdns_pcie, struct cdns_pcie_rc, pcie);
> > > > +		cdns_pcie_host_disable(rc);
> > > > +	} else {
> > > > +		ep = container_of(cdns_pcie, struct cdns_pcie_ep, pcie);
> > > > +		cdns_pcie_ep_disable(ep);
> > > > +	}
> > > > +
> > > > +	if (pcie->reset_gpio) {
> > > > +		msleep(PCIE_T_PVPERL_MS);
> > > 
> > > There is no point in adding a delay before PERST# assertion.
> > 
> > True :)
> > 
> > > 
> > > > +		gpiod_set_value_cansleep(pcie->reset_gpio, 1);
> > > 
> > > This is not PERST# assert, isn't it? Typo?
> > 
> > It is PERST# assert.
> 
> Since the reset-gpios polarity is defined as GPIO_ACTIVE_HIGH in DT (which is
> wrong unless you have an external component that changes polarity), for PERST#
> assert, you need to set 0. If you set 1, then PERST# will be signalled as
> deassert.

I realize now that I have accidentally set it to 1 when it should have
been 0. It was meant to be PERST# assert since it is the .remove callback.
The v3 patch at:
https://patchwork.kernel.org/project/linux-pci/patch/20250410104426.463453-5-s-vadapalli@ti.com/
dropped the delay which is not required for PERST# assert, but the
polarity is still incorrect. I will fix it in the v4 series.

Thank you for noticing this and pointing it out.

Regards,
Siddharth.

Patchew 2.1-devel-b67e4c2

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