[PATCH v5 09/17] media: rzg2l-cru: csi2: Skip system clock for RZ/V2H(P) SoC

Tommaso Merciai posted 17 patches 8 months, 3 weeks ago
There is a newer version of this series
[PATCH v5 09/17] media: rzg2l-cru: csi2: Skip system clock for RZ/V2H(P) SoC
Posted by Tommaso Merciai 8 months, 3 weeks ago
The RZ/V2H(P) SoC does not require a `system` clock for the CSI-2
interface. To accommodate this, introduce a `has_system_clk` bool flag
in the `rzg2l_csi2_info` structure and update the rzg2l_csi2_probe() to
conditionally request the clock only when needed.

This patch is in preparation for adding support for RZ/V2H(P) SoC.

Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
---
Changes since v2:
 - Added has_system_clk bool flag to the rzg2l_csi2_info structure to handle
   case where system clock is not required as suggested by LPinchart.
 - Fixed commit body and msg

 .../media/platform/renesas/rzg2l-cru/rzg2l-csi2.c    | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-csi2.c b/drivers/media/platform/renesas/rzg2l-cru/rzg2l-csi2.c
index 4aa5d58dde5bd..e4781105eadc0 100644
--- a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-csi2.c
+++ b/drivers/media/platform/renesas/rzg2l-cru/rzg2l-csi2.c
@@ -127,6 +127,7 @@ struct rzg2l_csi2 {
 struct rzg2l_csi2_info {
 	int (*dphy_enable)(struct rzg2l_csi2 *csi2);
 	int (*dphy_disable)(struct rzg2l_csi2 *csi2);
+	bool has_system_clk;
 };
 
 struct rzg2l_csi2_timings {
@@ -364,6 +365,7 @@ static int rzg2l_csi2_dphy_enable(struct rzg2l_csi2 *csi2)
 static const struct rzg2l_csi2_info rzg2l_csi2_info = {
 	.dphy_enable = rzg2l_csi2_dphy_enable,
 	.dphy_disable = rzg2l_csi2_dphy_disable,
+	.has_system_clk = true,
 };
 
 static int rzg2l_csi2_dphy_setting(struct v4l2_subdev *sd, bool on)
@@ -801,10 +803,12 @@ static int rzg2l_csi2_probe(struct platform_device *pdev)
 		return dev_err_probe(dev, PTR_ERR(csi2->presetn),
 				     "Failed to get cpg presetn\n");
 
-	csi2->sysclk = devm_clk_get(dev, "system");
-	if (IS_ERR(csi2->sysclk))
-		return dev_err_probe(dev, PTR_ERR(csi2->sysclk),
-				     "Failed to get system clk\n");
+	if (csi2->info->has_system_clk) {
+		csi2->sysclk = devm_clk_get(dev, "system");
+		if (IS_ERR(csi2->sysclk))
+			return dev_err_probe(dev, PTR_ERR(csi2->sysclk),
+					     "Failed to get system clk\n");
+	}
 
 	csi2->vclk = devm_clk_get(dev, "video");
 	if (IS_ERR(csi2->vclk))
-- 
2.43.0
Re: [PATCH v5 09/17] media: rzg2l-cru: csi2: Skip system clock for RZ/V2H(P) SoC
Posted by Laurent Pinchart 8 months, 2 weeks ago
Hi Tommaso,

Thank you for the patch.

On Fri, Mar 28, 2025 at 06:29:45PM +0100, Tommaso Merciai wrote:
> The RZ/V2H(P) SoC does not require a `system` clock for the CSI-2
> interface. To accommodate this, introduce a `has_system_clk` bool flag
> in the `rzg2l_csi2_info` structure and update the rzg2l_csi2_probe() to
> conditionally request the clock only when needed.
> 
> This patch is in preparation for adding support for RZ/V2H(P) SoC.
> 
> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>

Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

> ---
> Changes since v2:
>  - Added has_system_clk bool flag to the rzg2l_csi2_info structure to handle
>    case where system clock is not required as suggested by LPinchart.
>  - Fixed commit body and msg
> 
>  .../media/platform/renesas/rzg2l-cru/rzg2l-csi2.c    | 12 ++++++++----
>  1 file changed, 8 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-csi2.c b/drivers/media/platform/renesas/rzg2l-cru/rzg2l-csi2.c
> index 4aa5d58dde5bd..e4781105eadc0 100644
> --- a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-csi2.c
> +++ b/drivers/media/platform/renesas/rzg2l-cru/rzg2l-csi2.c
> @@ -127,6 +127,7 @@ struct rzg2l_csi2 {
>  struct rzg2l_csi2_info {
>  	int (*dphy_enable)(struct rzg2l_csi2 *csi2);
>  	int (*dphy_disable)(struct rzg2l_csi2 *csi2);
> +	bool has_system_clk;
>  };
>  
>  struct rzg2l_csi2_timings {
> @@ -364,6 +365,7 @@ static int rzg2l_csi2_dphy_enable(struct rzg2l_csi2 *csi2)
>  static const struct rzg2l_csi2_info rzg2l_csi2_info = {
>  	.dphy_enable = rzg2l_csi2_dphy_enable,
>  	.dphy_disable = rzg2l_csi2_dphy_disable,
> +	.has_system_clk = true,
>  };
>  
>  static int rzg2l_csi2_dphy_setting(struct v4l2_subdev *sd, bool on)
> @@ -801,10 +803,12 @@ static int rzg2l_csi2_probe(struct platform_device *pdev)
>  		return dev_err_probe(dev, PTR_ERR(csi2->presetn),
>  				     "Failed to get cpg presetn\n");
>  
> -	csi2->sysclk = devm_clk_get(dev, "system");
> -	if (IS_ERR(csi2->sysclk))
> -		return dev_err_probe(dev, PTR_ERR(csi2->sysclk),
> -				     "Failed to get system clk\n");
> +	if (csi2->info->has_system_clk) {
> +		csi2->sysclk = devm_clk_get(dev, "system");
> +		if (IS_ERR(csi2->sysclk))
> +			return dev_err_probe(dev, PTR_ERR(csi2->sysclk),
> +					     "Failed to get system clk\n");
> +	}
>  
>  	csi2->vclk = devm_clk_get(dev, "video");
>  	if (IS_ERR(csi2->vclk))

-- 
Regards,

Laurent Pinchart