[PATCH v9 0/5] PCI: dwc: Add support for configuring lane equalization presets

Krishna Chaitanya Chundru posted 5 patches 8 months, 2 weeks ago
arch/arm64/boot/dts/qcom/x1e80100.dtsi            | 11 ++++
drivers/pci/controller/dwc/pcie-designware-host.c | 79 +++++++++++++++++++++++
drivers/pci/controller/dwc/pcie-designware.c      |  8 +++
drivers/pci/controller/dwc/pcie-designware.h      |  4 ++
drivers/pci/of.c                                  | 44 +++++++++++++
drivers/pci/pci.h                                 | 32 ++++++++-
include/uapi/linux/pci_regs.h                     | 12 +++-
7 files changed, 188 insertions(+), 2 deletions(-)
[PATCH v9 0/5] PCI: dwc: Add support for configuring lane equalization presets
Posted by Krishna Chaitanya Chundru 8 months, 2 weeks ago
PCIe equalization presets are predefined settings used to optimize
signal integrity by compensating for signal loss and distortion in
high-speed data transmission.

As per PCIe spec 6.0.1 revision section 8.3.3.3 & 4.2.4 for data rates
of 8.0 GT/s, 16.0 GT/s, 32.0 GT/s, and 64.0 GT/s, there is a way to
configure lane equalization presets for each lane to enhance the PCIe
link reliability. Each preset value represents a different combination
of pre-shoot and de-emphasis values. For each data rate, different
registers are defined: for 8.0 GT/s, registers are defined in section
7.7.3.4; for 16.0 GT/s, in section 7.7.5.9, etc. The 8.0 GT/s rate has
an extra receiver preset hint, requiring 16 bits per lane, while the
remaining data rates use 8 bits per lane.

Based on the number of lanes and the supported data rate, read the
device tree property and stores in the presets structure.

Based upon the lane width and supported data rate update lane
equalization registers.

This patch depends on the this dt binding pull request which got recently
merged: https://github.com/devicetree-org/dt-schema/pull/146

Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
---
Changes in v9:
- Add support for data rates 32 GT/s & 64 GT/s in dwc driver & macros
  for those registers (mani).
- update the print statements (mani).
- Link to v8: https://lore.kernel.org/r/20250316-preset_v6-v8-0-0703a78cb355@oss.qualcomm.com

Changes in v8:
- Couple of nits by (bjorn & mani)
- Add EQ_PRESET_8GTS by (mani).
- Remove the logic not to update the DWC registers if the num_lanes is
  not equal to maximum lanes (mani)
- Link to v7: https://lore.kernel.org/r/20250225-preset_v6-v7-0-a593f3ef3951@oss.qualcomm.com

Changes in v7:
- Update the 16bit array in the array (mani & konrad)
- Update the couple of nits (comments, error log format etc) (mani)
- remove !num_lanes check as this is not needed with this series (mani)
- Add warning prints if the data rate is not supported and if there is
  no devicetree property for the data rate (mani).
- Link to v6: https://lore.kernel.org/r/20250210-preset_v6-v6-0-cbd837d0028d@oss.qualcomm.com

Changes in v6:
- update the dt properties to match the lane width ( mani & konard)
- move everything to helper function and let the helper function
  determine reg size and offset (mani)
- update the function header (mani)
- move the num_lanes check to the main function (mani)
- Link to v5: https://lore.kernel.org/linux-kernel/20250128-preset_v2-v5-0-4d230d956f8c@oss.qualcomm.com/

Changes in v5:
- Instead of using of_property_present use return value of
  of_property_read_u8_array to know about property is present or not and
  add a macro for reserved value(Konrad).
- Link to v4: https://lore.kernel.org/r/20250124-preset_v2-v4-0-0b512cad08e1@oss.qualcomm.com

Changes in v4:
- use static arrays for storing preset values and use default value 0xff
  to indicate the property is not present (Dimitry & konrad).
- Link to v3: https://lore.kernel.org/r/20241223-preset_v2-v3-0-a339f475caf5@oss.qualcomm.com

Changes in v3:
- In previous series a wrong patch was attached, correct it
- Link to v2: https://lore.kernel.org/r/20241212-preset_v2-v2-0-210430fbcd8a@oss.qualcomm.com

Changes in v2:
- Fix the kernel test robot error
- As suggested by konrad use for loop and read "eq-presets-%ugts", (8 << i)
- Link to v1: https://lore.kernel.org/r/20241116-presets-v1-0-878a837a4fee@quicinc.com

---
Krishna Chaitanya Chundru (5):
      arm64: dts: qcom: x1e80100: Add PCIe lane equalization preset properties
      PCI: of: Add of_pci_get_equalization_presets() API
      PCI: dwc: Update pci->num_lanes to maximum supported link width
      PCI: Add lane equalization register offsets
      PCI: dwc: Add support for configuring lane equalization presets

 arch/arm64/boot/dts/qcom/x1e80100.dtsi            | 11 ++++
 drivers/pci/controller/dwc/pcie-designware-host.c | 79 +++++++++++++++++++++++
 drivers/pci/controller/dwc/pcie-designware.c      |  8 +++
 drivers/pci/controller/dwc/pcie-designware.h      |  4 ++
 drivers/pci/of.c                                  | 44 +++++++++++++
 drivers/pci/pci.h                                 | 32 ++++++++-
 include/uapi/linux/pci_regs.h                     | 12 +++-
 7 files changed, 188 insertions(+), 2 deletions(-)
---
base-commit: 3175967ecb3266d0ad7d2ca7ccceaf15fa2f15e2
change-id: 20250210-preset_v6-1e7f560d13ad

Best regards,
-- 
Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Re: [PATCH v9 0/5] PCI: dwc: Add support for configuring lane equalization presets
Posted by Manivannan Sadhasivam 7 months, 4 weeks ago
On Fri, 28 Mar 2025 15:58:28 +0530, Krishna Chaitanya Chundru wrote:
> PCIe equalization presets are predefined settings used to optimize
> signal integrity by compensating for signal loss and distortion in
> high-speed data transmission.
> 
> As per PCIe spec 6.0.1 revision section 8.3.3.3 & 4.2.4 for data rates
> of 8.0 GT/s, 16.0 GT/s, 32.0 GT/s, and 64.0 GT/s, there is a way to
> configure lane equalization presets for each lane to enhance the PCIe
> link reliability. Each preset value represents a different combination
> of pre-shoot and de-emphasis values. For each data rate, different
> registers are defined: for 8.0 GT/s, registers are defined in section
> 7.7.3.4; for 16.0 GT/s, in section 7.7.5.9, etc. The 8.0 GT/s rate has
> an extra receiver preset hint, requiring 16 bits per lane, while the
> remaining data rates use 8 bits per lane.
> 
> [...]

Applied to controller/qcom, thanks!

[2/5] PCI: of: Add of_pci_get_equalization_presets() API
      commit: 2f12e20457a27599b6e1e1b0f08e6175e37c7e05
[3/5] PCI: dwc: Update pci->num_lanes to maximum supported link width
      commit: f1eb5da4d28b3788049ef98428b395fbab3478fd
[4/5] PCI: Add lane equalization register offsets
      commit: 165d80061e771390da26a29d362ceff96ab75da8
[5/5] PCI: dwc: Add support for configuring lane equalization presets
      commit: 3b35b43825f4e906d46519908dfff76a58d58bbb

Best regards,
-- 
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Re: (subset) [PATCH v9 0/5] PCI: dwc: Add support for configuring lane equalization presets
Posted by Bjorn Andersson 6 months, 4 weeks ago
On Fri, 28 Mar 2025 15:58:28 +0530, Krishna Chaitanya Chundru wrote:
> PCIe equalization presets are predefined settings used to optimize
> signal integrity by compensating for signal loss and distortion in
> high-speed data transmission.
> 
> As per PCIe spec 6.0.1 revision section 8.3.3.3 & 4.2.4 for data rates
> of 8.0 GT/s, 16.0 GT/s, 32.0 GT/s, and 64.0 GT/s, there is a way to
> configure lane equalization presets for each lane to enhance the PCIe
> link reliability. Each preset value represents a different combination
> of pre-shoot and de-emphasis values. For each data rate, different
> registers are defined: for 8.0 GT/s, registers are defined in section
> 7.7.3.4; for 16.0 GT/s, in section 7.7.5.9, etc. The 8.0 GT/s rate has
> an extra receiver preset hint, requiring 16 bits per lane, while the
> remaining data rates use 8 bits per lane.
> 
> [...]

Applied, thanks!

[1/5] arm64: dts: qcom: x1e80100: Add PCIe lane equalization preset properties
      commit: 435c3642a6a82c774f2897d72e6ed794a1dbaba1

Best regards,
-- 
Bjorn Andersson <andersson@kernel.org>