Move phy, perst, to root port from the controller node.
Rename perst-gpios to reset-gpios to align with the expected naming
convention of pci-bus-common.yaml.
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 5 ++++-
arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi | 5 ++++-
arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 5 ++++-
arch/arm64/boot/dts/qcom/sc7280.dtsi | 7 +++----
4 files changed, 15 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
index 7a36c90ad4ec..f54db6345b7a 100644
--- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
+++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
@@ -709,8 +709,11 @@ &mdss_edp_phy {
status = "okay";
};
+&pcieport1 {
+ reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
+};
+
&pcie1 {
- perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie1_reset_n>, <&pcie1_wake_n>;
pinctrl-names = "default";
diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi
index 2ba4ea60cb14..60b3cf50ea1d 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi
@@ -472,10 +472,13 @@ &pcie1 {
pinctrl-names = "default";
pinctrl-0 = <&pcie1_clkreq_n>, <&ssd_rst_l>, <&pe_wake_odl>;
- perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
vddpe-3v3-supply = <&pp3300_ssd>;
};
+&pcieport1 {
+ reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
+};
+
&pm8350c_pwm {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
index 7370aa0dbf0e..19910670fc3a 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
@@ -414,9 +414,12 @@ &lpass_va_macro {
vdd-micb-supply = <&vreg_bob>;
};
+&pcieport1 {
+ reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
+};
+
&pcie1 {
status = "okay";
- perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
vddpe-3v3-supply = <&nvme_3v3_regulator>;
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 0f2caf36910b..6c21c320a2b5 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -2271,9 +2271,6 @@ pcie1: pcie@1c08000 {
power-domains = <&gcc GCC_PCIE_1_GDSC>;
- phys = <&pcie1_phy>;
- phy-names = "pciephy";
-
pinctrl-names = "default";
pinctrl-0 = <&pcie1_clkreq_n>;
@@ -2284,7 +2281,7 @@ pcie1: pcie@1c08000 {
status = "disabled";
- pcie@0 {
+ pcieport1: pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
@@ -2292,6 +2289,8 @@ pcie@0 {
#address-cells = <3>;
#size-cells = <2>;
ranges;
+ phys = <&pcie1_phy>;
+ phy-names = "pciephy";
};
};
--
2.34.1On 3/22/25 4:00 AM, Krishna Chaitanya Chundru wrote:
> Move phy, perst, to root port from the controller node.
>
> Rename perst-gpios to reset-gpios to align with the expected naming
> convention of pci-bus-common.yaml.
>
> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
> ---
[...]
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index 0f2caf36910b..6c21c320a2b5 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -2271,9 +2271,6 @@ pcie1: pcie@1c08000 {
>
> power-domains = <&gcc GCC_PCIE_1_GDSC>;
>
> - phys = <&pcie1_phy>;
> - phy-names = "pciephy";
> -
> pinctrl-names = "default";
> pinctrl-0 = <&pcie1_clkreq_n>;
>
> @@ -2284,7 +2281,7 @@ pcie1: pcie@1c08000 {
>
> status = "disabled";
>
> - pcie@0 {
> + pcieport1: pcie@0 {
pcie1_port0 (or pcie1_port), please
Konrad
On 3/25/2025 12:45 AM, Konrad Dybcio wrote:
> On 3/22/25 4:00 AM, Krishna Chaitanya Chundru wrote:
>> Move phy, perst, to root port from the controller node.
>>
>> Rename perst-gpios to reset-gpios to align with the expected naming
>> convention of pci-bus-common.yaml.
>>
>> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
>> ---
>
> [...]
>
>> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> index 0f2caf36910b..6c21c320a2b5 100644
>> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> @@ -2271,9 +2271,6 @@ pcie1: pcie@1c08000 {
>>
>> power-domains = <&gcc GCC_PCIE_1_GDSC>;
>>
>> - phys = <&pcie1_phy>;
>> - phy-names = "pciephy";
>> -
>> pinctrl-names = "default";
>> pinctrl-0 = <&pcie1_clkreq_n>;
>>
>> @@ -2284,7 +2281,7 @@ pcie1: pcie@1c08000 {
>>
>> status = "disabled";
>>
>> - pcie@0 {
>> + pcieport1: pcie@0 {
>
> pcie1_port0 (or pcie1_port), please
>
pcie1_port0 makes more sense as pcie1 indicates pcie instance
and port0 indicates root port0. I will update this in next
series.
- Krishna Chaitanya.
> Konrad
On Sat, Mar 22, 2025 at 08:30:44AM +0530, Krishna Chaitanya Chundru wrote: > Move phy, perst, to root port from the controller node. > > Rename perst-gpios to reset-gpios to align with the expected naming > convention of pci-bus-common.yaml. > > Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> > --- > arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 5 ++++- This dtb won't work with existing kernels without the driver change. > arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi | 5 ++++- > arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 5 ++++- > arch/arm64/boot/dts/qcom/sc7280.dtsi | 7 +++---- > 4 files changed, 15 insertions(+), 7 deletions(-)
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