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[PATCH v1 3/3] ARM: tegra: Add DFLL clock support on Tegra 4

Svyatoslav Ryhel posted 3 patches 9 months ago
There is a newer version of this series
[PATCH v1 3/3] ARM: tegra: Add DFLL clock support on Tegra 4
Posted by Svyatoslav Ryhel 9 months ago 
Add DFLL clock node to common Tegra114 device tree along with clocks
property to cpu node.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
---
 arch/arm/boot/dts/nvidia/tegra114.dtsi | 34 ++++++++++++++++++++++++++
 1 file changed, 34 insertions(+)

diff --git a/arch/arm/boot/dts/nvidia/tegra114.dtsi b/arch/arm/boot/dts/nvidia/tegra114.dtsi
index 341ec0962460..25d063a47ca5 100644
--- a/arch/arm/boot/dts/nvidia/tegra114.dtsi
+++ b/arch/arm/boot/dts/nvidia/tegra114.dtsi
@@ -4,6 +4,7 @@
 #include <dt-bindings/memory/tegra114-mc.h>
 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/reset/tegra114-car.h>
 #include <dt-bindings/soc/tegra-pmc.h>
 
 #include "tegra114-peripherals-opp.dtsi"
@@ -710,6 +711,30 @@ mipi: mipi@700e3000 {
 		#nvidia,mipi-calibrate-cells = <1>;
 	};
 
+	dfll: clock@70110000 {
+		compatible = "nvidia,tegra114-dfll";
+		reg = <0x70110000 0x100>, /* DFLL control */
+		      <0x70110000 0x100>, /* I2C output control */
+		      <0x70110100 0x100>, /* Integrated I2C controller */
+		      <0x70110200 0x100>; /* Look-up table RAM */
+		interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&tegra_car TEGRA114_CLK_DFLL_SOC>,
+			 <&tegra_car TEGRA114_CLK_DFLL_REF>,
+			 <&tegra_car TEGRA114_CLK_I2C5>;
+		clock-names = "soc", "ref", "i2c";
+		resets = <&tegra_car TEGRA114_RST_DFLL_DVCO>;
+		reset-names = "dvco";
+		#clock-cells = <0>;
+		clock-output-names = "dfllCPU_out";
+		nvidia,sample-rate = <11500>;
+		nvidia,droop-ctrl = <0x00000f00>;
+		nvidia,force-mode = <1>;
+		nvidia,cf = <10>;
+		nvidia,ci = <0>;
+		nvidia,cg = <2>;
+		status = "disabled";
+	};
+
 	mmc@78000000 {
 		compatible = "nvidia,tegra114-sdhci";
 		reg = <0x78000000 0x200>;
@@ -841,6 +866,15 @@ cpu@0 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a15";
 			reg = <0>;
+
+			clocks = <&tegra_car TEGRA114_CLK_CCLK_G>,
+				 <&tegra_car TEGRA114_CLK_CCLK_LP>,
+				 <&tegra_car TEGRA114_CLK_PLL_X>,
+				 <&tegra_car TEGRA114_CLK_PLL_P>,
+				 <&dfll>;
+			clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll";
+			/* FIXME: what's the actual transition time? */
+			clock-latency = <300000>;
 		};
 
 		cpu@1 {
-- 
2.43.0
Re: [PATCH v1 3/3] ARM: tegra: Add DFLL clock support on Tegra 4
Posted by Mikko Perttunen 3 months, 3 weeks ago 
On Friday, March 21, 2025 6:55 PM Svyatoslav Ryhel wrote:
> Add DFLL clock node to common Tegra114 device tree along with clocks
> property to cpu node.
> 
> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
> ---
>  arch/arm/boot/dts/nvidia/tegra114.dtsi | 34 ++++++++++++++++++++++++++
>  1 file changed, 34 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/nvidia/tegra114.dtsi
> b/arch/arm/boot/dts/nvidia/tegra114.dtsi index 341ec0962460..25d063a47ca5
> 100644
> --- a/arch/arm/boot/dts/nvidia/tegra114.dtsi
> +++ b/arch/arm/boot/dts/nvidia/tegra114.dtsi
> @@ -4,6 +4,7 @@
>  #include <dt-bindings/memory/tegra114-mc.h>
>  #include <dt-bindings/pinctrl/pinctrl-tegra.h>
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/reset/tegra114-car.h>
>  #include <dt-bindings/soc/tegra-pmc.h>
> 
>  #include "tegra114-peripherals-opp.dtsi"
> @@ -710,6 +711,30 @@ mipi: mipi@700e3000 {
>  		#nvidia,mipi-calibrate-cells = <1>;
>  	};
> 
> +	dfll: clock@70110000 {
> +		compatible = "nvidia,tegra114-dfll";
> +		reg = <0x70110000 0x100>, /* DFLL control */
> +		      <0x70110000 0x100>, /* I2C output control */
> +		      <0x70110100 0x100>, /* Integrated I2C controller */
> +		      <0x70110200 0x100>; /* Look-up table RAM */
> +		interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&tegra_car TEGRA114_CLK_DFLL_SOC>,
> +			 <&tegra_car TEGRA114_CLK_DFLL_REF>,
> +			 <&tegra_car TEGRA114_CLK_I2C5>;
> +		clock-names = "soc", "ref", "i2c";
> +		resets = <&tegra_car TEGRA114_RST_DFLL_DVCO>;
> +		reset-names = "dvco";
> +		#clock-cells = <0>;
> +		clock-output-names = "dfllCPU_out";
> +		nvidia,sample-rate = <11500>;

Should this be 12500? That would match Tegra124 and a downstream kernel for 
Tegra114 I have.

> +		nvidia,droop-ctrl = <0x00000f00>;
> +		nvidia,force-mode = <1>;
> +		nvidia,cf = <10>;
> +		nvidia,ci = <0>;
> +		nvidia,cg = <2>;
> +		status = "disabled";
> +	};
> +
>  	mmc@78000000 {
>  		compatible = "nvidia,tegra114-sdhci";
>  		reg = <0x78000000 0x200>;
> @@ -841,6 +866,15 @@ cpu@0 {
>  			device_type = "cpu";
>  			compatible = "arm,cortex-a15";
>  			reg = <0>;
> +
> +			clocks = <&tegra_car TEGRA114_CLK_CCLK_G>,
> +				 <&tegra_car TEGRA114_CLK_CCLK_LP>,
> +				 <&tegra_car TEGRA114_CLK_PLL_X>,
> +				 <&tegra_car TEGRA114_CLK_PLL_P>,
> +				 <&dfll>;
> +			clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", 
"dfll";
> +			/* FIXME: what's the actual transition time? */
> +			clock-latency = <300000>;
>  		};
> 
>  		cpu@1 {
Re: [PATCH v1 3/3] ARM: tegra: Add DFLL clock support on Tegra 4
Posted by Svyatoslav Ryhel 3 months, 3 weeks ago 
пт, 22 серп. 2025 р. о 06:05 Mikko Perttunen <mperttunen@nvidia.com> пише:
>
> On Friday, March 21, 2025 6:55 PM Svyatoslav Ryhel wrote:
> > Add DFLL clock node to common Tegra114 device tree along with clocks
> > property to cpu node.
> >
> > Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
> > ---
> >  arch/arm/boot/dts/nvidia/tegra114.dtsi | 34 ++++++++++++++++++++++++++
> >  1 file changed, 34 insertions(+)
> >
> > diff --git a/arch/arm/boot/dts/nvidia/tegra114.dtsi
> > b/arch/arm/boot/dts/nvidia/tegra114.dtsi index 341ec0962460..25d063a47ca5
> > 100644
> > --- a/arch/arm/boot/dts/nvidia/tegra114.dtsi
> > +++ b/arch/arm/boot/dts/nvidia/tegra114.dtsi
> > @@ -4,6 +4,7 @@
> >  #include <dt-bindings/memory/tegra114-mc.h>
> >  #include <dt-bindings/pinctrl/pinctrl-tegra.h>
> >  #include <dt-bindings/interrupt-controller/arm-gic.h>
> > +#include <dt-bindings/reset/tegra114-car.h>
> >  #include <dt-bindings/soc/tegra-pmc.h>
> >
> >  #include "tegra114-peripherals-opp.dtsi"
> > @@ -710,6 +711,30 @@ mipi: mipi@700e3000 {
> >               #nvidia,mipi-calibrate-cells = <1>;
> >       };
> >
> > +     dfll: clock@70110000 {
> > +             compatible = "nvidia,tegra114-dfll";
> > +             reg = <0x70110000 0x100>, /* DFLL control */
> > +                   <0x70110000 0x100>, /* I2C output control */
> > +                   <0x70110100 0x100>, /* Integrated I2C controller */
> > +                   <0x70110200 0x100>; /* Look-up table RAM */
> > +             interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
> > +             clocks = <&tegra_car TEGRA114_CLK_DFLL_SOC>,
> > +                      <&tegra_car TEGRA114_CLK_DFLL_REF>,
> > +                      <&tegra_car TEGRA114_CLK_I2C5>;
> > +             clock-names = "soc", "ref", "i2c";
> > +             resets = <&tegra_car TEGRA114_RST_DFLL_DVCO>;
> > +             reset-names = "dvco";
> > +             #clock-cells = <0>;
> > +             clock-output-names = "dfllCPU_out";
> > +             nvidia,sample-rate = <11500>;
>
> Should this be 12500? That would match Tegra124 and a downstream kernel for
> Tegra114 I have.
>

I referred to tegratab and macallan boards in 3.4 kernel which give
11500, maybe sample-rate was changed to 12500 later with tegra124
addition?

> > +             nvidia,droop-ctrl = <0x00000f00>;
> > +             nvidia,force-mode = <1>;
> > +             nvidia,cf = <10>;
> > +             nvidia,ci = <0>;
> > +             nvidia,cg = <2>;
> > +             status = "disabled";
> > +     };
> > +
> >       mmc@78000000 {
> >               compatible = "nvidia,tegra114-sdhci";
> >               reg = <0x78000000 0x200>;
> > @@ -841,6 +866,15 @@ cpu@0 {
> >                       device_type = "cpu";
> >                       compatible = "arm,cortex-a15";
> >                       reg = <0>;
> > +
> > +                     clocks = <&tegra_car TEGRA114_CLK_CCLK_G>,
> > +                              <&tegra_car TEGRA114_CLK_CCLK_LP>,
> > +                              <&tegra_car TEGRA114_CLK_PLL_X>,
> > +                              <&tegra_car TEGRA114_CLK_PLL_P>,
> > +                              <&dfll>;
> > +                     clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p",
> "dfll";
> > +                     /* FIXME: what's the actual transition time? */
> > +                     clock-latency = <300000>;
> >               };
> >
> >               cpu@1 {
>
>
>
>

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