From: Nitheesh Sekar <quic_nsekar@quicinc.com>
Add phy and controller nodes for a 2-lane Gen2 and
a 1-lane Gen2 PCIe bus. IPQ5018 has 8 MSI SPI interrupts and
one global interrupt.
Signed-off-by: Nitheesh Sekar <quic_nsekar@quicinc.com>
Signed-off-by: Sricharan R <quic_srichara@quicinc.com>
Signed-off-by: George Moussalem <george.moussalem@outlook.com>
---
arch/arm64/boot/dts/qcom/ipq5018.dtsi | 234 +++++++++++++++++++++++++++++++++-
1 file changed, 232 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
index 8914f2ef0bc4..d08034b57e80 100644
--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
@@ -147,6 +147,40 @@ usbphy0: phy@5b000 {
status = "disabled";
};
+ pcie1_phy: phy@7e000{
+ compatible = "qcom,ipq5018-uniphy-pcie-phy";
+ reg = <0x0007e000 0x800>;
+
+ clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
+
+ resets = <&gcc GCC_PCIE1_PHY_BCR>,
+ <&gcc GCC_PCIE1PHY_PHY_BCR>;
+
+ #clock-cells = <0>;
+ #phy-cells = <0>;
+
+ num-lanes = <1>;
+
+ status = "disabled";
+ };
+
+ pcie0_phy: phy@86000{
+ compatible = "qcom,ipq5018-uniphy-pcie-phy";
+ reg = <0x00086000 0x800>;
+
+ clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
+
+ resets = <&gcc GCC_PCIE0_PHY_BCR>,
+ <&gcc GCC_PCIE0PHY_PHY_BCR>;
+
+ #clock-cells = <0>;
+ #phy-cells = <0>;
+
+ num-lanes = <2>;
+
+ status = "disabled";
+ };
+
tlmm: pinctrl@1000000 {
compatible = "qcom,ipq5018-tlmm";
reg = <0x01000000 0x300000>;
@@ -170,8 +204,8 @@ gcc: clock-controller@1800000 {
reg = <0x01800000 0x80000>;
clocks = <&xo_board_clk>,
<&sleep_clk>,
- <0>,
- <0>,
+ <&pcie0_phy>,
+ <&pcie1_phy>,
<0>,
<0>,
<0>,
@@ -387,6 +421,202 @@ frame@b128000 {
status = "disabled";
};
};
+
+ pcie1: pcie@80000000 {
+ compatible = "qcom,pcie-ipq5018";
+ reg = <0x80000000 0xf1d>,
+ <0x80000f20 0xa8>,
+ <0x80001000 0x1000>,
+ <0x00078000 0x3000>,
+ <0x80100000 0x1000>,
+ <0x0007b000 0x1000>;
+ reg-names = "dbi",
+ "elbi",
+ "atu",
+ "parf",
+ "config",
+ "mhi";
+ device_type = "pci";
+ linux,pci-domain = <0>;
+ bus-range = <0x00 0xff>;
+ num-lanes = <1>;
+ max-link-speed = <2>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ phys = <&pcie1_phy>;
+ phy-names ="pciephy";
+
+ ranges = <0x01000000 0 0x00000000 0x80200000 0 0x00100000>,
+ <0x02000000 0 0x80300000 0x80300000 0 0x10000000>;
+
+ msi-map = <0x0 &v2m0 0x0 0xff8>;
+
+ interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0",
+ "msi1",
+ "msi2",
+ "msi3",
+ "msi4",
+ "msi5",
+ "msi6",
+ "msi7",
+ "global";
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 0 142 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &intc 0 0 143 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &intc 0 0 144 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &intc 0 0 145 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>,
+ <&gcc GCC_PCIE1_AXI_M_CLK>,
+ <&gcc GCC_PCIE1_AXI_S_CLK>,
+ <&gcc GCC_PCIE1_AHB_CLK>,
+ <&gcc GCC_PCIE1_AUX_CLK>,
+ <&gcc GCC_PCIE1_AXI_S_BRIDGE_CLK>;
+ clock-names = "iface",
+ "axi_m",
+ "axi_s",
+ "ahb",
+ "aux",
+ "axi_bridge";
+
+ resets = <&gcc GCC_PCIE1_PIPE_ARES>,
+ <&gcc GCC_PCIE1_SLEEP_ARES>,
+ <&gcc GCC_PCIE1_CORE_STICKY_ARES>,
+ <&gcc GCC_PCIE1_AXI_MASTER_ARES>,
+ <&gcc GCC_PCIE1_AXI_SLAVE_ARES>,
+ <&gcc GCC_PCIE1_AHB_ARES>,
+ <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>,
+ <&gcc GCC_PCIE1_AXI_SLAVE_STICKY_ARES>;
+ reset-names = "pipe",
+ "sleep",
+ "sticky",
+ "axi_m",
+ "axi_s",
+ "ahb",
+ "axi_m_sticky",
+ "axi_s_sticky";
+
+ status = "disabled";
+
+ pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
+ };
+
+ pcie0: pcie@a0000000 {
+ compatible = "qcom,pcie-ipq5018";
+ reg = <0xa0000000 0xf1d>,
+ <0xa0000f20 0xa8>,
+ <0xa0001000 0x1000>,
+ <0x00080000 0x3000>,
+ <0xa0100000 0x1000>,
+ <0x00083000 0x1000>;
+ reg-names = "dbi",
+ "elbi",
+ "atu",
+ "parf",
+ "config",
+ "mhi";
+ device_type = "pci";
+ linux,pci-domain = <1>;
+ bus-range = <0x00 0xff>;
+ num-lanes = <2>;
+ max-link-speed = <2>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ phys = <&pcie0_phy>;
+ phy-names ="pciephy";
+
+ ranges = <0x01000000 0 0x00000000 0xa0200000 0 0x00100000>,
+ <0x02000000 0 0xa0300000 0xa0300000 0 0x10000000>;
+
+ msi-map = <0x0 &v2m0 0x0 0xff8>;
+
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0",
+ "msi1",
+ "msi2",
+ "msi3",
+ "msi4",
+ "msi5",
+ "msi6",
+ "msi7",
+ "global";
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 0 75 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &intc 0 0 78 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &intc 0 0 79 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &intc 0 0 83 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
+ <&gcc GCC_PCIE0_AXI_M_CLK>,
+ <&gcc GCC_PCIE0_AXI_S_CLK>,
+ <&gcc GCC_PCIE0_AHB_CLK>,
+ <&gcc GCC_PCIE0_AUX_CLK>,
+ <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>;
+ clock-names = "iface",
+ "axi_m",
+ "axi_s",
+ "ahb",
+ "aux",
+ "axi_bridge";
+
+ resets = <&gcc GCC_PCIE0_PIPE_ARES>,
+ <&gcc GCC_PCIE0_SLEEP_ARES>,
+ <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
+ <&gcc GCC_PCIE0_AXI_MASTER_ARES>,
+ <&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
+ <&gcc GCC_PCIE0_AHB_ARES>,
+ <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>,
+ <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>;
+ reset-names = "pipe",
+ "sleep",
+ "sticky",
+ "axi_m",
+ "axi_s",
+ "ahb",
+ "axi_m_sticky",
+ "axi_s_sticky";
+
+ status = "disabled";
+
+ pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
+ };
};
timer {
--
2.48.1On Fri, Mar 21, 2025 at 04:14:43PM +0400, George Moussalem via B4 Relay wrote:
> From: Nitheesh Sekar <quic_nsekar@quicinc.com>
>
> Add phy and controller nodes for a 2-lane Gen2 and
Controller is Gen 3 capable but you are limiting it to Gen 2.
> a 1-lane Gen2 PCIe bus. IPQ5018 has 8 MSI SPI interrupts and
> one global interrupt.
>
> Signed-off-by: Nitheesh Sekar <quic_nsekar@quicinc.com>
> Signed-off-by: Sricharan R <quic_srichara@quicinc.com>
> Signed-off-by: George Moussalem <george.moussalem@outlook.com>
One comment below. With that addressed,
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> ---
> arch/arm64/boot/dts/qcom/ipq5018.dtsi | 234 +++++++++++++++++++++++++++++++++-
> 1 file changed, 232 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> index 8914f2ef0bc4..d08034b57e80 100644
> --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> @@ -147,6 +147,40 @@ usbphy0: phy@5b000 {
> status = "disabled";
> };
>
> + pcie1_phy: phy@7e000{
> + compatible = "qcom,ipq5018-uniphy-pcie-phy";
> + reg = <0x0007e000 0x800>;
> +
> + clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
> +
> + resets = <&gcc GCC_PCIE1_PHY_BCR>,
> + <&gcc GCC_PCIE1PHY_PHY_BCR>;
> +
> + #clock-cells = <0>;
> + #phy-cells = <0>;
> +
> + num-lanes = <1>;
> +
> + status = "disabled";
> + };
> +
> + pcie0_phy: phy@86000{
> + compatible = "qcom,ipq5018-uniphy-pcie-phy";
> + reg = <0x00086000 0x800>;
> +
> + clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
> +
> + resets = <&gcc GCC_PCIE0_PHY_BCR>,
> + <&gcc GCC_PCIE0PHY_PHY_BCR>;
> +
> + #clock-cells = <0>;
> + #phy-cells = <0>;
> +
> + num-lanes = <2>;
> +
> + status = "disabled";
> + };
> +
> tlmm: pinctrl@1000000 {
> compatible = "qcom,ipq5018-tlmm";
> reg = <0x01000000 0x300000>;
> @@ -170,8 +204,8 @@ gcc: clock-controller@1800000 {
> reg = <0x01800000 0x80000>;
> clocks = <&xo_board_clk>,
> <&sleep_clk>,
> - <0>,
> - <0>,
> + <&pcie0_phy>,
> + <&pcie1_phy>,
> <0>,
> <0>,
> <0>,
> @@ -387,6 +421,202 @@ frame@b128000 {
> status = "disabled";
> };
> };
> +
> + pcie1: pcie@80000000 {
> + compatible = "qcom,pcie-ipq5018";
> + reg = <0x80000000 0xf1d>,
> + <0x80000f20 0xa8>,
> + <0x80001000 0x1000>,
> + <0x00078000 0x3000>,
> + <0x80100000 0x1000>,
> + <0x0007b000 0x1000>;
> + reg-names = "dbi",
> + "elbi",
> + "atu",
> + "parf",
> + "config",
> + "mhi";
> + device_type = "pci";
> + linux,pci-domain = <0>;
> + bus-range = <0x00 0xff>;
> + num-lanes = <1>;
> + max-link-speed = <2>;
This still needs some justification. If Qcom folks didn't reply, atleast move
this to board dts with a comment saying that the link is not coming up with
Gen3.
- Mani
--
மணிவண்ணன் சதாசிவம்
On 3/24/2025 1:26 PM, Manivannan Sadhasivam wrote:
> On Fri, Mar 21, 2025 at 04:14:43PM +0400, George Moussalem via B4 Relay wrote:
>> From: Nitheesh Sekar<quic_nsekar@quicinc.com>
>>
>> Add phy and controller nodes for a 2-lane Gen2 and
> Controller is Gen 3 capable but you are limiting it to Gen 2.
>
>> a 1-lane Gen2 PCIe bus. IPQ5018 has 8 MSI SPI interrupts and
>> one global interrupt.
>>
>> Signed-off-by: Nitheesh Sekar<quic_nsekar@quicinc.com>
>> Signed-off-by: Sricharan R<quic_srichara@quicinc.com>
>> Signed-off-by: George Moussalem<george.moussalem@outlook.com>
> One comment below. With that addressed,
>
> Reviewed-by: Manivannan Sadhasivam<manivannan.sadhasivam@linaro.org>
>
>> ---
>> arch/arm64/boot/dts/qcom/ipq5018.dtsi | 234 +++++++++++++++++++++++++++++++++-
>> 1 file changed, 232 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
>> index 8914f2ef0bc4..d08034b57e80 100644
>> --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
>> @@ -147,6 +147,40 @@ usbphy0: phy@5b000 {
>> status = "disabled";
>> };
>>
>> + pcie1_phy: phy@7e000{
>> + compatible = "qcom,ipq5018-uniphy-pcie-phy";
>> + reg = <0x0007e000 0x800>;
>> +
>> + clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
>> +
>> + resets = <&gcc GCC_PCIE1_PHY_BCR>,
>> + <&gcc GCC_PCIE1PHY_PHY_BCR>;
>> +
>> + #clock-cells = <0>;
>> + #phy-cells = <0>;
>> +
>> + num-lanes = <1>;
>> +
>> + status = "disabled";
>> + };
>> +
>> + pcie0_phy: phy@86000{
>> + compatible = "qcom,ipq5018-uniphy-pcie-phy";
>> + reg = <0x00086000 0x800>;
>> +
>> + clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
>> +
>> + resets = <&gcc GCC_PCIE0_PHY_BCR>,
>> + <&gcc GCC_PCIE0PHY_PHY_BCR>;
>> +
>> + #clock-cells = <0>;
>> + #phy-cells = <0>;
>> +
>> + num-lanes = <2>;
>> +
>> + status = "disabled";
>> + };
>> +
>> tlmm: pinctrl@1000000 {
>> compatible = "qcom,ipq5018-tlmm";
>> reg = <0x01000000 0x300000>;
>> @@ -170,8 +204,8 @@ gcc: clock-controller@1800000 {
>> reg = <0x01800000 0x80000>;
>> clocks = <&xo_board_clk>,
>> <&sleep_clk>,
>> - <0>,
>> - <0>,
>> + <&pcie0_phy>,
>> + <&pcie1_phy>,
>> <0>,
>> <0>,
>> <0>,
>> @@ -387,6 +421,202 @@ frame@b128000 {
>> status = "disabled";
>> };
>> };
>> +
>> + pcie1: pcie@80000000 {
>> + compatible = "qcom,pcie-ipq5018";
>> + reg = <0x80000000 0xf1d>,
>> + <0x80000f20 0xa8>,
>> + <0x80001000 0x1000>,
>> + <0x00078000 0x3000>,
>> + <0x80100000 0x1000>,
>> + <0x0007b000 0x1000>;
>> + reg-names = "dbi",
>> + "elbi",
>> + "atu",
>> + "parf",
>> + "config",
>> + "mhi";
>> + device_type = "pci";
>> + linux,pci-domain = <0>;
>> + bus-range = <0x00 0xff>;
>> + num-lanes = <1>;
>> + max-link-speed = <2>;
> This still needs some justification. If Qcom folks didn't reply, atleast move
> this to board dts with a comment saying that the link is not coming up with
> Gen3.
>
> - Mani
The IPQ5018 PCIe controller can support Gen3, but the PCIe phy is
limited Gen2 and does not supported Gen3.
Hence, it is restricted using the DTSI property.
--
Thanks,
Praveenkumar
On Mon, Mar 24, 2025 at 04:48:34PM +0530, Praveenkumar I wrote:
>
>
> On 3/24/2025 1:26 PM, Manivannan Sadhasivam wrote:
> > On Fri, Mar 21, 2025 at 04:14:43PM +0400, George Moussalem via B4 Relay wrote:
> > > From: Nitheesh Sekar<quic_nsekar@quicinc.com>
> > >
> > > Add phy and controller nodes for a 2-lane Gen2 and
> > Controller is Gen 3 capable but you are limiting it to Gen 2.
> >
> > > a 1-lane Gen2 PCIe bus. IPQ5018 has 8 MSI SPI interrupts and
> > > one global interrupt.
> > >
> > > Signed-off-by: Nitheesh Sekar<quic_nsekar@quicinc.com>
> > > Signed-off-by: Sricharan R<quic_srichara@quicinc.com>
> > > Signed-off-by: George Moussalem<george.moussalem@outlook.com>
> > One comment below. With that addressed,
> >
> > Reviewed-by: Manivannan Sadhasivam<manivannan.sadhasivam@linaro.org>
> >
> > > ---
> > > arch/arm64/boot/dts/qcom/ipq5018.dtsi | 234 +++++++++++++++++++++++++++++++++-
> > > 1 file changed, 232 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> > > index 8914f2ef0bc4..d08034b57e80 100644
> > > --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> > > +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> > > @@ -147,6 +147,40 @@ usbphy0: phy@5b000 {
> > > status = "disabled";
> > > };
> > > + pcie1_phy: phy@7e000{
> > > + compatible = "qcom,ipq5018-uniphy-pcie-phy";
> > > + reg = <0x0007e000 0x800>;
> > > +
> > > + clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
> > > +
> > > + resets = <&gcc GCC_PCIE1_PHY_BCR>,
> > > + <&gcc GCC_PCIE1PHY_PHY_BCR>;
> > > +
> > > + #clock-cells = <0>;
> > > + #phy-cells = <0>;
> > > +
> > > + num-lanes = <1>;
> > > +
> > > + status = "disabled";
> > > + };
> > > +
> > > + pcie0_phy: phy@86000{
> > > + compatible = "qcom,ipq5018-uniphy-pcie-phy";
> > > + reg = <0x00086000 0x800>;
> > > +
> > > + clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
> > > +
> > > + resets = <&gcc GCC_PCIE0_PHY_BCR>,
> > > + <&gcc GCC_PCIE0PHY_PHY_BCR>;
> > > +
> > > + #clock-cells = <0>;
> > > + #phy-cells = <0>;
> > > +
> > > + num-lanes = <2>;
> > > +
> > > + status = "disabled";
> > > + };
> > > +
> > > tlmm: pinctrl@1000000 {
> > > compatible = "qcom,ipq5018-tlmm";
> > > reg = <0x01000000 0x300000>;
> > > @@ -170,8 +204,8 @@ gcc: clock-controller@1800000 {
> > > reg = <0x01800000 0x80000>;
> > > clocks = <&xo_board_clk>,
> > > <&sleep_clk>,
> > > - <0>,
> > > - <0>,
> > > + <&pcie0_phy>,
> > > + <&pcie1_phy>,
> > > <0>,
> > > <0>,
> > > <0>,
> > > @@ -387,6 +421,202 @@ frame@b128000 {
> > > status = "disabled";
> > > };
> > > };
> > > +
> > > + pcie1: pcie@80000000 {
> > > + compatible = "qcom,pcie-ipq5018";
> > > + reg = <0x80000000 0xf1d>,
> > > + <0x80000f20 0xa8>,
> > > + <0x80001000 0x1000>,
> > > + <0x00078000 0x3000>,
> > > + <0x80100000 0x1000>,
> > > + <0x0007b000 0x1000>;
> > > + reg-names = "dbi",
> > > + "elbi",
> > > + "atu",
> > > + "parf",
> > > + "config",
> > > + "mhi";
> > > + device_type = "pci";
> > > + linux,pci-domain = <0>;
> > > + bus-range = <0x00 0xff>;
> > > + num-lanes = <1>;
> > > + max-link-speed = <2>;
> > This still needs some justification. If Qcom folks didn't reply, atleast move
> > this to board dts with a comment saying that the link is not coming up with
> > Gen3.
> >
> > - Mani
> The IPQ5018 PCIe controller can support Gen3, but the PCIe phy is limited
> Gen2 and does not supported Gen3.
Hmm, so if a Gen 3 capable device is connected, the link will not work at Gen 2?
It seems so from the error that George shared previously.
> Hence, it is restricted using the DTSI property.
>
Ok. George, please add a comment for the property stating the reason.
- Mani
--
மணிவண்ணன் சதாசிவம்
On 3/25/2025 10:23 PM, Manivannan Sadhasivam wrote:
> On Mon, Mar 24, 2025 at 04:48:34PM +0530, Praveenkumar I wrote:
>>
>> On 3/24/2025 1:26 PM, Manivannan Sadhasivam wrote:
>>> On Fri, Mar 21, 2025 at 04:14:43PM +0400, George Moussalem via B4 Relay wrote:
>>>> From: Nitheesh Sekar<quic_nsekar@quicinc.com>
>>>>
>>>> Add phy and controller nodes for a 2-lane Gen2 and
>>> Controller is Gen 3 capable but you are limiting it to Gen 2.
>>>
>>>> a 1-lane Gen2 PCIe bus. IPQ5018 has 8 MSI SPI interrupts and
>>>> one global interrupt.
>>>>
>>>> Signed-off-by: Nitheesh Sekar<quic_nsekar@quicinc.com>
>>>> Signed-off-by: Sricharan R<quic_srichara@quicinc.com>
>>>> Signed-off-by: George Moussalem<george.moussalem@outlook.com>
>>> One comment below. With that addressed,
>>>
>>> Reviewed-by: Manivannan Sadhasivam<manivannan.sadhasivam@linaro.org>
>>>
>>>> ---
>>>> arch/arm64/boot/dts/qcom/ipq5018.dtsi | 234 +++++++++++++++++++++++++++++++++-
>>>> 1 file changed, 232 insertions(+), 2 deletions(-)
>>>>
>>>> diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
>>>> index 8914f2ef0bc4..d08034b57e80 100644
>>>> --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
>>>> +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
>>>> @@ -147,6 +147,40 @@ usbphy0: phy@5b000 {
>>>> status = "disabled";
>>>> };
>>>> + pcie1_phy: phy@7e000{
>>>> + compatible = "qcom,ipq5018-uniphy-pcie-phy";
>>>> + reg = <0x0007e000 0x800>;
>>>> +
>>>> + clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
>>>> +
>>>> + resets = <&gcc GCC_PCIE1_PHY_BCR>,
>>>> + <&gcc GCC_PCIE1PHY_PHY_BCR>;
>>>> +
>>>> + #clock-cells = <0>;
>>>> + #phy-cells = <0>;
>>>> +
>>>> + num-lanes = <1>;
>>>> +
>>>> + status = "disabled";
>>>> + };
>>>> +
>>>> + pcie0_phy: phy@86000{
>>>> + compatible = "qcom,ipq5018-uniphy-pcie-phy";
>>>> + reg = <0x00086000 0x800>;
>>>> +
>>>> + clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
>>>> +
>>>> + resets = <&gcc GCC_PCIE0_PHY_BCR>,
>>>> + <&gcc GCC_PCIE0PHY_PHY_BCR>;
>>>> +
>>>> + #clock-cells = <0>;
>>>> + #phy-cells = <0>;
>>>> +
>>>> + num-lanes = <2>;
>>>> +
>>>> + status = "disabled";
>>>> + };
>>>> +
>>>> tlmm: pinctrl@1000000 {
>>>> compatible = "qcom,ipq5018-tlmm";
>>>> reg = <0x01000000 0x300000>;
>>>> @@ -170,8 +204,8 @@ gcc: clock-controller@1800000 {
>>>> reg = <0x01800000 0x80000>;
>>>> clocks = <&xo_board_clk>,
>>>> <&sleep_clk>,
>>>> - <0>,
>>>> - <0>,
>>>> + <&pcie0_phy>,
>>>> + <&pcie1_phy>,
>>>> <0>,
>>>> <0>,
>>>> <0>,
>>>> @@ -387,6 +421,202 @@ frame@b128000 {
>>>> status = "disabled";
>>>> };
>>>> };
>>>> +
>>>> + pcie1: pcie@80000000 {
>>>> + compatible = "qcom,pcie-ipq5018";
>>>> + reg = <0x80000000 0xf1d>,
>>>> + <0x80000f20 0xa8>,
>>>> + <0x80001000 0x1000>,
>>>> + <0x00078000 0x3000>,
>>>> + <0x80100000 0x1000>,
>>>> + <0x0007b000 0x1000>;
>>>> + reg-names = "dbi",
>>>> + "elbi",
>>>> + "atu",
>>>> + "parf",
>>>> + "config",
>>>> + "mhi";
>>>> + device_type = "pci";
>>>> + linux,pci-domain = <0>;
>>>> + bus-range = <0x00 0xff>;
>>>> + num-lanes = <1>;
>>>> + max-link-speed = <2>;
>>> This still needs some justification. If Qcom folks didn't reply, atleast move
>>> this to board dts with a comment saying that the link is not coming up with
>>> Gen3.
>>>
>>> - Mani
>> The IPQ5018 PCIe controller can support Gen3, but the PCIe phy is limited
>> Gen2 and does not supported Gen3.
> Hmm, so if a Gen 3 capable device is connected, the link will not work at Gen 2?
> It seems so from the error that George shared previously.
No, that is not the case. The link will work with a Gen3 capable device
at Gen2 speed. The failure log shared by George indicates a PHY failure,
which is due to IPQ5018 PHY's hardware limitation.
>
>> Hence, it is restricted using the DTSI property.
>>
> Ok. George, please add a comment for the property stating the reason.
>
> - Mani
>
--
Thanks,
Praveenkumar
On Wed, Mar 26, 2025 at 01:11:35PM +0530, Praveenkumar I wrote:
>
>
> On 3/25/2025 10:23 PM, Manivannan Sadhasivam wrote:
> > On Mon, Mar 24, 2025 at 04:48:34PM +0530, Praveenkumar I wrote:
> > >
> > > On 3/24/2025 1:26 PM, Manivannan Sadhasivam wrote:
> > > > On Fri, Mar 21, 2025 at 04:14:43PM +0400, George Moussalem via B4 Relay wrote:
> > > > > From: Nitheesh Sekar<quic_nsekar@quicinc.com>
> > > > >
> > > > > Add phy and controller nodes for a 2-lane Gen2 and
> > > > Controller is Gen 3 capable but you are limiting it to Gen 2.
> > > >
> > > > > a 1-lane Gen2 PCIe bus. IPQ5018 has 8 MSI SPI interrupts and
> > > > > one global interrupt.
> > > > >
> > > > > Signed-off-by: Nitheesh Sekar<quic_nsekar@quicinc.com>
> > > > > Signed-off-by: Sricharan R<quic_srichara@quicinc.com>
> > > > > Signed-off-by: George Moussalem<george.moussalem@outlook.com>
> > > > One comment below. With that addressed,
> > > >
> > > > Reviewed-by: Manivannan Sadhasivam<manivannan.sadhasivam@linaro.org>
> > > >
> > > > > ---
> > > > > arch/arm64/boot/dts/qcom/ipq5018.dtsi | 234 +++++++++++++++++++++++++++++++++-
> > > > > 1 file changed, 232 insertions(+), 2 deletions(-)
> > > > >
> > > > > diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> > > > > index 8914f2ef0bc4..d08034b57e80 100644
> > > > > --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> > > > > +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> > > > > @@ -147,6 +147,40 @@ usbphy0: phy@5b000 {
> > > > > status = "disabled";
> > > > > };
> > > > > + pcie1_phy: phy@7e000{
> > > > > + compatible = "qcom,ipq5018-uniphy-pcie-phy";
> > > > > + reg = <0x0007e000 0x800>;
> > > > > +
> > > > > + clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
> > > > > +
> > > > > + resets = <&gcc GCC_PCIE1_PHY_BCR>,
> > > > > + <&gcc GCC_PCIE1PHY_PHY_BCR>;
> > > > > +
> > > > > + #clock-cells = <0>;
> > > > > + #phy-cells = <0>;
> > > > > +
> > > > > + num-lanes = <1>;
> > > > > +
> > > > > + status = "disabled";
> > > > > + };
> > > > > +
> > > > > + pcie0_phy: phy@86000{
> > > > > + compatible = "qcom,ipq5018-uniphy-pcie-phy";
> > > > > + reg = <0x00086000 0x800>;
> > > > > +
> > > > > + clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
> > > > > +
> > > > > + resets = <&gcc GCC_PCIE0_PHY_BCR>,
> > > > > + <&gcc GCC_PCIE0PHY_PHY_BCR>;
> > > > > +
> > > > > + #clock-cells = <0>;
> > > > > + #phy-cells = <0>;
> > > > > +
> > > > > + num-lanes = <2>;
> > > > > +
> > > > > + status = "disabled";
> > > > > + };
> > > > > +
> > > > > tlmm: pinctrl@1000000 {
> > > > > compatible = "qcom,ipq5018-tlmm";
> > > > > reg = <0x01000000 0x300000>;
> > > > > @@ -170,8 +204,8 @@ gcc: clock-controller@1800000 {
> > > > > reg = <0x01800000 0x80000>;
> > > > > clocks = <&xo_board_clk>,
> > > > > <&sleep_clk>,
> > > > > - <0>,
> > > > > - <0>,
> > > > > + <&pcie0_phy>,
> > > > > + <&pcie1_phy>,
> > > > > <0>,
> > > > > <0>,
> > > > > <0>,
> > > > > @@ -387,6 +421,202 @@ frame@b128000 {
> > > > > status = "disabled";
> > > > > };
> > > > > };
> > > > > +
> > > > > + pcie1: pcie@80000000 {
> > > > > + compatible = "qcom,pcie-ipq5018";
> > > > > + reg = <0x80000000 0xf1d>,
> > > > > + <0x80000f20 0xa8>,
> > > > > + <0x80001000 0x1000>,
> > > > > + <0x00078000 0x3000>,
> > > > > + <0x80100000 0x1000>,
> > > > > + <0x0007b000 0x1000>;
> > > > > + reg-names = "dbi",
> > > > > + "elbi",
> > > > > + "atu",
> > > > > + "parf",
> > > > > + "config",
> > > > > + "mhi";
> > > > > + device_type = "pci";
> > > > > + linux,pci-domain = <0>;
> > > > > + bus-range = <0x00 0xff>;
> > > > > + num-lanes = <1>;
> > > > > + max-link-speed = <2>;
> > > > This still needs some justification. If Qcom folks didn't reply, atleast move
> > > > this to board dts with a comment saying that the link is not coming up with
> > > > Gen3.
> > > >
> > > > - Mani
> > > The IPQ5018 PCIe controller can support Gen3, but the PCIe phy is limited
> > > Gen2 and does not supported Gen3.
> > Hmm, so if a Gen 3 capable device is connected, the link will not work at Gen 2?
> > It seems so from the error that George shared previously.
> No, that is not the case. The link will work with a Gen3 capable device at
> Gen2 speed. The failure log shared by George indicates a PHY failure, which
> is due to IPQ5018 PHY's hardware limitation.
It doesn't matter. If a Gen 3 device is not going to work with the controller +
phy combo, then it is a host hardware limitation. But I'm OK with adding a
comment and limiting the controller link speed.
- Mani
--
மணிவண்ணன் சதாசிவம்
On Mon, Mar 24, 2025 at 04:48:34PM +0530, Praveenkumar I wrote:
>
>
> On 3/24/2025 1:26 PM, Manivannan Sadhasivam wrote:
> > On Fri, Mar 21, 2025 at 04:14:43PM +0400, George Moussalem via B4 Relay wrote:
> > > From: Nitheesh Sekar<quic_nsekar@quicinc.com>
> > >
> > > Add phy and controller nodes for a 2-lane Gen2 and
> > Controller is Gen 3 capable but you are limiting it to Gen 2.
> >
> > > a 1-lane Gen2 PCIe bus. IPQ5018 has 8 MSI SPI interrupts and
> > > one global interrupt.
> > >
> > > Signed-off-by: Nitheesh Sekar<quic_nsekar@quicinc.com>
> > > Signed-off-by: Sricharan R<quic_srichara@quicinc.com>
> > > Signed-off-by: George Moussalem<george.moussalem@outlook.com>
> > One comment below. With that addressed,
> >
> > Reviewed-by: Manivannan Sadhasivam<manivannan.sadhasivam@linaro.org>
> >
> > > ---
> > > arch/arm64/boot/dts/qcom/ipq5018.dtsi | 234 +++++++++++++++++++++++++++++++++-
> > > 1 file changed, 232 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> > > index 8914f2ef0bc4..d08034b57e80 100644
> > > --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> > > +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> > > @@ -147,6 +147,40 @@ usbphy0: phy@5b000 {
> > > status = "disabled";
> > > };
> > > + pcie1_phy: phy@7e000{
> > > + compatible = "qcom,ipq5018-uniphy-pcie-phy";
> > > + reg = <0x0007e000 0x800>;
> > > +
> > > + clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
> > > +
> > > + resets = <&gcc GCC_PCIE1_PHY_BCR>,
> > > + <&gcc GCC_PCIE1PHY_PHY_BCR>;
> > > +
> > > + #clock-cells = <0>;
> > > + #phy-cells = <0>;
> > > +
> > > + num-lanes = <1>;
> > > +
> > > + status = "disabled";
> > > + };
> > > +
> > > + pcie0_phy: phy@86000{
> > > + compatible = "qcom,ipq5018-uniphy-pcie-phy";
> > > + reg = <0x00086000 0x800>;
> > > +
> > > + clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
> > > +
> > > + resets = <&gcc GCC_PCIE0_PHY_BCR>,
> > > + <&gcc GCC_PCIE0PHY_PHY_BCR>;
> > > +
> > > + #clock-cells = <0>;
> > > + #phy-cells = <0>;
> > > +
> > > + num-lanes = <2>;
> > > +
> > > + status = "disabled";
> > > + };
> > > +
> > > tlmm: pinctrl@1000000 {
> > > compatible = "qcom,ipq5018-tlmm";
> > > reg = <0x01000000 0x300000>;
> > > @@ -170,8 +204,8 @@ gcc: clock-controller@1800000 {
> > > reg = <0x01800000 0x80000>;
> > > clocks = <&xo_board_clk>,
> > > <&sleep_clk>,
> > > - <0>,
> > > - <0>,
> > > + <&pcie0_phy>,
> > > + <&pcie1_phy>,
> > > <0>,
> > > <0>,
> > > <0>,
> > > @@ -387,6 +421,202 @@ frame@b128000 {
> > > status = "disabled";
> > > };
> > > };
> > > +
> > > + pcie1: pcie@80000000 {
> > > + compatible = "qcom,pcie-ipq5018";
> > > + reg = <0x80000000 0xf1d>,
> > > + <0x80000f20 0xa8>,
> > > + <0x80001000 0x1000>,
> > > + <0x00078000 0x3000>,
> > > + <0x80100000 0x1000>,
> > > + <0x0007b000 0x1000>;
> > > + reg-names = "dbi",
> > > + "elbi",
> > > + "atu",
> > > + "parf",
> > > + "config",
> > > + "mhi";
> > > + device_type = "pci";
> > > + linux,pci-domain = <0>;
> > > + bus-range = <0x00 0xff>;
> > > + num-lanes = <1>;
> > > + max-link-speed = <2>;
> > This still needs some justification. If Qcom folks didn't reply, atleast move
> > this to board dts with a comment saying that the link is not coming up with
> > Gen3.
> >
> > - Mani
> The IPQ5018 PCIe controller can support Gen3, but the PCIe phy is limited
> Gen2 and does not supported Gen3.
> Hence, it is restricted using the DTSI property.
Ideally this needs to be negotiated between the PCIe host and PHY
drivers.
--
With best wishes
Dmitry
On 3/24/25 12:36 PM, Dmitry Baryshkov wrote:
> On Mon, Mar 24, 2025 at 04:48:34PM +0530, Praveenkumar I wrote:
>>
>>
>> On 3/24/2025 1:26 PM, Manivannan Sadhasivam wrote:
>>> On Fri, Mar 21, 2025 at 04:14:43PM +0400, George Moussalem via B4 Relay wrote:
>>>> From: Nitheesh Sekar<quic_nsekar@quicinc.com>
>>>>
>>>> Add phy and controller nodes for a 2-lane Gen2 and
>>> Controller is Gen 3 capable but you are limiting it to Gen 2.
>>>
>>>> a 1-lane Gen2 PCIe bus. IPQ5018 has 8 MSI SPI interrupts and
>>>> one global interrupt.
>>>>
>>>> Signed-off-by: Nitheesh Sekar<quic_nsekar@quicinc.com>
>>>> Signed-off-by: Sricharan R<quic_srichara@quicinc.com>
>>>> Signed-off-by: George Moussalem<george.moussalem@outlook.com>
>>> One comment below. With that addressed,
>>>
>>> Reviewed-by: Manivannan Sadhasivam<manivannan.sadhasivam@linaro.org>
>>>
>>>> ---
>>>> arch/arm64/boot/dts/qcom/ipq5018.dtsi | 234 +++++++++++++++++++++++++++++++++-
>>>> 1 file changed, 232 insertions(+), 2 deletions(-)
>>>>
>>>> diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
>>>> index 8914f2ef0bc4..d08034b57e80 100644
>>>> --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
>>>> +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
>>>> @@ -147,6 +147,40 @@ usbphy0: phy@5b000 {
>>>> status = "disabled";
>>>> };
>>>> + pcie1_phy: phy@7e000{
>>>> + compatible = "qcom,ipq5018-uniphy-pcie-phy";
>>>> + reg = <0x0007e000 0x800>;
>>>> +
>>>> + clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
>>>> +
>>>> + resets = <&gcc GCC_PCIE1_PHY_BCR>,
>>>> + <&gcc GCC_PCIE1PHY_PHY_BCR>;
>>>> +
>>>> + #clock-cells = <0>;
>>>> + #phy-cells = <0>;
>>>> +
>>>> + num-lanes = <1>;
>>>> +
>>>> + status = "disabled";
>>>> + };
>>>> +
>>>> + pcie0_phy: phy@86000{
>>>> + compatible = "qcom,ipq5018-uniphy-pcie-phy";
>>>> + reg = <0x00086000 0x800>;
>>>> +
>>>> + clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
>>>> +
>>>> + resets = <&gcc GCC_PCIE0_PHY_BCR>,
>>>> + <&gcc GCC_PCIE0PHY_PHY_BCR>;
>>>> +
>>>> + #clock-cells = <0>;
>>>> + #phy-cells = <0>;
>>>> +
>>>> + num-lanes = <2>;
>>>> +
>>>> + status = "disabled";
>>>> + };
>>>> +
>>>> tlmm: pinctrl@1000000 {
>>>> compatible = "qcom,ipq5018-tlmm";
>>>> reg = <0x01000000 0x300000>;
>>>> @@ -170,8 +204,8 @@ gcc: clock-controller@1800000 {
>>>> reg = <0x01800000 0x80000>;
>>>> clocks = <&xo_board_clk>,
>>>> <&sleep_clk>,
>>>> - <0>,
>>>> - <0>,
>>>> + <&pcie0_phy>,
>>>> + <&pcie1_phy>,
>>>> <0>,
>>>> <0>,
>>>> <0>,
>>>> @@ -387,6 +421,202 @@ frame@b128000 {
>>>> status = "disabled";
>>>> };
>>>> };
>>>> +
>>>> + pcie1: pcie@80000000 {
>>>> + compatible = "qcom,pcie-ipq5018";
>>>> + reg = <0x80000000 0xf1d>,
>>>> + <0x80000f20 0xa8>,
>>>> + <0x80001000 0x1000>,
>>>> + <0x00078000 0x3000>,
>>>> + <0x80100000 0x1000>,
>>>> + <0x0007b000 0x1000>;
>>>> + reg-names = "dbi",
>>>> + "elbi",
>>>> + "atu",
>>>> + "parf",
>>>> + "config",
>>>> + "mhi";
>>>> + device_type = "pci";
>>>> + linux,pci-domain = <0>;
>>>> + bus-range = <0x00 0xff>;
>>>> + num-lanes = <1>;
>>>> + max-link-speed = <2>;
>>> This still needs some justification. If Qcom folks didn't reply, atleast move
>>> this to board dts with a comment saying that the link is not coming up with
>>> Gen3.
>>>
>>> - Mani
>> The IPQ5018 PCIe controller can support Gen3, but the PCIe phy is limited
>> Gen2 and does not supported Gen3.
>> Hence, it is restricted using the DTSI property.
>
> Ideally this needs to be negotiated between the PCIe host and PHY
> drivers.
Would it not fall back automatically?
In any case, I'm fine with this, so long as there's a comment above it
Konrad
On Fri, Mar 21, 2025 at 04:14:43PM +0400, George Moussalem via B4 Relay wrote: > From: Nitheesh Sekar <quic_nsekar@quicinc.com> > > Add phy and controller nodes for a 2-lane Gen2 and > a 1-lane Gen2 PCIe bus. IPQ5018 has 8 MSI SPI interrupts and > one global interrupt. > > Signed-off-by: Nitheesh Sekar <quic_nsekar@quicinc.com> > Signed-off-by: Sricharan R <quic_srichara@quicinc.com> > Signed-off-by: George Moussalem <george.moussalem@outlook.com> > --- > arch/arm64/boot/dts/qcom/ipq5018.dtsi | 234 +++++++++++++++++++++++++++++++++- > 1 file changed, 232 insertions(+), 2 deletions(-) > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> -- With best wishes Dmitry
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