From: David Collins <david.collins@oss.qualcomm.com>
Certain TEMP_ALARM GEN2 PMIC peripherals need over-temperature
stage 2 automatic PMIC partial shutdown to be enabled in order to
avoid repeated faults in the event of reaching over-temperature
stage 3. Modify the stage 2 shutdown control logic to ensure that
stage 2 shutdown is enabled on all affected PMICs. Read the
digital major and minor revision registers to identify these
PMICs.
Signed-off-by: David Collins <david.collins@oss.qualcomm.com>
Signed-off-by: Anjelique Melendez <anjelique.melendez@oss.qualcomm.com>
---
drivers/thermal/qcom/qcom-spmi-temp-alarm.c | 32 +++++++++++++++++++--
1 file changed, 30 insertions(+), 2 deletions(-)
diff --git a/drivers/thermal/qcom/qcom-spmi-temp-alarm.c b/drivers/thermal/qcom/qcom-spmi-temp-alarm.c
index c2d59cbfaea9..b2077ff9fe73 100644
--- a/drivers/thermal/qcom/qcom-spmi-temp-alarm.c
+++ b/drivers/thermal/qcom/qcom-spmi-temp-alarm.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2011-2015, 2017, 2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/bitops.h>
@@ -16,6 +17,7 @@
#include "../thermal_hwmon.h"
+#define QPNP_TM_REG_DIG_MINOR 0x00
#define QPNP_TM_REG_DIG_MAJOR 0x01
#define QPNP_TM_REG_TYPE 0x04
#define QPNP_TM_REG_SUBTYPE 0x05
@@ -71,6 +73,7 @@ struct qpnp_tm_chip {
struct device *dev;
struct thermal_zone_device *tz_dev;
unsigned int subtype;
+ unsigned int dig_revision;
long temp;
unsigned int thresh;
unsigned int stage;
@@ -78,6 +81,7 @@ struct qpnp_tm_chip {
/* protects .thresh, .stage and chip registers */
struct mutex lock;
bool initialized;
+ bool require_s2_shutdown;
struct iio_channel *adc;
const long (*temp_map)[THRESH_COUNT][STAGE_COUNT];
@@ -255,7 +259,7 @@ static int qpnp_tm_update_critical_trip_temp(struct qpnp_tm_chip *chip,
skip:
reg |= chip->thresh;
- if (disable_s2_shutdown)
+ if (disable_s2_shutdown && !chip->require_s2_shutdown)
reg |= SHUTDOWN_CTRL1_OVERRIDE_S2;
return qpnp_tm_write(chip, QPNP_TM_REG_SHUTDOWN_CTRL1, reg);
@@ -350,7 +354,7 @@ static int qpnp_tm_probe(struct platform_device *pdev)
{
struct qpnp_tm_chip *chip;
struct device_node *node;
- u8 type, subtype, dig_major;
+ u8 type, subtype, dig_major, dig_minor;
u32 res;
int ret, irq;
@@ -403,6 +407,30 @@ static int qpnp_tm_probe(struct platform_device *pdev)
return dev_err_probe(&pdev->dev, ret,
"could not read dig_major\n");
+ ret = qpnp_tm_read(chip, QPNP_TM_REG_DIG_MINOR, &dig_minor);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "could not read dig_minor\n");
+ return ret;
+ }
+
+ chip->dig_revision = (dig_major << 8) | dig_minor;
+
+ if (chip->subtype == QPNP_TM_SUBTYPE_GEN2) {
+ /*
+ * Check if stage 2 automatic partial shutdown must remain
+ * enabled to avoid potential repeated faults upon reaching
+ * over-temperature stage 3.
+ */
+ switch (chip->dig_revision) {
+ case 0x0001:
+ case 0x0002:
+ case 0x0100:
+ case 0x0101:
+ chip->require_s2_shutdown = true;
+ break;
+ }
+ }
+
if (type != QPNP_TM_TYPE || (subtype != QPNP_TM_SUBTYPE_GEN1
&& subtype != QPNP_TM_SUBTYPE_GEN2)) {
dev_err(&pdev->dev, "invalid type 0x%02x or subtype 0x%02x\n",
--
2.34.1On Thu, Mar 20, 2025 at 01:24:04PM -0700, Anjelique Melendez wrote:
> From: David Collins <david.collins@oss.qualcomm.com>
>
> Certain TEMP_ALARM GEN2 PMIC peripherals need over-temperature
> stage 2 automatic PMIC partial shutdown to be enabled in order to
> avoid repeated faults in the event of reaching over-temperature
> stage 3. Modify the stage 2 shutdown control logic to ensure that
> stage 2 shutdown is enabled on all affected PMICs. Read the
> digital major and minor revision registers to identify these
> PMICs.
>
> Signed-off-by: David Collins <david.collins@oss.qualcomm.com>
> Signed-off-by: Anjelique Melendez <anjelique.melendez@oss.qualcomm.com>
> ---
> drivers/thermal/qcom/qcom-spmi-temp-alarm.c | 32 +++++++++++++++++++--
> 1 file changed, 30 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/thermal/qcom/qcom-spmi-temp-alarm.c b/drivers/thermal/qcom/qcom-spmi-temp-alarm.c
> index c2d59cbfaea9..b2077ff9fe73 100644
> --- a/drivers/thermal/qcom/qcom-spmi-temp-alarm.c
> +++ b/drivers/thermal/qcom/qcom-spmi-temp-alarm.c
> @@ -1,6 +1,7 @@
> // SPDX-License-Identifier: GPL-2.0-only
> /*
> * Copyright (c) 2011-2015, 2017, 2020, The Linux Foundation. All rights reserved.
> + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
> */
>
> #include <linux/bitops.h>
> @@ -16,6 +17,7 @@
>
> #include "../thermal_hwmon.h"
>
> +#define QPNP_TM_REG_DIG_MINOR 0x00
> #define QPNP_TM_REG_DIG_MAJOR 0x01
> #define QPNP_TM_REG_TYPE 0x04
> #define QPNP_TM_REG_SUBTYPE 0x05
> @@ -71,6 +73,7 @@ struct qpnp_tm_chip {
> struct device *dev;
> struct thermal_zone_device *tz_dev;
> unsigned int subtype;
> + unsigned int dig_revision;
> long temp;
> unsigned int thresh;
> unsigned int stage;
> @@ -78,6 +81,7 @@ struct qpnp_tm_chip {
> /* protects .thresh, .stage and chip registers */
> struct mutex lock;
> bool initialized;
> + bool require_s2_shutdown;
>
> struct iio_channel *adc;
> const long (*temp_map)[THRESH_COUNT][STAGE_COUNT];
> @@ -255,7 +259,7 @@ static int qpnp_tm_update_critical_trip_temp(struct qpnp_tm_chip *chip,
>
> skip:
> reg |= chip->thresh;
> - if (disable_s2_shutdown)
> + if (disable_s2_shutdown && !chip->require_s2_shutdown)
> reg |= SHUTDOWN_CTRL1_OVERRIDE_S2;
>
> return qpnp_tm_write(chip, QPNP_TM_REG_SHUTDOWN_CTRL1, reg);
> @@ -350,7 +354,7 @@ static int qpnp_tm_probe(struct platform_device *pdev)
> {
> struct qpnp_tm_chip *chip;
> struct device_node *node;
> - u8 type, subtype, dig_major;
> + u8 type, subtype, dig_major, dig_minor;
> u32 res;
> int ret, irq;
>
> @@ -403,6 +407,30 @@ static int qpnp_tm_probe(struct platform_device *pdev)
> return dev_err_probe(&pdev->dev, ret,
> "could not read dig_major\n");
>
> + ret = qpnp_tm_read(chip, QPNP_TM_REG_DIG_MINOR, &dig_minor);
> + if (ret < 0) {
> + dev_err(&pdev->dev, "could not read dig_minor\n");
> + return ret;
> + }
> +
> + chip->dig_revision = (dig_major << 8) | dig_minor;
I would move this inside the block below.
> + if (chip->subtype == QPNP_TM_SUBTYPE_GEN2) {
> + /*
> + * Check if stage 2 automatic partial shutdown must remain
> + * enabled to avoid potential repeated faults upon reaching
> + * over-temperature stage 3.
> + */
> + switch (chip->dig_revision) {
> + case 0x0001:
> + case 0x0002:
> + case 0x0100:
> + case 0x0101:
> + chip->require_s2_shutdown = true;
> + break;
> + }
> + }
And move this block after the test below
> +
> if (type != QPNP_TM_TYPE || (subtype != QPNP_TM_SUBTYPE_GEN1
> && subtype != QPNP_TM_SUBTYPE_GEN2)) {
> dev_err(&pdev->dev, "invalid type 0x%02x or subtype 0x%02x\n",
> --
> 2.34.1
>
--
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On Thu, Mar 20, 2025 at 01:24:04PM -0700, Anjelique Melendez wrote: > From: David Collins <david.collins@oss.qualcomm.com> > > Certain TEMP_ALARM GEN2 PMIC peripherals need over-temperature > stage 2 automatic PMIC partial shutdown to be enabled in order to > avoid repeated faults in the event of reaching over-temperature > stage 3. Modify the stage 2 shutdown control logic to ensure that > stage 2 shutdown is enabled on all affected PMICs. Read the > digital major and minor revision registers to identify these > PMICs. It would be nice to mention affected PMICs (at least thsoe supported upstream). > > Signed-off-by: David Collins <david.collins@oss.qualcomm.com> > Signed-off-by: Anjelique Melendez <anjelique.melendez@oss.qualcomm.com> > --- > drivers/thermal/qcom/qcom-spmi-temp-alarm.c | 32 +++++++++++++++++++-- > 1 file changed, 30 insertions(+), 2 deletions(-) > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> -- With best wishes Dmitry
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