From: Frank Li <Frank.Li@nxp.com>
Return the offset from CPU physical address to the parent bus address of
the specified element of the devicetree 'reg' property.
[bhelgaas: return offset, split .cpu_addr_fixup() checking and debug to
separate patch]
Link: https://lore.kernel.org/r/20250313-pci_fixup_addr-v11-5-01d2313502ab@nxp.com
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
---
drivers/pci/controller/dwc/pcie-designware.c | 23 ++++++++++++++++++++
drivers/pci/controller/dwc/pcie-designware.h | 3 +++
2 files changed, 26 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index 9d0a5f75effc..0a35e36da703 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -16,6 +16,7 @@
#include <linux/gpio/consumer.h>
#include <linux/ioport.h>
#include <linux/of.h>
+#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/sizes.h>
#include <linux/types.h>
@@ -1105,3 +1106,25 @@ void dw_pcie_setup(struct dw_pcie *pci)
dw_pcie_link_set_max_link_width(pci, pci->num_lanes);
}
+
+resource_size_t dw_pcie_parent_bus_offset(struct dw_pcie *pci,
+ const char *reg_name,
+ resource_size_t cpu_phy_addr)
+{
+ struct device *dev = pci->dev;
+ struct device_node *np = dev->of_node;
+ int index;
+ u64 reg_addr;
+
+ /* Look up reg_name address on parent bus */
+ index = of_property_match_string(np, "reg-names", reg_name);
+
+ if (index < 0) {
+ dev_err(dev, "No %s in devicetree \"reg\" property\n", reg_name);
+ return 0;
+ }
+
+ of_property_read_reg(np, index, ®_addr, NULL);
+
+ return cpu_phy_addr - reg_addr;
+}
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index d0d8c622a6e8..16548b01347d 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -500,6 +500,9 @@ void dw_pcie_setup(struct dw_pcie *pci);
void dw_pcie_iatu_detect(struct dw_pcie *pci);
int dw_pcie_edma_detect(struct dw_pcie *pci);
void dw_pcie_edma_remove(struct dw_pcie *pci);
+resource_size_t dw_pcie_parent_bus_offset(struct dw_pcie *pci,
+ const char *reg_name,
+ resource_size_t cpu_phy_addr);
static inline void dw_pcie_writel_dbi(struct dw_pcie *pci, u32 reg, u32 val)
{
--
2.34.1On Sat, Mar 15, 2025 at 03:15:40PM -0500, Bjorn Helgaas wrote:
> From: Frank Li <Frank.Li@nxp.com>
>
> Return the offset from CPU physical address to the parent bus address of
> the specified element of the devicetree 'reg' property.
>
> [bhelgaas: return offset, split .cpu_addr_fixup() checking and debug to
> separate patch]
> Link: https://lore.kernel.org/r/20250313-pci_fixup_addr-v11-5-01d2313502ab@nxp.com
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
> ---
> drivers/pci/controller/dwc/pcie-designware.c | 23 ++++++++++++++++++++
> drivers/pci/controller/dwc/pcie-designware.h | 3 +++
> 2 files changed, 26 insertions(+)
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
> index 9d0a5f75effc..0a35e36da703 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.c
> +++ b/drivers/pci/controller/dwc/pcie-designware.c
> @@ -16,6 +16,7 @@
> #include <linux/gpio/consumer.h>
> #include <linux/ioport.h>
> #include <linux/of.h>
> +#include <linux/of_address.h>
> #include <linux/platform_device.h>
> #include <linux/sizes.h>
> #include <linux/types.h>
> @@ -1105,3 +1106,25 @@ void dw_pcie_setup(struct dw_pcie *pci)
>
> dw_pcie_link_set_max_link_width(pci, pci->num_lanes);
> }
> +
> +resource_size_t dw_pcie_parent_bus_offset(struct dw_pcie *pci,
> + const char *reg_name,
> + resource_size_t cpu_phy_addr)
> +{
s/cpu_phy_addr/cpu_phys_addr/g
'phy' usually refers to the physical layer IP block. So 'cpu_phy_addr' sounds
like the address of the CPU PHY.
> + struct device *dev = pci->dev;
> + struct device_node *np = dev->of_node;
> + int index;
> + u64 reg_addr;
> +
> + /* Look up reg_name address on parent bus */
'parent bus' is not accurate as the below code checks for the 'reg_name' in
current PCI controller node.
> + index = of_property_match_string(np, "reg-names", reg_name);
> +
> + if (index < 0) {
> + dev_err(dev, "No %s in devicetree \"reg\" property\n", reg_name);
Both of these callers are checking for the existence of the 'reg_name' property
before calling this API. So this check seems to be redundant (for now).
- Mani
--
மணிவண்ணன் சதாசிவம்
On Mon, Mar 24, 2025 at 10:48:23PM +0530, Manivannan Sadhasivam wrote:
> On Sat, Mar 15, 2025 at 03:15:40PM -0500, Bjorn Helgaas wrote:
> > From: Frank Li <Frank.Li@nxp.com>
> >
> > Return the offset from CPU physical address to the parent bus address of
> > the specified element of the devicetree 'reg' property.
> > +resource_size_t dw_pcie_parent_bus_offset(struct dw_pcie *pci,
> > + const char *reg_name,
> > + resource_size_t cpu_phy_addr)
> > +{
>
> s/cpu_phy_addr/cpu_phys_addr/g
Fixed, thanks!
> > + struct device *dev = pci->dev;
> > + struct device_node *np = dev->of_node;
> > + int index;
> > + u64 reg_addr;
> > +
> > + /* Look up reg_name address on parent bus */
>
> 'parent bus' is not accurate as the below code checks for the 'reg_name' in
> current PCI controller node.
We want the address of "reg_name" on the node's primary side. We've
been calling that the "parent bus address", I guess because it's the
address on the "parent bus" of the node.
I'm not sure what the best term is for this. Do you have a
suggestion?
If "parent bus address" is the wrong term, maybe we need to rename
dw_pcie_parent_bus_offset() itself?
Currently we pass in cpu_phys_addr, but this function doesn't need it
except for the debug code added later. I would really rather have
something like this in the callers:
pci->parent_bus_offset = pp->cfg0_base -
dw_pcie_parent_bus_addr(pci, "config");
because then the offset is computed sort of at the same level where
it's used, and a grep for "cfg0_base" would find both the set and the
use and they would be easy to match up.
> > + index = of_property_match_string(np, "reg-names", reg_name);
> > +
> > + if (index < 0) {
> > + dev_err(dev, "No %s in devicetree \"reg\" property\n", reg_name);
>
> Both of these callers are checking for the existence of the
> 'reg_name' property before calling this API. So this check seems to
> be redundant (for now).
True, but I don't see a way to enforce the caller checks. I don't
like the idea of calling of_property_read_reg(np, index, ...) where we
have to look the caller to verify that "index" is valid.
Bjorn
On Mon, Mar 24, 2025 at 01:28:27PM -0500, Bjorn Helgaas wrote:
> On Mon, Mar 24, 2025 at 10:48:23PM +0530, Manivannan Sadhasivam wrote:
> > On Sat, Mar 15, 2025 at 03:15:40PM -0500, Bjorn Helgaas wrote:
> > > From: Frank Li <Frank.Li@nxp.com>
> > >
> > > Return the offset from CPU physical address to the parent bus address of
> > > the specified element of the devicetree 'reg' property.
>
> > > +resource_size_t dw_pcie_parent_bus_offset(struct dw_pcie *pci,
> > > + const char *reg_name,
> > > + resource_size_t cpu_phy_addr)
> > > +{
> >
> > s/cpu_phy_addr/cpu_phys_addr/g
>
> Fixed, thanks!
>
> > > + struct device *dev = pci->dev;
> > > + struct device_node *np = dev->of_node;
> > > + int index;
> > > + u64 reg_addr;
> > > +
> > > + /* Look up reg_name address on parent bus */
> >
> > 'parent bus' is not accurate as the below code checks for the 'reg_name' in
> > current PCI controller node.
>
> We want the address of "reg_name" on the node's primary side. We've
> been calling that the "parent bus address", I guess because it's the
> address on the "parent bus" of the node.
>
Yeah, 'parent bus address' sounds bogus to me. 'ranges' property is described
as:
ranges = <child_addr parent_addr child_size>
Here, child_addr refers to the PCIe host controller's view of the address space
and parent_addr refers to the CPU's view of the address space.
So the register address described in the PCIe controller node is not a 'parent
bus address'.
> I'm not sure what the best term is for this. Do you have a
> suggestion?
>
We are just extracting the offset between translated (cpu_phy_addr) and
untranslated (reg_addr) addresses of a specific register. Maybe the function
should just return the 'untranslated address' and the caller should compute the
offset to make it simple?
> If "parent bus address" is the wrong term, maybe we need to rename
> dw_pcie_parent_bus_offset() itself?
>
Yes!
> Currently we pass in cpu_phys_addr, but this function doesn't need it
> except for the debug code added later. I would really rather have
> something like this in the callers:
>
> pci->parent_bus_offset = pp->cfg0_base -
> dw_pcie_parent_bus_addr(pci, "config");
>
I agree. This should become, dw_pcie_get_untranslated_addr().
> because then the offset is computed sort of at the same level where
> it's used, and a grep for "cfg0_base" would find both the set and the
> use and they would be easy to match up.
>
> > > + index = of_property_match_string(np, "reg-names", reg_name);
> > > +
> > > + if (index < 0) {
> > > + dev_err(dev, "No %s in devicetree \"reg\" property\n", reg_name);
> >
> > Both of these callers are checking for the existence of the
> > 'reg_name' property before calling this API. So this check seems to
> > be redundant (for now).
>
> True, but I don't see a way to enforce the caller checks. I don't
> like the idea of calling of_property_read_reg(np, index, ...) where we
> have to look the caller to verify that "index" is valid.
>
Ok.
- Mani
--
மணிவண்ணன் சதாசிவம்
On Tue, Mar 25, 2025 at 11:59:14PM +0530, Manivannan Sadhasivam wrote:
> On Mon, Mar 24, 2025 at 01:28:27PM -0500, Bjorn Helgaas wrote:
> > On Mon, Mar 24, 2025 at 10:48:23PM +0530, Manivannan Sadhasivam wrote:
> > > On Sat, Mar 15, 2025 at 03:15:40PM -0500, Bjorn Helgaas wrote:
> > > > From: Frank Li <Frank.Li@nxp.com>
> > > >
> > > > Return the offset from CPU physical address to the parent bus address of
> > > > the specified element of the devicetree 'reg' property.
> >
> > > > +resource_size_t dw_pcie_parent_bus_offset(struct dw_pcie *pci,
> > > > + const char *reg_name,
> > > > + resource_size_t cpu_phy_addr)
> > > > +{
> > >
> > > s/cpu_phy_addr/cpu_phys_addr/g
> >
> > Fixed, thanks!
> >
> > > > + struct device *dev = pci->dev;
> > > > + struct device_node *np = dev->of_node;
> > > > + int index;
> > > > + u64 reg_addr;
> > > > +
> > > > + /* Look up reg_name address on parent bus */
> > >
> > > 'parent bus' is not accurate as the below code checks for the 'reg_name' in
> > > current PCI controller node.
> >
> > We want the address of "reg_name" on the node's primary side. We've
> > been calling that the "parent bus address", I guess because it's the
> > address on the "parent bus" of the node.
> >
>
> Yeah, 'parent bus address' sounds bogus to me. 'ranges' property is described
> as:
>
> ranges = <child_addr parent_addr child_size>
>
> Here, child_addr refers to the PCIe host controller's view of the address space
> and parent_addr refers to the CPU's view of the address space.
>
> So the register address described in the PCIe controller node is not a 'parent
> bus address'.
All should be parent bus address. See Rob's comments
https://lore.kernel.org/imx/20240927221831.GA135061-robh@kernel.org/
bus{
ranges = <child_addr parent_addr child_size>
pcie {
All address here, will be translated by bus's ranges, which
use 1:1 map if out of ranges by default.
from pcie node (children node of bus) view, the 'child_addr'
is parent node (bus)'s output address.
}
}
bus may not only one layer to CPU.
bus1 {
ranges = <...>
bus2 {
ranges = <...>
bus3 {
ranges = <...>
All address here is parent's node (bus3)'s bus address
So, 'parent bus address' means the parent node's
output bus address.
};
};
};
Frank
>
> > I'm not sure what the best term is for this. Do you have a
> > suggestion?
> >
>
> We are just extracting the offset between translated (cpu_phy_addr) and
> untranslated (reg_addr) addresses of a specific register. Maybe the function
> should just return the 'untranslated address' and the caller should compute the
> offset to make it simple?
>
> > If "parent bus address" is the wrong term, maybe we need to rename
> > dw_pcie_parent_bus_offset() itself?
> >
>
> Yes!
>
> > Currently we pass in cpu_phys_addr, but this function doesn't need it
> > except for the debug code added later. I would really rather have
> > something like this in the callers:
> >
> > pci->parent_bus_offset = pp->cfg0_base -
> > dw_pcie_parent_bus_addr(pci, "config");
> >
>
> I agree. This should become, dw_pcie_get_untranslated_addr().
>
> > because then the offset is computed sort of at the same level where
> > it's used, and a grep for "cfg0_base" would find both the set and the
> > use and they would be easy to match up.
> >
> > > > + index = of_property_match_string(np, "reg-names", reg_name);
> > > > +
> > > > + if (index < 0) {
> > > > + dev_err(dev, "No %s in devicetree \"reg\" property\n", reg_name);
> > >
> > > Both of these callers are checking for the existence of the
> > > 'reg_name' property before calling this API. So this check seems to
> > > be redundant (for now).
> >
> > True, but I don't see a way to enforce the caller checks. I don't
> > like the idea of calling of_property_read_reg(np, index, ...) where we
> > have to look the caller to verify that "index" is valid.
> >
>
> Ok.
>
> - Mani
>
> --
> மணிவண்ணன் சதாசிவம்
On Sat, Mar 15, 2025 at 03:15:40PM -0500, Bjorn Helgaas wrote:
> From: Frank Li <Frank.Li@nxp.com>
>
> Return the offset from CPU physical address to the parent bus address of
> the specified element of the devicetree 'reg' property.
>
> [bhelgaas: return offset, split .cpu_addr_fixup() checking and debug to
> separate patch]
> Link: https://lore.kernel.org/r/20250313-pci_fixup_addr-v11-5-01d2313502ab@nxp.com
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
> ---
look good!
> drivers/pci/controller/dwc/pcie-designware.c | 23 ++++++++++++++++++++
> drivers/pci/controller/dwc/pcie-designware.h | 3 +++
> 2 files changed, 26 insertions(+)
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
> index 9d0a5f75effc..0a35e36da703 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.c
> +++ b/drivers/pci/controller/dwc/pcie-designware.c
> @@ -16,6 +16,7 @@
> #include <linux/gpio/consumer.h>
> #include <linux/ioport.h>
> #include <linux/of.h>
> +#include <linux/of_address.h>
> #include <linux/platform_device.h>
> #include <linux/sizes.h>
> #include <linux/types.h>
> @@ -1105,3 +1106,25 @@ void dw_pcie_setup(struct dw_pcie *pci)
>
> dw_pcie_link_set_max_link_width(pci, pci->num_lanes);
> }
> +
> +resource_size_t dw_pcie_parent_bus_offset(struct dw_pcie *pci,
> + const char *reg_name,
> + resource_size_t cpu_phy_addr)
> +{
> + struct device *dev = pci->dev;
> + struct device_node *np = dev->of_node;
> + int index;
> + u64 reg_addr;
> +
> + /* Look up reg_name address on parent bus */
> + index = of_property_match_string(np, "reg-names", reg_name);
> +
> + if (index < 0) {
> + dev_err(dev, "No %s in devicetree \"reg\" property\n", reg_name);
> + return 0;
> + }
> +
> + of_property_read_reg(np, index, ®_addr, NULL);
> +
> + return cpu_phy_addr - reg_addr;
> +}
> diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> index d0d8c622a6e8..16548b01347d 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.h
> +++ b/drivers/pci/controller/dwc/pcie-designware.h
> @@ -500,6 +500,9 @@ void dw_pcie_setup(struct dw_pcie *pci);
> void dw_pcie_iatu_detect(struct dw_pcie *pci);
> int dw_pcie_edma_detect(struct dw_pcie *pci);
> void dw_pcie_edma_remove(struct dw_pcie *pci);
> +resource_size_t dw_pcie_parent_bus_offset(struct dw_pcie *pci,
> + const char *reg_name,
> + resource_size_t cpu_phy_addr);
>
> static inline void dw_pcie_writel_dbi(struct dw_pcie *pci, u32 reg, u32 val)
> {
> --
> 2.34.1
>
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