Add dt-bindings for Aspeed for Aspeed LPC POST code capture controller.
Signed-off-by: Kevin Chen <kevin_chen@aspeedtech.com>
---
.../devicetree/bindings/mfd/aspeed-lpc.yaml | 38 +++++++++++++++++++
1 file changed, 38 insertions(+)
diff --git a/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml b/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml
index 5dfe77aca167..178c151a19ba 100644
--- a/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml
+++ b/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml
@@ -149,6 +149,37 @@ patternProperties:
- interrupts
- snoop-ports
+ "^lpc-pcc@[0-9a-f]+$":
+ type: object
+ additionalProperties: false
+
+ description:
+ The LPC pcc interface allows the BMC to listen on and record the data
+ bytes written by the Host to the targeted LPC I/O pots.
+
+ properties:
+ compatible:
+ items:
+ - enum:
+ - aspeed,ast2600-lpc-pcc
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ pcc-ports:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ description:
+ As a device handshake with a host using the port-mmaped I/O in x86
+ architecture, need to handle specific which port I/O address for use.
+
+ required:
+ - compatible
+ - interrupts
+ - pcc-ports
+
"^uart-routing@[0-9a-f]+$":
$ref: /schemas/soc/aspeed/uart-routing.yaml#
description: The UART routing control under LPC register space
@@ -176,6 +207,13 @@ examples:
#size-cells = <1>;
ranges = <0x0 0x1e789000 0x1000>;
+ lpc_pcc: lpc-pcc@0 {
+ compatible = "aspeed,ast2600-lpc-pcc";
+ reg = <0x0 0x140>;
+ interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+ pcc-ports = <0x80>;
+ };
+
lpc_ctrl: lpc-ctrl@80 {
compatible = "aspeed,ast2600-lpc-ctrl";
reg = <0x80 0x80>;
--
2.34.1