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[PATCH v2 3/3] ARM: tegra124: complete HOST1X devices binding

Svyatoslav Ryhel posted 3 patches 11 months, 1 week ago
There is a newer version of this series
[PATCH v2 3/3] ARM: tegra124: complete HOST1X devices binding
Posted by Svyatoslav Ryhel 11 months, 1 week ago 
Add nodes for devices on the HOST1X bus: VI, ISP, ISPB, MSENC and TSEC.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
---
 arch/arm/boot/dts/nvidia/tegra124.dtsi | 65 ++++++++++++++++++++++++++
 1 file changed, 65 insertions(+)

diff --git a/arch/arm/boot/dts/nvidia/tegra124.dtsi b/arch/arm/boot/dts/nvidia/tegra124.dtsi
index ec4f0e346b2b..8181e5d88654 100644
--- a/arch/arm/boot/dts/nvidia/tegra124.dtsi
+++ b/arch/arm/boot/dts/nvidia/tegra124.dtsi
@@ -103,6 +103,45 @@ host1x@50000000 {
 
 		ranges = <0 0x54000000 0 0x54000000 0 0x01000000>;
 
+		vi@54080000 {
+			compatible = "nvidia,tegra124-vi";
+			reg = <0x0 0x54080000 0x0 0x00040000>;
+			interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&tegra_car TEGRA124_CLK_VI>;
+			resets = <&tegra_car 20>;
+			reset-names = "vi";
+
+			iommus = <&mc TEGRA_SWGROUP_VI>;
+
+			status = "disabled";
+		};
+
+		isp@54600000 {
+			compatible = "nvidia,tegra124-isp";
+			reg = <0x0 0x54600000 0x0 0x00040000>;
+			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&tegra_car TEGRA124_CLK_ISP>;
+			resets = <&tegra_car TEGRA124_CLK_ISP>;
+			reset-names = "isp";
+
+			iommus = <&mc TEGRA_SWGROUP_ISP2>;
+
+			status = "disabled";
+		};
+
+		isp@54680000 {
+			compatible = "nvidia,tegra124-isp";
+			reg = <0x0 0x54680000 0x0 0x00040000>;
+			interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&tegra_car TEGRA124_CLK_ISPB>;
+			resets = <&tegra_car TEGRA124_CLK_ISPB>;
+			reset-names = "ispb";
+
+			iommus = <&mc TEGRA_SWGROUP_ISP2B>;
+
+			status = "disabled";
+		};
+
 		dc@54200000 {
 			compatible = "nvidia,tegra124-dc";
 			reg = <0x0 0x54200000 0x0 0x00040000>;
@@ -209,6 +248,32 @@ dsib: dsi@54400000 {
 			#size-cells = <0>;
 		};
 
+		msenc@544c0000 {
+			compatible = "nvidia,tegra124-msenc";
+			reg = <0x0 0x544c0000 0x0 0x00040000>;
+			interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&tegra_car TEGRA124_CLK_MSENC>;
+			resets = <&tegra_car TEGRA124_CLK_MSENC>;
+			reset-names = "msenc";
+
+			iommus = <&mc TEGRA_SWGROUP_MSENC>;
+
+			status = "disabled";
+		};
+
+		tsec@54500000 {
+			compatible = "nvidia,tegra124-tsec";
+			reg = <0x0 0x54500000 0x0 0x00040000>;
+			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&tegra_car TEGRA124_CLK_TSEC>;
+			resets = <&tegra_car TEGRA124_CLK_TSEC>;
+			reset-names = "tsec";
+
+			iommus = <&mc TEGRA_SWGROUP_TSEC>;
+
+			status = "disabled";
+		};
+
 		sor@54540000 {
 			compatible = "nvidia,tegra124-sor";
 			reg = <0x0 0x54540000 0x0 0x00040000>;
-- 
2.43.0
Re: [PATCH v2 3/3] ARM: tegra124: complete HOST1X devices binding
Posted by Svyatoslav Ryhel 11 months, 1 week ago 
пт, 7 бер. 2025 р. о 10:11 Svyatoslav Ryhel <clamor95@gmail.com> пише:
>
> Add nodes for devices on the HOST1X bus: VI, ISP, ISPB, MSENC and TSEC.
>
> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
> ---
>  arch/arm/boot/dts/nvidia/tegra124.dtsi | 65 ++++++++++++++++++++++++++
>  1 file changed, 65 insertions(+)
>
> diff --git a/arch/arm/boot/dts/nvidia/tegra124.dtsi b/arch/arm/boot/dts/nvidia/tegra124.dtsi
> index ec4f0e346b2b..8181e5d88654 100644
> --- a/arch/arm/boot/dts/nvidia/tegra124.dtsi
> +++ b/arch/arm/boot/dts/nvidia/tegra124.dtsi
> @@ -103,6 +103,45 @@ host1x@50000000 {
>
>                 ranges = <0 0x54000000 0 0x54000000 0 0x01000000>;
>
> +               vi@54080000 {
> +                       compatible = "nvidia,tegra124-vi";
> +                       reg = <0x0 0x54080000 0x0 0x00040000>;
> +                       interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&tegra_car TEGRA124_CLK_VI>;
> +                       resets = <&tegra_car 20>;
> +                       reset-names = "vi";
> +
> +                       iommus = <&mc TEGRA_SWGROUP_VI>;
> +
> +                       status = "disabled";
> +               };
> +
> +               isp@54600000 {
> +                       compatible = "nvidia,tegra124-isp";
> +                       reg = <0x0 0x54600000 0x0 0x00040000>;
> +                       interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&tegra_car TEGRA124_CLK_ISP>;
> +                       resets = <&tegra_car TEGRA124_CLK_ISP>;
> +                       reset-names = "isp";
> +
> +                       iommus = <&mc TEGRA_SWGROUP_ISP2>;
> +
> +                       status = "disabled";
> +               };
> +
> +               isp@54680000 {
> +                       compatible = "nvidia,tegra124-isp";
> +                       reg = <0x0 0x54680000 0x0 0x00040000>;
> +                       interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&tegra_car TEGRA124_CLK_ISPB>;
> +                       resets = <&tegra_car TEGRA124_CLK_ISPB>;
> +                       reset-names = "ispb";

Thierry, here ispb is typo and should be just isp, obviously. I can
re-upload patchset or you may adjust it when applying. Let me know
what you would prefer.

> +
> +                       iommus = <&mc TEGRA_SWGROUP_ISP2B>;
> +
> +                       status = "disabled";
> +               };
> +
>                 dc@54200000 {
>                         compatible = "nvidia,tegra124-dc";
>                         reg = <0x0 0x54200000 0x0 0x00040000>;
> @@ -209,6 +248,32 @@ dsib: dsi@54400000 {
>                         #size-cells = <0>;
>                 };
>
> +               msenc@544c0000 {
> +                       compatible = "nvidia,tegra124-msenc";
> +                       reg = <0x0 0x544c0000 0x0 0x00040000>;
> +                       interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&tegra_car TEGRA124_CLK_MSENC>;
> +                       resets = <&tegra_car TEGRA124_CLK_MSENC>;
> +                       reset-names = "msenc";
> +
> +                       iommus = <&mc TEGRA_SWGROUP_MSENC>;
> +
> +                       status = "disabled";
> +               };
> +
> +               tsec@54500000 {
> +                       compatible = "nvidia,tegra124-tsec";
> +                       reg = <0x0 0x54500000 0x0 0x00040000>;
> +                       interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&tegra_car TEGRA124_CLK_TSEC>;
> +                       resets = <&tegra_car TEGRA124_CLK_TSEC>;
> +                       reset-names = "tsec";
> +
> +                       iommus = <&mc TEGRA_SWGROUP_TSEC>;
> +
> +                       status = "disabled";
> +               };
> +
>                 sor@54540000 {
>                         compatible = "nvidia,tegra124-sor";
>                         reg = <0x0 0x54540000 0x0 0x00040000>;
> --
> 2.43.0
>

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