On 3/3/25 15:36, Michal Wilczynski wrote:
> This is a subset of a larger patch series enabling the Imagination BXM-4-64 GPU
> on the LicheePi 4A board, which is powered by the T-HEAD TH1520 SoC. While the
> full series includes power-domain, reset, and firmware changes, this part
> focuses solely on the clock subsystem needed for the GPU and other VO (video
> output) blocks. By merging these clock patches independently, we prepare the
> groundwork for future GPU integration via the `drm/imagination` driver.
>
> The T-HEAD TH1520 SoC features multiple clock controllers. Initially, only the
> AP clock controller was supported upstream. The patches below add support for
> the VO (video output) clock controller, which manages GPU-related gates, HDMI,
> and other multimedia clocks. Additionally, they introduce a mechanism to
> provide no-op operations for the GPU's "mem" clock gate (documented as
> “Reserved” in the hardware manual) and coordinate the GPU CLKGEN reset in the
> clock driver.
>
> Bigger series cover letter:
>
> https://lore.kernel.org/all/20250219140239.1378758-1-m.wilczynski@samsung.com/
This series should be versioned as v6, to maintain continuity with the
bigger patchset it is a subseries of. Please find below a changelog for
the clock sub-series:
v6:
- squashed the "dt-bindings: clock: thead: Add GPU clkgen reset property"
with the "dt-bindings: clock: thead: Add TH1520 VO clock controller". As
a result, also removed the Reviewed-by from Krzysztof, since the new
resets property has been introduced, which is mandatory in the VO
case
v5:
- introduced a new macro CCU_GATE_CLK_OPS, which allows providing custom clk_ops.
In the case of the 'MEM' clock, it provides empty clk_nops. Later, this clock
is provided to the GPU node, thereby avoiding any ABI breakage
- used the CCU_GATE_CLK_OPS macro to implement a workaround for de-asserting
the clkgen reset only after both core and sys clocks are enabled. This
sequence is required to properly initialize the GPU
v4:
- enhanced documentation for new Video Output (VO) clock inputs in device tree
bindings
v3:
- reworked driver to support multiple clock controllers through .compatible
and .data instead of using multiple address spaces in dt-binding. This change
allows to re-use the driver code for multiple clock controllers
v2:
- removed AP_SUBSYS clock refactoring commits (1-6):
- instead of refactoring, I opted to extend the current driver and its
associated device tree node to include support for a second address space.
- resolved all checkpatch issues using --strict, except for the call to
devm_clk_hw_register_gate_parent_data(). The current implementation remains
preferable in this context, and clang-format aligns with this choice
>
> Michal Wilczynski (4):
> dt-bindings: clock: thead: Add TH1520 VO clock controller
> clk: thead: Add clock support for VO subsystem in T-Head TH1520 SoC
> clk: thead: Add support for custom ops in CCU_GATE_CLK_OPS macro
> clk: thead: Add GPU clock gate control with CLKGEN reset support
>
> .../bindings/clock/thead,th1520-clk-ap.yaml | 33 +-
> drivers/clk/thead/clk-th1520-ap.c | 298 ++++++++++++++++--
> .../dt-bindings/clock/thead,th1520-clk-ap.h | 34 ++
> 3 files changed, 334 insertions(+), 31 deletions(-)
>