[PATCH v8 00/15] drm/msm/dpu: Support quad pipe with dual-DSI

Jun Nie posted 15 patches 11 months, 1 week ago
There is a newer version of this series
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c         |  89 +++--
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h         |   8 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c      |  70 ++--
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h |   2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h   |   2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h      |   2 +
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h          |  12 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c        | 404 ++++++++++++++---------
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h        |  12 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c           | 215 ++++++------
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h           |  32 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h        |  10 +-
12 files changed, 516 insertions(+), 342 deletions(-)
[PATCH v8 00/15] drm/msm/dpu: Support quad pipe with dual-DSI
Posted by Jun Nie 11 months, 1 week ago
2 or more SSPPs and dual-DSI interface are need for super wide panel.
And 4 DSC are preferred for power optimal in this case due to width
limitation of SSPP and MDP clock rate constrain. This patch set
extends number of pipes to 4 and revise related mixer blending logic
to support quad pipe. All these changes depends on the virtual plane
feature to split a super wide drm plane horizontally into 2 or more sub
clip. Thus DMA of multiple SSPPs can share the effort of fetching the
whole drm plane.

The first pipe pair co-work with the first mixer pair to cover the left
half of screen and 2nd pair of pipes and mixers are for the right half
of screen. If a plane is only for the right half of screen, only one
or two of pipes in the 2nd pipe pair are valid, and no SSPP or mixer is
assinged for invalid pipe.

For those panel that does not require quad-pipe, only 1 or 2 pipes in
the 1st pipe pair will be used. There is no concept of right half of
screen.

For legacy non virtual plane mode, the first 1 or 2 pipes are used for
the single SSPP and its multi-rect mode.

To test bonded DSI on SM8650, the 5 patches for active-CTL improvement
are needed:
https://gitlab.freedesktop.org/lumag/msm/-/commits/dpu-4k?ref_type=heads

Changes in v8:
- Fix looping pipes of a plane in _dpu_plane_color_fill()
- Improve pipe assignment with deleting pipes loop in stage.
- Define PIPES_PER_PLANE properly when it appears fisrt.
- rename lms_in_pair to lms_in_stage to avoid confusion.
- Add review tags.
- Link to v7: https://lore.kernel.org/r/20250226-sm8650-v6-14-hmd-deckard-mdss-quad-upstream-oldbootwrapper-36-prep-v7-0-8d5f5f426eb2@linaro.org

Changes in v7:
- Improve pipe assignment to avoid point to invalid memory.
- Define STAGES_PER_PLANE as 2 only when quad-pipe is introduced.
- Polish LM number when blending pipes with min() and pull up to caller func.
- Add review tags.
- Link to v6: https://lore.kernel.org/r/20250217-sm8650-v6-14-hmd-deckard-mdss-quad-upstream-oldbootwrapper-36-prep-v6-0-c11402574367@linaro.org

Changes in v6:
- Replace LM number with PP number to calculate PP number per encoder.
- Rebase to Linux v6.14-rc2.
- Add review tags.
- Link to v5: https://lore.kernel.org/r/20250118-sm8650-v6-13-hmd-deckard-mdss-quad-upstream-33-v5-0-9701a16340da@linaro.org

Changes in v5:
- Iterate SSPP flushing within the required mixer pair, instead of all
  active mixers or specific mixer.
- Limit qaud-pipe usage case to SoC with 4 or more DSC engines and 2
  interfaces case.
- Remove valid flag and use width for pipe validation.
- Polish commit messages and code comments.
- Link to v4: https://lore.kernel.org/r/20250116-sm8650-v6-13-hmd-deckard-mdss-quad-upstream-33-v4-0-74749c6eba33@linaro.org

Changes in v4:
- Restrict SSPP flushing to the required mixer, instead of all active mixers.
- Polish commit messages and code comments.
- Rebase to latest msm/drm-next branch.
- Move pipe checking patch to the top of patch set.
- Link to v3: https://lore.kernel.org/dri-devel/20241219-sm8650-v6-13-hmd-deckard-mdss-quad-upstream-32-v3-0-92c7c0a228e3@linaro.org

Changes in v3:
- Split change in trace into a separate patch.
- Rebase to latest msm-next branch.
- Reorder patch sequence to make sure valid flag is set in earlier patch
- Rectify rewrite patch to move logic change into other patch
- Polish commit messages and code comments.
- Link to v2: https://lore.kernel.org/dri-devel/20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-0-76d4f5d413bf@linaro.org

Changes in v2:
- Revise the patch sequence with changing to 2 pipes topology first. Then
  prepare for quad-pipe setup, then enable quad-pipe at last.
- Split DSI patches into other patch set.
- Link to v1: https://lore.kernel.org/all/20240829-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-8-v1-0-bdb05b4b5a2e@linaro.org
    

Signed-off-by: Jun Nie <jun.nie@linaro.org>
---
Jun Nie (15):
      drm/msm/dpu: check every pipe per capability
      drm/msm/dpu: Do not fix number of DSC
      drm/msm/dpu: configure DSC per number in use
      drm/msm/dpu: polish log for resource allocation
      drm/msm/dpu: decide right side per last bit
      drm/msm/dpu: fix mixer number counter on allocation
      drm/msm/dpu: switch RM to use crtc_id rather than enc_id for allocation
      drm/msm/dpu: bind correct pingpong for quad pipe
      drm/msm/dpu: Add pipe as trace argument
      drm/msm/dpu: handle pipes as array
      drm/msm/dpu: split PIPES_PER_STAGE definition per plane and mixer
      drm/msm/dpu: blend pipes per mixer pairs config
      drm/msm/dpu: support SSPP assignment for quad-pipe case
      drm/msm/dpu: support plane splitting in quad-pipe case
      drm/msm/dpu: Enable quad-pipe for DSC and dual-DSI case

 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c         |  89 +++--
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h         |   8 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c      |  70 ++--
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h |   2 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h   |   2 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h      |   2 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h          |  12 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c        | 404 ++++++++++++++---------
 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h        |  12 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c           | 215 ++++++------
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h           |  32 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h        |  10 +-
 12 files changed, 516 insertions(+), 342 deletions(-)
---
base-commit: b44251a8c179381b9f3ed3aa49be04fe1d516903
change-id: 20250217-sm8650-v6-14-hmd-deckard-mdss-quad-upstream-oldbootwrapper-36-prep-e309f9f8336a

Best regards,
-- 
Jun Nie <jun.nie@linaro.org>
Re: [PATCH v8 00/15] drm/msm/dpu: Support quad pipe with dual-DSI
Posted by Pengyu Luo 9 months, 3 weeks ago
On Mon, 03 Mar 2025 23:14:29 +0800 Jun Nie <jun.nie@linaro.org> wrote:
> 2 or more SSPPs and dual-DSI interface are need for super wide panel.
> And 4 DSC are preferred for power optimal in this case due to width
> limitation of SSPP and MDP clock rate constrain. This patch set
> extends number of pipes to 4 and revise related mixer blending logic
> to support quad pipe. All these changes depends on the virtual plane
> feature to split a super wide drm plane horizontally into 2 or more sub
> clip. Thus DMA of multiple SSPPs can share the effort of fetching the
> whole drm plane.
>
> The first pipe pair co-work with the first mixer pair to cover the left
> half of screen and 2nd pair of pipes and mixers are for the right half
> of screen. If a plane is only for the right half of screen, only one
> or two of pipes in the 2nd pipe pair are valid, and no SSPP or mixer is
> assinged for invalid pipe.
>
> For those panel that does not require quad-pipe, only 1 or 2 pipes in
> the 1st pipe pair will be used. There is no concept of right half of
> screen.
>
> For legacy non virtual plane mode, the first 1 or 2 pipes are used for
> the single SSPP and its multi-rect mode.
>
> To test bonded DSI on SM8650, the 5 patches for active-CTL improvement
> are needed:
> https://gitlab.freedesktop.org/lumag/msm/-/commits/dpu-4k?ref_type=heads
>

[...]

> base-commit: b44251a8c179381b9f3ed3aa49be04fe1d516903

Hi, Jun. The display of my sm8650 device requires 4:4:2(lm, dsc, intf)
topology, I want to test this series, these patches can't be applied to
the latest linux-next tree, and I can't find the commit id in linux-next
or msm-next. Where can I fetch the tree?

Best wishes,
Pengyu
Re: [PATCH v8 00/15] drm/msm/dpu: Support quad pipe with dual-DSI
Posted by Jun Nie 9 months, 3 weeks ago
Pengyu Luo <mitltlatltl@gmail.com> 于2025年4月19日周六 02:34写道:
>
> On Mon, 03 Mar 2025 23:14:29 +0800 Jun Nie <jun.nie@linaro.org> wrote:
> > 2 or more SSPPs and dual-DSI interface are need for super wide panel.
> > And 4 DSC are preferred for power optimal in this case due to width
> > limitation of SSPP and MDP clock rate constrain. This patch set
> > extends number of pipes to 4 and revise related mixer blending logic
> > to support quad pipe. All these changes depends on the virtual plane
> > feature to split a super wide drm plane horizontally into 2 or more sub
> > clip. Thus DMA of multiple SSPPs can share the effort of fetching the
> > whole drm plane.
> >
> > The first pipe pair co-work with the first mixer pair to cover the left
> > half of screen and 2nd pair of pipes and mixers are for the right half
> > of screen. If a plane is only for the right half of screen, only one
> > or two of pipes in the 2nd pipe pair are valid, and no SSPP or mixer is
> > assinged for invalid pipe.
> >
> > For those panel that does not require quad-pipe, only 1 or 2 pipes in
> > the 1st pipe pair will be used. There is no concept of right half of
> > screen.
> >
> > For legacy non virtual plane mode, the first 1 or 2 pipes are used for
> > the single SSPP and its multi-rect mode.
> >
> > To test bonded DSI on SM8650, the 5 patches for active-CTL improvement
> > are needed:
> > https://gitlab.freedesktop.org/lumag/msm/-/commits/dpu-4k?ref_type=heads
> >
>
> [...]
>
> > base-commit: b44251a8c179381b9f3ed3aa49be04fe1d516903
>
> Hi, Jun. The display of my sm8650 device requires 4:4:2(lm, dsc, intf)
> topology, I want to test this series, these patches can't be applied to
> the latest linux-next tree, and I can't find the commit id in linux-next
> or msm-next. Where can I fetch the tree?
>
> Best wishes,
> Pengyu

This is staging patch set. Code clean and formatting is still needed.

https://gitlab.com/jun.nie/linux/-/tree/sm8650/v6.15-quadpipe-staging?ref_type=heads

Regards,
Jun
Re: [PATCH v8 00/15] drm/msm/dpu: Support quad pipe with dual-DSI
Posted by Pengyu Luo 9 months, 3 weeks ago
On Wed, Apr 23, 2025 at 10:50 AM Jun Nie <jun.nie@linaro.org> wrote:
> Pengyu Luo <mitltlatltl@gmail.com> 于2025年4月19日周六 02:34写道:
> >
> > On Mon, 03 Mar 2025 23:14:29 +0800 Jun Nie <jun.nie@linaro.org> wrote:
> > > 2 or more SSPPs and dual-DSI interface are need for super wide panel.
> > > And 4 DSC are preferred for power optimal in this case due to width
> > > limitation of SSPP and MDP clock rate constrain. This patch set
> > > extends number of pipes to 4 and revise related mixer blending logic
> > > to support quad pipe. All these changes depends on the virtual plane
> > > feature to split a super wide drm plane horizontally into 2 or more sub
> > > clip. Thus DMA of multiple SSPPs can share the effort of fetching the
> > > whole drm plane.
> > >
> > > The first pipe pair co-work with the first mixer pair to cover the left
> > > half of screen and 2nd pair of pipes and mixers are for the right half
> > > of screen. If a plane is only for the right half of screen, only one
> > > or two of pipes in the 2nd pipe pair are valid, and no SSPP or mixer is
> > > assinged for invalid pipe.
> > >
> > > For those panel that does not require quad-pipe, only 1 or 2 pipes in
> > > the 1st pipe pair will be used. There is no concept of right half of
> > > screen.
> > >
> > > For legacy non virtual plane mode, the first 1 or 2 pipes are used for
> > > the single SSPP and its multi-rect mode.
> > >
> > > To test bonded DSI on SM8650, the 5 patches for active-CTL improvement
> > > are needed:
> > > https://gitlab.freedesktop.org/lumag/msm/-/commits/dpu-4k?ref_type=heads
> > >
> >
> > [...]
> >
> > > base-commit: b44251a8c179381b9f3ed3aa49be04fe1d516903
> >
> > Hi, Jun. The display of my sm8650 device requires 4:4:2(lm, dsc, intf)
> > topology, I want to test this series, these patches can't be applied to
> > the latest linux-next tree, and I can't find the commit id in linux-next
> > or msm-next. Where can I fetch the tree?
> >
> > Best wishes,
> > Pengyu
>
> This is staging patch set. Code clean and formatting is still needed.
>
> https://gitlab.com/jun.nie/linux/-/tree/sm8650/v6.15-quadpipe-staging?ref_type=heads
>

Sory, it seems that this repo is private or internal for linaro, it is
unavailable in my end. Is it possible to set the repo publicly accessible?

BTW, I had tried it with linux-6.14-rc2 as you mentioned in changelog,
my display(PPC100HB1-1 binding with TDDI NT36532E) has the flag
`BL_UPDATE_DELAY_UNTIL_FIRST_FRAME`, if there is no frame, backlight
would refused to turn on. It turns out no frame is sent to display. I
checked encoder in debugfs(/sys/kernel/debug/dri/0/encoder-0/status),
found all frames underrun. Do you have any idea? Thanks in advance.

Best wishes,
Pengyu