riscv: dts: sophgo: sg2042: Add spi devices

[PATCH] riscv: dts: sophgo: sg2042: Add spi devices

Posted by Zixian Zeng 1 year, 1 month ago

Add spi devices for the sg2042 soc.

Signed-off-by: Zixian Zeng <sycamoremoon376@gmail.com>
---
 arch/riscv/boot/dts/sophgo/sg2042.dtsi | 30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
index 0fca16c469cc95aa897b6b57e0a287a687b4d251..d413daa47cf081f23284851db1eeceb3a157e9c0 100644
--- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi
+++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
@@ -800,5 +800,35 @@ flash@0 {
 				compatible = "jedec,spi-nor";
 			};
 		};
+
+		spi0: spi@7040004000 {
+			compatible = "snps,dw-apb-ssi";
+			#address-cells = <0x01>;
+			#size-cells = <0x00>;
+			reg = <0x70 0x40004000 0x00 0x1000>;
+			interrupt-parent = <&intc>;
+			interrupts = <110 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clkgen GATE_CLK_APB_SPI>,
+					<&clkgen GATE_CLK_SYSDMA_AXI>;
+			clock-frequency = <250000000>;
+			resets = <&rstgen RST_SPI0>;
+			num-cs = <0x02>;
+			status = "okay";
+		};
+
+		spi1: spi@7040005000 {
+			compatible = "snps,dw-apb-ssi";
+			#address-cells = <0x01>;
+			#size-cells = <0x00>;
+			reg = <0x70 0x40005000 0x00 0x1000>;
+			interrupt-parent = <&intc>;
+			interrupts = <111 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clkgen GATE_CLK_APB_SPI>,
+					<&clkgen GATE_CLK_SYSDMA_AXI>;
+			clock-frequency = <250000000>;
+			resets = <&rstgen RST_SPI1>;
+			num-cs = <0x02>;
+			status = "okay";
+		};
 	};
 };

---
base-commit: 9ef5d3235d41a6f5230d3ddf5eb994483853b3e8
change-id: 20250228-sfg-spi-e3f2aeca09ab

Best regards,
-- 
Zixian Zeng <sycamoremoon376@gmail.com>

Re: [PATCH] riscv: dts: sophgo: sg2042: Add spi devices

Posted by Yixun Lan 1 year, 1 month ago

Hi Zixian:

On 10:47 Fri 28 Feb     , Zixian Zeng wrote:
> Add spi devices for the sg2042 soc.
> 
> Signed-off-by: Zixian Zeng <sycamoremoon376@gmail.com>
> ---
>  arch/riscv/boot/dts/sophgo/sg2042.dtsi | 30 ++++++++++++++++++++++++++++++
>  1 file changed, 30 insertions(+)
> 
> diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
> index 0fca16c469cc95aa897b6b57e0a287a687b4d251..d413daa47cf081f23284851db1eeceb3a157e9c0 100644
> --- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
> @@ -800,5 +800,35 @@ flash@0 {
>  				compatible = "jedec,spi-nor";
>  			};
>  		};
> +
> +		spi0: spi@7040004000 {
> +			compatible = "snps,dw-apb-ssi";
> +			#address-cells = <0x01>;
> +			#size-cells = <0x00>;
> +			reg = <0x70 0x40004000 0x00 0x1000>;
for consistency, I'd suggest moving 'reg' info above '#address-cells'

> +			interrupt-parent = <&intc>;
> +			interrupts = <110 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&clkgen GATE_CLK_APB_SPI>,
> +					<&clkgen GATE_CLK_SYSDMA_AXI>;
> +			clock-frequency = <250000000>;
ditto, move clock above interrupt

> +			resets = <&rstgen RST_SPI0>;
> +			num-cs = <0x02>;
> +			status = "okay";
in dtsi file, please make status disabled by default, then enable it at board file

> +		};
> +
> +		spi1: spi@7040005000 {
> +			compatible = "snps,dw-apb-ssi";
> +			#address-cells = <0x01>;
> +			#size-cells = <0x00>;
> +			reg = <0x70 0x40005000 0x00 0x1000>;
> +			interrupt-parent = <&intc>;
> +			interrupts = <111 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&clkgen GATE_CLK_APB_SPI>,
> +					<&clkgen GATE_CLK_SYSDMA_AXI>;
> +			clock-frequency = <250000000>;
> +			resets = <&rstgen RST_SPI1>;
> +			num-cs = <0x02>;
> +			status = "okay";
> +		};
>  	};
>  };
> 
> ---
> base-commit: 9ef5d3235d41a6f5230d3ddf5eb994483853b3e8
> change-id: 20250228-sfg-spi-e3f2aeca09ab
> 
> Best regards,
> -- 
> Zixian Zeng <sycamoremoon376@gmail.com>
> 

-- 
Yixun Lan (dlan)
Gentoo Linux Developer
GPG Key ID AABEFD55