The TRANSTAB (Translation table base address) layout is different
depending on the legacy mode configuration.
Currently, the defined values apply to the legacy mode. Let's rename
them so we can add the ones for no-legacy mode.
Signed-off-by: Ariel D'Alessandro <ariel.dalessandro@collabora.com>
---
drivers/gpu/drm/panfrost/panfrost_regs.h | 19 ++++++++++++-------
1 file changed, 12 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/panfrost/panfrost_regs.h b/drivers/gpu/drm/panfrost/panfrost_regs.h
index b5f279a19a08..4e6064d5feaa 100644
--- a/drivers/gpu/drm/panfrost/panfrost_regs.h
+++ b/drivers/gpu/drm/panfrost/panfrost_regs.h
@@ -317,14 +317,19 @@
#define MMU_AS_STRIDE (1 << MMU_AS_SHIFT)
/*
- * Begin LPAE MMU TRANSTAB register values
+ * Begin LPAE MMU TRANSTAB register values (legacy mode)
*/
-#define AS_TRANSTAB_LPAE_ADDR_SPACE_MASK 0xfffffffffffff000
-#define AS_TRANSTAB_LPAE_ADRMODE_IDENTITY 0x2
-#define AS_TRANSTAB_LPAE_ADRMODE_TABLE 0x3
-#define AS_TRANSTAB_LPAE_ADRMODE_MASK 0x3
-#define AS_TRANSTAB_LPAE_READ_INNER BIT(2)
-#define AS_TRANSTAB_LPAE_SHARE_OUTER BIT(4)
+#define AS_TRANSTAB_LEGACY_ADDR_SPACE_MASK 0xfffffffffffff000
+#define AS_TRANSTAB_LEGACY_ADRMODE_IDENTITY 0x2
+#define AS_TRANSTAB_LEGACY_ADRMODE_TABLE 0x3
+#define AS_TRANSTAB_LEGACY_ADRMODE_MASK 0x3
+#define AS_TRANSTAB_LEGACY_READ_INNER BIT(2)
+#define AS_TRANSTAB_LEGACY_SHARE_OUTER BIT(4)
+
+/*
+ * Begin LPAE MMU TRANSTAB register values (no-legacy mode)
+ */
+#define AS_TRANSTAB_LPAE_ADDR_SPACE_MASK 0xfffffffffffffff0
#define AS_STATUS_AS_ACTIVE 0x01
--
2.47.2On Wed, 26 Feb 2025 15:30:41 -0300 Ariel D'Alessandro <ariel.dalessandro@collabora.com> wrote: > The TRANSTAB (Translation table base address) layout is different > depending on the legacy mode configuration. > > Currently, the defined values apply to the legacy mode. Let's rename > them so we can add the ones for no-legacy mode. > > Signed-off-by: Ariel D'Alessandro <ariel.dalessandro@collabora.com> > --- > drivers/gpu/drm/panfrost/panfrost_regs.h | 19 ++++++++++++------- > 1 file changed, 12 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/panfrost/panfrost_regs.h b/drivers/gpu/drm/panfrost/panfrost_regs.h > index b5f279a19a08..4e6064d5feaa 100644 > --- a/drivers/gpu/drm/panfrost/panfrost_regs.h > +++ b/drivers/gpu/drm/panfrost/panfrost_regs.h > @@ -317,14 +317,19 @@ > #define MMU_AS_STRIDE (1 << MMU_AS_SHIFT) > > /* > - * Begin LPAE MMU TRANSTAB register values > + * Begin LPAE MMU TRANSTAB register values (legacy mode) > */ > -#define AS_TRANSTAB_LPAE_ADDR_SPACE_MASK 0xfffffffffffff000 > -#define AS_TRANSTAB_LPAE_ADRMODE_IDENTITY 0x2 > -#define AS_TRANSTAB_LPAE_ADRMODE_TABLE 0x3 > -#define AS_TRANSTAB_LPAE_ADRMODE_MASK 0x3 > -#define AS_TRANSTAB_LPAE_READ_INNER BIT(2) > -#define AS_TRANSTAB_LPAE_SHARE_OUTER BIT(4) > +#define AS_TRANSTAB_LEGACY_ADDR_SPACE_MASK 0xfffffffffffff000 > +#define AS_TRANSTAB_LEGACY_ADRMODE_IDENTITY 0x2 > +#define AS_TRANSTAB_LEGACY_ADRMODE_TABLE 0x3 > +#define AS_TRANSTAB_LEGACY_ADRMODE_MASK 0x3 > +#define AS_TRANSTAB_LEGACY_READ_INNER BIT(2) > +#define AS_TRANSTAB_LEGACY_SHARE_OUTER BIT(4) How about we keep AS_TRANSTAB_LPAE_ here and prefix the new reg values with AS_xxx_AARCH64_ when there's a collision between the two formats. > + > +/* > + * Begin LPAE MMU TRANSTAB register values (no-legacy mode) > + */ > +#define AS_TRANSTAB_LPAE_ADDR_SPACE_MASK 0xfffffffffffffff0 It looks like we're not use AS_TRANSTAB_LPAE_ADDR_SPACE_MASK, so I'm not sure it's worth defining the mask for the AARCH64 format. > > #define AS_STATUS_AS_ACTIVE 0x01 >
Boris, On 2/27/25 5:25 AM, Boris Brezillon wrote: > On Wed, 26 Feb 2025 15:30:41 -0300 > Ariel D'Alessandro <ariel.dalessandro@collabora.com> wrote: [snip] >> diff --git a/drivers/gpu/drm/panfrost/panfrost_regs.h b/drivers/gpu/drm/panfrost/panfrost_regs.h >> index b5f279a19a08..4e6064d5feaa 100644 >> --- a/drivers/gpu/drm/panfrost/panfrost_regs.h >> +++ b/drivers/gpu/drm/panfrost/panfrost_regs.h >> @@ -317,14 +317,19 @@ >> #define MMU_AS_STRIDE (1 << MMU_AS_SHIFT) >> >> /* >> - * Begin LPAE MMU TRANSTAB register values >> + * Begin LPAE MMU TRANSTAB register values (legacy mode) >> */ >> -#define AS_TRANSTAB_LPAE_ADDR_SPACE_MASK 0xfffffffffffff000 >> -#define AS_TRANSTAB_LPAE_ADRMODE_IDENTITY 0x2 >> -#define AS_TRANSTAB_LPAE_ADRMODE_TABLE 0x3 >> -#define AS_TRANSTAB_LPAE_ADRMODE_MASK 0x3 >> -#define AS_TRANSTAB_LPAE_READ_INNER BIT(2) >> -#define AS_TRANSTAB_LPAE_SHARE_OUTER BIT(4) >> +#define AS_TRANSTAB_LEGACY_ADDR_SPACE_MASK 0xfffffffffffff000 >> +#define AS_TRANSTAB_LEGACY_ADRMODE_IDENTITY 0x2 >> +#define AS_TRANSTAB_LEGACY_ADRMODE_TABLE 0x3 >> +#define AS_TRANSTAB_LEGACY_ADRMODE_MASK 0x3 >> +#define AS_TRANSTAB_LEGACY_READ_INNER BIT(2) >> +#define AS_TRANSTAB_LEGACY_SHARE_OUTER BIT(4) > > How about we keep AS_TRANSTAB_LPAE_ here and prefix the new reg values > with AS_xxx_AARCH64_ when there's a collision between the two formats. Agreed. Will use AS_TRANSTAB_AARCH64_4K_ prefix for the new ones. > >> + >> +/* >> + * Begin LPAE MMU TRANSTAB register values (no-legacy mode) >> + */ >> +#define AS_TRANSTAB_LPAE_ADDR_SPACE_MASK 0xfffffffffffffff0 > > It looks like we're not use AS_TRANSTAB_LPAE_ADDR_SPACE_MASK, so I'm > not sure it's worth defining the mask for the AARCH64 format. None of the original AS_TRANSTAB_LPAE_* values are used, but these refer to the LPAE (legacy mode) format. The new mask for the AARCH64 format is required by the follow up patch `[RFC PATCH 3/4] drm/panfrost: Support ARM_64_LPAE_S1 page table`. It probably makes sense to just squash it now that this patch got simplified and the naming will be more clear. I'll send a new patchset version with these changes. Thanks! -- Ariel D'Alessandro Software Engineer Collabora Ltd. Platinum Building, St John's Innovation Park, Cambridge CB4 0DS, UK Registered in England & Wales, no. 5513718
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