Add nodes for devices on the HOST1X bus: VI, EPP, ISP, MSENC and TSEC.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
---
arch/arm/boot/dts/nvidia/tegra114.dtsi | 65 ++++++++++++++++++++++++++
1 file changed, 65 insertions(+)
diff --git a/arch/arm/boot/dts/nvidia/tegra114.dtsi b/arch/arm/boot/dts/nvidia/tegra114.dtsi
index 86f14e2fd29f..4365daee2f3a 100644
--- a/arch/arm/boot/dts/nvidia/tegra114.dtsi
+++ b/arch/arm/boot/dts/nvidia/tegra114.dtsi
@@ -47,6 +47,45 @@ host1x@50000000 {
ranges = <0x54000000 0x54000000 0x01000000>;
+ vi@54080000 {
+ compatible = "nvidia,tegra114-vi";
+ reg = <0x54080000 0x00040000>;
+ interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA114_CLK_VI>;
+ resets = <&tegra_car 20>;
+ reset-names = "vi";
+
+ iommus = <&mc TEGRA_SWGROUP_VI>;
+
+ status = "disabled";
+ };
+
+ epp@540c0000 {
+ compatible = "nvidia,tegra114-epp";
+ reg = <0x540c0000 0x00040000>;
+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA114_CLK_EPP>;
+ resets = <&tegra_car TEGRA114_CLK_EPP>;
+ reset-names = "epp";
+
+ iommus = <&mc TEGRA_SWGROUP_EPP>;
+
+ status = "disabled";
+ };
+
+ isp@54100000 {
+ compatible = "nvidia,tegra114-isp";
+ reg = <0x54100000 0x00040000>;
+ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA114_CLK_ISP>;
+ resets = <&tegra_car TEGRA114_CLK_ISP>;
+ reset-names = "isp";
+
+ iommus = <&mc TEGRA_SWGROUP_ISP>;
+
+ status = "disabled";
+ };
+
gr2d@54140000 {
compatible = "nvidia,tegra114-gr2d";
reg = <0x54140000 0x00040000>;
@@ -149,6 +188,32 @@ dsib: dsi@54400000 {
#address-cells = <1>;
#size-cells = <0>;
};
+
+ msenc@544c0000 {
+ compatible = "nvidia,tegra114-msenc";
+ reg = <0x544c0000 0x00040000>;
+ interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA114_CLK_MSENC>;
+ resets = <&tegra_car TEGRA114_CLK_MSENC>;
+ reset-names = "msenc";
+
+ iommus = <&mc TEGRA_SWGROUP_MSENC>;
+
+ status = "disabled";
+ };
+
+ tsec@54500000 {
+ compatible = "nvidia,tegra114-tsec";
+ reg = <0x54500000 0x00040000>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA114_CLK_TSEC>;
+ resets = <&tegra_car TEGRA114_CLK_TSEC>;
+ reset-names = "tsec";
+
+ iommus = <&mc TEGRA_SWGROUP_TSEC>;
+
+ status = "disabled";
+ };
};
gic: interrupt-controller@50041000 {
--
2.43.0
On Wed, Feb 26, 2025 at 12:56:10PM +0200, Svyatoslav Ryhel wrote: > Add nodes for devices on the HOST1X bus: VI, EPP, ISP, MSENC and TSEC. > > Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> > --- > arch/arm/boot/dts/nvidia/tegra114.dtsi | 65 ++++++++++++++++++++++++++ > 1 file changed, 65 insertions(+) It looks like we're missing device tree bindings for ISP, MSENC and TSEC. I didn't see those posted anywhere. Can you add them? Thanks, Thierry
чт, 6 бер. 2025 р. о 19:42 Thierry Reding <thierry.reding@gmail.com> пише: > > On Wed, Feb 26, 2025 at 12:56:10PM +0200, Svyatoslav Ryhel wrote: > > Add nodes for devices on the HOST1X bus: VI, EPP, ISP, MSENC and TSEC. > > > > Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> > > --- > > arch/arm/boot/dts/nvidia/tegra114.dtsi | 65 ++++++++++++++++++++++++++ > > 1 file changed, 65 insertions(+) > > It looks like we're missing device tree bindings for ISP, MSENC and > TSEC. I didn't see those posted anywhere. Can you add them? > You mean schema? Yes, sure, will do. > Thanks, > Thierry
On Thu, Mar 06, 2025 at 07:46:18PM +0200, Svyatoslav Ryhel wrote: > чт, 6 бер. 2025 р. о 19:42 Thierry Reding <thierry.reding@gmail.com> пише: > > > > On Wed, Feb 26, 2025 at 12:56:10PM +0200, Svyatoslav Ryhel wrote: > > > Add nodes for devices on the HOST1X bus: VI, EPP, ISP, MSENC and TSEC. > > > > > > Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> > > > --- > > > arch/arm/boot/dts/nvidia/tegra114.dtsi | 65 ++++++++++++++++++++++++++ > > > 1 file changed, 65 insertions(+) > > > > It looks like we're missing device tree bindings for ISP, MSENC and > > TSEC. I didn't see those posted anywhere. Can you add them? > > > > You mean schema? Yes, sure, will do. Yes, the schema. Thanks, Thierry
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