.../interrupt-controller/nxp,lpc3220-mic.txt | 58 -------------- .../interrupt-controller/nxp,lpc3220-mic.yaml | 80 +++++++++++++++++++ 2 files changed, 80 insertions(+), 58 deletions(-) delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/nxp,lpc3220-mic.txt create mode 100644 Documentation/devicetree/bindings/interrupt-controller/nxp,lpc3220-mic.yaml
Convert NXP LPC3220-MIC to DT schema.
Signed-off-by: Leonardo Felipe Takao Hirata <leo.fthirata@gmail.com>
---
Changes in v2:
- Fix SoB
- Remove reg description
- List #interrupt-cell items
- Add interrupt restriction per variant
- Remove extra examples
---
.../interrupt-controller/nxp,lpc3220-mic.txt | 58 --------------
.../interrupt-controller/nxp,lpc3220-mic.yaml | 80 +++++++++++++++++++
2 files changed, 80 insertions(+), 58 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/nxp,lpc3220-mic.txt
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/nxp,lpc3220-mic.yaml
diff --git a/Documentation/devicetree/bindings/interrupt-controller/nxp,lpc3220-mic.txt b/Documentation/devicetree/bindings/interrupt-controller/nxp,lpc3220-mic.txt
deleted file mode 100644
index 0bfb3ba55f4c..000000000000
--- a/Documentation/devicetree/bindings/interrupt-controller/nxp,lpc3220-mic.txt
+++ /dev/null
@@ -1,58 +0,0 @@
-* NXP LPC32xx MIC, SIC1 and SIC2 Interrupt Controllers
-
-Required properties:
-- compatible: "nxp,lpc3220-mic" or "nxp,lpc3220-sic".
-- reg: should contain IC registers location and length.
-- interrupt-controller: identifies the node as an interrupt controller.
-- #interrupt-cells: the number of cells to define an interrupt, should be 2.
- The first cell is the IRQ number, the second cell is used to specify
- one of the supported IRQ types:
- IRQ_TYPE_EDGE_RISING = low-to-high edge triggered,
- IRQ_TYPE_EDGE_FALLING = high-to-low edge triggered,
- IRQ_TYPE_LEVEL_HIGH = active high level-sensitive,
- IRQ_TYPE_LEVEL_LOW = active low level-sensitive.
- Reset value is IRQ_TYPE_LEVEL_LOW.
-
-Optional properties:
-- interrupts: empty for MIC interrupt controller, cascaded MIC
- hardware interrupts for SIC1 and SIC2
-
-Examples:
-
- /* LPC32xx MIC, SIC1 and SIC2 interrupt controllers */
- mic: interrupt-controller@40008000 {
- compatible = "nxp,lpc3220-mic";
- reg = <0x40008000 0x4000>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- sic1: interrupt-controller@4000c000 {
- compatible = "nxp,lpc3220-sic";
- reg = <0x4000c000 0x4000>;
- interrupt-controller;
- #interrupt-cells = <2>;
-
- interrupt-parent = <&mic>;
- interrupts = <0 IRQ_TYPE_LEVEL_LOW>,
- <30 IRQ_TYPE_LEVEL_LOW>;
- };
-
- sic2: interrupt-controller@40010000 {
- compatible = "nxp,lpc3220-sic";
- reg = <0x40010000 0x4000>;
- interrupt-controller;
- #interrupt-cells = <2>;
-
- interrupt-parent = <&mic>;
- interrupts = <1 IRQ_TYPE_LEVEL_LOW>,
- <31 IRQ_TYPE_LEVEL_LOW>;
- };
-
- /* ADC */
- adc@40048000 {
- compatible = "nxp,lpc3220-adc";
- reg = <0x40048000 0x1000>;
- interrupt-parent = <&sic1>;
- interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
- };
diff --git a/Documentation/devicetree/bindings/interrupt-controller/nxp,lpc3220-mic.yaml b/Documentation/devicetree/bindings/interrupt-controller/nxp,lpc3220-mic.yaml
new file mode 100644
index 000000000000..489bd329bc4e
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/nxp,lpc3220-mic.yaml
@@ -0,0 +1,80 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/nxp,lpc3220-mic.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP LPC32xx MIC, SIC1 and SIC2 Interrupt Controllers
+
+maintainers:
+ - Vladimir Zapolskiy <vz@mleia.com>
+
+properties:
+ compatible:
+ enum:
+ - nxp,lpc3220-mic
+ - nxp,lpc3220-sic
+
+ reg:
+ maxItems: 1
+
+ interrupt-controller: true
+
+ '#interrupt-cells':
+ const: 2
+
+ interrupts:
+ items:
+ - description:
+ IRQ number.
+ - description: |
+ IRQ type. Can be one of:
+
+ IRQ_TYPE_EDGE_RISING = Low-to-high edge triggered,
+ IRQ_TYPE_EDGE_FALLING = High-to-low edge triggered,
+ IRQ_TYPE_LEVEL_HIGH = Active high level-sensitive,
+ IRQ_TYPE_LEVEL_LOW = Active low level-sensitive.
+
+ Reset value is IRQ_TYPE_LEVEL_LOW.
+
+required:
+ - compatible
+ - reg
+ - interrupt-controller
+ - '#interrupt-cells'
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: nxp,lpc3220-sic
+ then:
+ required:
+ - interrupts
+ else:
+ properties:
+ interrupts: false
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ mic: interrupt-controller@40008000 {
+ compatible = "nxp,lpc3220-mic";
+ reg = <0x40008000 0x4000>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ sic1: interrupt-controller@4000c000 {
+ compatible = "nxp,lpc3220-sic";
+ reg = <0x4000c000 0x4000>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&mic>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>,
+ <30 IRQ_TYPE_LEVEL_LOW>;
+ };
--
2.43.0Hello Leonardo,
thank you so much for working on this.
On 2/26/25 03:09, Leonardo Felipe Takao Hirata wrote:
> Convert NXP LPC3220-MIC to DT schema.
>
> Signed-off-by: Leonardo Felipe Takao Hirata <leo.fthirata@gmail.com>
> ---
> Changes in v2:
> - Fix SoB
> - Remove reg description
> - List #interrupt-cell items
> - Add interrupt restriction per variant
> - Remove extra examples
> ---
> .../interrupt-controller/nxp,lpc3220-mic.txt | 58 --------------
> .../interrupt-controller/nxp,lpc3220-mic.yaml | 80 +++++++++++++++++++
> 2 files changed, 80 insertions(+), 58 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/nxp,lpc3220-mic.txt
> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/nxp,lpc3220-mic.yaml
>
<snip>
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/nxp,lpc3220-mic.yaml b/Documentation/devicetree/bindings/interrupt-controller/nxp,lpc3220-mic.yaml
> new file mode 100644
> index 000000000000..489bd329bc4e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interrupt-controller/nxp,lpc3220-mic.yaml
> @@ -0,0 +1,80 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/interrupt-controller/nxp,lpc3220-mic.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: NXP LPC32xx MIC, SIC1 and SIC2 Interrupt Controllers
> +
> +maintainers:
> + - Vladimir Zapolskiy <vz@mleia.com>
> +
> +properties:
> + compatible:
> + enum:
> + - nxp,lpc3220-mic
> + - nxp,lpc3220-sic
> +
> + reg:
> + maxItems: 1
> +
> + interrupt-controller: true
> +
> + '#interrupt-cells':
> + const: 2
> +
> + interrupts:
> + items:
> + - description:
> + IRQ number.
For sake of better understanding SIC1 and SIC2 interrupt controllers
are chained to MIC, that's why there is 'interrupts' property present,
and here 0/1 interrupt values are for regular IRQ, 30/31 are for fast IRQ.
Also please add here
minItems: 2
maxItems: 2
I believe that the 'interrupts' property can be just left without any
given description, or just give a simple description like
IRQ and FIQ outputs of sub interrupt controllers to the main interrupt controller
> + - description: |
> + IRQ type. Can be one of:
> +
> + IRQ_TYPE_EDGE_RISING = Low-to-high edge triggered,
> + IRQ_TYPE_EDGE_FALLING = High-to-low edge triggered,
> + IRQ_TYPE_LEVEL_HIGH = Active high level-sensitive,
> + IRQ_TYPE_LEVEL_LOW = Active low level-sensitive.
> +
> + Reset value is IRQ_TYPE_LEVEL_LOW.
> +
> +required:
> + - compatible
> + - reg
> + - interrupt-controller
> + - '#interrupt-cells'
> +
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: nxp,lpc3220-sic
> + then:
> + required:
> + - interrupts
> + else:
> + properties:
> + interrupts: false
Please check if this 'else' condition can be removed.
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/irq.h>
> +
> + mic: interrupt-controller@40008000 {
> + compatible = "nxp,lpc3220-mic";
> + reg = <0x40008000 0x4000>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + sic1: interrupt-controller@4000c000 {
> + compatible = "nxp,lpc3220-sic";
> + reg = <0x4000c000 0x4000>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupt-parent = <&mic>;
> + interrupts = <0 IRQ_TYPE_LEVEL_LOW>,
> + <30 IRQ_TYPE_LEVEL_LOW>;
> + };
--
Best wishes,
Vladimir
On 26/02/2025 10:41, Vladimir Zapolskiy wrote: >> + >> +properties: >> + compatible: >> + enum: >> + - nxp,lpc3220-mic >> + - nxp,lpc3220-sic >> + >> + reg: >> + maxItems: 1 >> + >> + interrupt-controller: true >> + >> + '#interrupt-cells': >> + const: 2 >> + >> + interrupts: >> + items: >> + - description: >> + IRQ number. > > For sake of better understanding SIC1 and SIC2 interrupt controllers > are chained to MIC, that's why there is 'interrupts' property present, > and here 0/1 interrupt values are for regular IRQ, 30/31 are for fast IRQ. > > Also please add here > > minItems: 2 > maxItems: 2 > > I believe that the 'interrupts' property can be just left without any > given description, or just give a simple description like > > IRQ and FIQ outputs of sub interrupt controllers to the main interrupt controller If they are obvious, e.g. maxItems: 2 would be enough, but I understand that these are distinctive interrupts from dedicated blocks - 1 and 2 - so they should be listed. - description: IRQ/FIO of SIC1 (or whatever name is here better) - description: IRQ/FIO of SIC2 Best regards, Krzysztof
Hello Krzysztof and Vladimir, Thanks a lot for your time. I really appreciate your feedbacks. On 26/02/2025 7:14 AM, Krzysztof Kozlowski wrote: > On 26/02/2025 10:41, Vladimir Zapolskiy wrote: >>> + >>> +properties: >>> + compatible: >>> + enum: >>> + - nxp,lpc3220-mic >>> + - nxp,lpc3220-sic >>> + >>> + reg: >>> + maxItems: 1 >>> + >>> + interrupt-controller: true >>> + >>> + '#interrupt-cells': >>> + const: 2 >>> + >>> + interrupts: >>> + items: >>> + - description: >>> + IRQ number. >> >> For sake of better understanding SIC1 and SIC2 interrupt controllers >> are chained to MIC, that's why there is 'interrupts' property present, >> and here 0/1 interrupt values are for regular IRQ, 30/31 are for fast IRQ. >> >> Also please add here >> >> minItems: 2 >> maxItems: 2 >> >> I believe that the 'interrupts' property can be just left without any >> given description, or just give a simple description like >> >> IRQ and FIQ outputs of sub interrupt controllers to the main interrupt controller > If they are obvious, e.g. maxItems: 2 would be enough, but I understand > that these are distinctive interrupts from dedicated blocks - 1 and 2 - > so they should be listed. > - description: IRQ/FIO of SIC1 (or whatever name is here better) > - description: IRQ/FIO of SIC2 > > Best regards, > Krzysztof If I understood correctly, the first item of interrupts is dedicated to IRQ type and the second to FIQ type. Then, I was thinking about listing them like: - description: Regular interrupt request - description: Fast interrupt request What do you guys think? Best regards, Leonardo Hirata
On Tue, Feb 25, 2025 at 10:09:40PM -0300, Leonardo Felipe Takao Hirata wrote: > +properties: > + compatible: > + enum: > + - nxp,lpc3220-mic > + - nxp,lpc3220-sic > + > + reg: > + maxItems: 1 > + > + interrupt-controller: true > + > + '#interrupt-cells': > + const: 2 > + > + interrupts: > + items: > + - description: > + IRQ number. > + - description: | > + IRQ type. Can be one of: That's not correct. Previously you said you have here two interrupts - SIC1 and SIC2. Now you say you have one intrerrupt "IRQ Number" and second interrupt "IRQ type". This makes little sense - your interrupt is not "IRQ type". Unless it is an interrupt signaling that other interrupt has type? Look at other bindings what are the interrupts. > + > + IRQ_TYPE_EDGE_RISING = Low-to-high edge triggered, > + IRQ_TYPE_EDGE_FALLING = High-to-low edge triggered, > + IRQ_TYPE_LEVEL_HIGH = Active high level-sensitive, > + IRQ_TYPE_LEVEL_LOW = Active low level-sensitive. None of these are relevant here. Best regards, Krzysztof
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