Currently PLL142XX locktime is 270. As per spec, it should be 150. Hence
update PLL142XX controller locktime to 150.

Cc: stable@vger.kernel.org
Signed-off-by: Varada Pavani <v.pavani@samsung.com>
---
 drivers/clk/samsung/clk-pll.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index 2e94bba6c396..023a25af73c4 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -206,6 +206,7 @@ static const struct clk_ops samsung_pll3000_clk_ops = {
  */
 /* Maximum lock time can be 270 * PDIV cycles */
 #define PLL35XX_LOCK_FACTOR	(270)
+#define PLL142XX_LOCK_FACTOR	(150)
 
 #define PLL35XX_MDIV_MASK       (0x3FF)
 #define PLL35XX_PDIV_MASK       (0x3F)
@@ -272,7 +273,11 @@ static int samsung_pll35xx_set_rate(struct clk_hw *hw, unsigned long drate,
 	}
 
 	/* Set PLL lock time. */
-	writel_relaxed(rate->pdiv * PLL35XX_LOCK_FACTOR,
+	if (pll->type == pll_142xx)
+		writel_relaxed(rate->pdiv * PLL142XX_LOCK_FACTOR,
+			pll->lock_reg);
+	else
+		writel_relaxed(rate->pdiv * PLL35XX_LOCK_FACTOR,
 			pll->lock_reg);
 
 	/* Change PLL PMS values */
-- 
2.17.1

On 25/02/2025 14:19, Varada Pavani wrote:
> Currently PLL142XX locktime is 270. As per spec, it should be 150. Hence
> update PLL142XX controller locktime to 150.
> 
> Cc: stable@vger.kernel.org

Fixes commit?

> Signed-off-by: Varada Pavani <v.pavani@samsung.com>
> ---
>  drivers/clk/samsung/clk-pll.c | 7 ++++++-
>  1 file changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
> index 2e94bba6c396..023a25af73c4 100644
> --- a/drivers/clk/samsung/clk-pll.c
> +++ b/drivers/clk/samsung/clk-pll.c
> @@ -206,6 +206,7 @@ static const struct clk_ops samsung_pll3000_clk_ops = {
>   */
>  /* Maximum lock time can be 270 * PDIV cycles */
>  #define PLL35XX_LOCK_FACTOR	(270)
> +#define PLL142XX_LOCK_FACTOR	(150)
>  
>  #define PLL35XX_MDIV_MASK       (0x3FF)
>  #define PLL35XX_PDIV_MASK       (0x3F)
> @@ -272,7 +273,11 @@ static int samsung_pll35xx_set_rate(struct clk_hw *hw, unsigned long drate,
>  	}
>  
>  	/* Set PLL lock time. */
> -	writel_relaxed(rate->pdiv * PLL35XX_LOCK_FACTOR,
> +	if (pll->type == pll_142xx)
> +		writel_relaxed(rate->pdiv * PLL142XX_LOCK_FACTOR,
> +			pll->lock_reg);
> +	else
> +		writel_relaxed(rate->pdiv * PLL35XX_LOCK_FACTOR,
>  			pll->lock_reg);
>  
>  	/* Change PLL PMS values */


Best regards,
Krzysztof

On 01/03/2025 15:14, Krzysztof Kozlowski wrote:
> On 25/02/2025 14:19, Varada Pavani wrote:
>> Currently PLL142XX locktime is 270. As per spec, it should be 150. Hence
>> update PLL142XX controller locktime to 150.
>>
>> Cc: stable@vger.kernel.org
> 
> Fixes commit?

If this is a fix, commit msg should describe the bug. You decided to
drop the fixes tag, but you kept stable, so this makes no sense.

Best regards,
Krzysztof

On 05/03/2025 20:12, Krzysztof Kozlowski wrote:
> On 01/03/2025 15:14, Krzysztof Kozlowski wrote:
>> On 25/02/2025 14:19, Varada Pavani wrote:
>>> Currently PLL142XX locktime is 270. As per spec, it should be 150. Hence
>>> update PLL142XX controller locktime to 150.
>>>
>>> Cc: stable@vger.kernel.org
>>
>> Fixes commit?
> 
> If this is a fix, commit msg should describe the bug. You decided to
> drop the fixes tag, but you kept stable, so this makes no sense.
> 
Also in the future: run checkpatch.

CHECK: Alignment should match open parenthesis

Best regards,
Krzysztof

On Tue, 25 Feb 2025 18:49:18 +0530, Varada Pavani wrote:
> Currently PLL142XX locktime is 270. As per spec, it should be 150. Hence
> update PLL142XX controller locktime to 150.
> 
> 

Applied, thanks!

[2/2] clk: samsung: update PLL locktime for PLL142XX used on FSD platform
      https://git.kernel.org/krzk/linux/c/53517a70873c7a91675f7244768aad5006cc45de

Best regards,
-- 
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>