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[PATCH] RISC-V: vDSO: Wire up getrandom() vDSO implementation

Xi Ruoyao posted 1 patch 11 months, 2 weeks ago
There is a newer version of this series
arch/riscv/Kconfig                            |   1 +
arch/riscv/include/asm/vdso/getrandom.h       |  30 +++
arch/riscv/kernel/vdso/Makefile               |   7 +-
arch/riscv/kernel/vdso/getrandom.c            |  10 +
arch/riscv/kernel/vdso/vdso.lds.S             |   1 +
arch/riscv/kernel/vdso/vgetrandom-chacha.S    | 244 ++++++++++++++++++
.../selftests/vDSO/vgetrandom-chacha.S        |   2 +
7 files changed, 294 insertions(+), 1 deletion(-)
create mode 100644 arch/riscv/include/asm/vdso/getrandom.h
create mode 100644 arch/riscv/kernel/vdso/getrandom.c
create mode 100644 arch/riscv/kernel/vdso/vgetrandom-chacha.S
[PATCH] RISC-V: vDSO: Wire up getrandom() vDSO implementation
Posted by Xi Ruoyao 11 months, 2 weeks ago 
Hook up the generic vDSO implementation to the LoongArch vDSO data page
by providing the required __arch_chacha20_blocks_nostack,
__arch_get_k_vdso_rng_data, and getrandom_syscall implementations. Also
wire up the selftests.

The benchmark result:

	vdso: 25000000 times in 2.560024913 seconds
	libc: 25000000 times in 40.960524767 seconds
	syscall: 25000000 times in 40.380651864 seconds

	vdso: 25000000 x 256 times in 171.830655321 seconds
	libc: 25000000 x 256 times in 2913.107080132 seconds
	syscall: 25000000 x 256 times in 2692.084323377 seconds

Note that it depends on Thomas Weißschuh's vDSO generic data storage
implementation (now in the timers/vdso branch of tip).

Signed-off-by: Xi Ruoyao <xry111@xry111.site>
---
 arch/riscv/Kconfig                            |   1 +
 arch/riscv/include/asm/vdso/getrandom.h       |  30 +++
 arch/riscv/kernel/vdso/Makefile               |   7 +-
 arch/riscv/kernel/vdso/getrandom.c            |  10 +
 arch/riscv/kernel/vdso/vdso.lds.S             |   1 +
 arch/riscv/kernel/vdso/vgetrandom-chacha.S    | 244 ++++++++++++++++++
 .../selftests/vDSO/vgetrandom-chacha.S        |   2 +
 7 files changed, 294 insertions(+), 1 deletion(-)
 create mode 100644 arch/riscv/include/asm/vdso/getrandom.h
 create mode 100644 arch/riscv/kernel/vdso/getrandom.c
 create mode 100644 arch/riscv/kernel/vdso/vgetrandom-chacha.S

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index aa8ea53186c0..6fdd63e15fb4 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -213,6 +213,7 @@ config RISCV
 	select THREAD_INFO_IN_TASK
 	select TRACE_IRQFLAGS_SUPPORT
 	select UACCESS_MEMCPY if !MMU
+	select VDSO_GETRANDOM if HAVE_GENERIC_VDSO
 	select USER_STACKTRACE_SUPPORT
 	select ZONE_DMA32 if 64BIT
 
diff --git a/arch/riscv/include/asm/vdso/getrandom.h b/arch/riscv/include/asm/vdso/getrandom.h
new file mode 100644
index 000000000000..7d5e53e670bb
--- /dev/null
+++ b/arch/riscv/include/asm/vdso/getrandom.h
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2025 Xi Ruoyao <xry111@xry111.site>. All Rights Reserved.
+ */
+#ifndef __ASM_VDSO_GETRANDOM_H
+#define __ASM_VDSO_GETRANDOM_H
+
+#ifndef __ASSEMBLY__
+
+#include <asm/unistd.h>
+
+static __always_inline ssize_t getrandom_syscall(void *_buffer, size_t _len, unsigned int _flags)
+{
+	register long ret asm("a0");
+	register long nr asm("a7") = __NR_getrandom;
+	register void *buffer asm("a0") = _buffer;
+	register size_t len asm("a1") = _len;
+	register unsigned int flags asm("a2") = _flags;
+
+	asm volatile ("ecall\n"
+		      : "+r" (ret)
+		      : "r" (nr), "r" (buffer), "r" (len), "r" (flags)
+		      : "memory");
+
+	return ret;
+}
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* __ASM_VDSO_GETRANDOM_H */
diff --git a/arch/riscv/kernel/vdso/Makefile b/arch/riscv/kernel/vdso/Makefile
index 4a5d131506fc..be068a50f671 100644
--- a/arch/riscv/kernel/vdso/Makefile
+++ b/arch/riscv/kernel/vdso/Makefile
@@ -12,9 +12,10 @@ vdso-syms += getcpu
 vdso-syms += flush_icache
 vdso-syms += hwprobe
 vdso-syms += sys_hwprobe
+vdso-syms += getrandom
 
 # Files to link into the vdso
-obj-vdso = $(patsubst %, %.o, $(vdso-syms)) note.o
+obj-vdso = $(patsubst %, %.o, $(vdso-syms)) note.o vgetrandom-chacha.o
 
 ccflags-y := -fno-stack-protector
 ccflags-y += -DDISABLE_BRANCH_PROFILING
@@ -24,6 +25,10 @@ ifneq ($(c-gettimeofday-y),)
   CFLAGS_vgettimeofday.o += -fPIC -include $(c-gettimeofday-y)
 endif
 
+ifneq ($(c-getrandom-y),)
+  CFLAGS_getrandom.o += -fPIC -include $(c-getrandom-y)
+endif
+
 CFLAGS_hwprobe.o += -fPIC
 
 # Build rules
diff --git a/arch/riscv/kernel/vdso/getrandom.c b/arch/riscv/kernel/vdso/getrandom.c
new file mode 100644
index 000000000000..f21922e8cebd
--- /dev/null
+++ b/arch/riscv/kernel/vdso/getrandom.c
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2025 Xi Ruoyao <xry111@xry111.site>. All Rights Reserved.
+ */
+#include <linux/types.h>
+
+ssize_t __vdso_getrandom(void *buffer, size_t len, unsigned int flags, void *opaque_state, size_t opaque_len)
+{
+	return __cvdso_getrandom(buffer, len, flags, opaque_state, opaque_len);
+}
diff --git a/arch/riscv/kernel/vdso/vdso.lds.S b/arch/riscv/kernel/vdso/vdso.lds.S
index 8e86965a8aae..abc69cda0445 100644
--- a/arch/riscv/kernel/vdso/vdso.lds.S
+++ b/arch/riscv/kernel/vdso/vdso.lds.S
@@ -80,6 +80,7 @@ VERSION
 #ifndef COMPAT_VDSO
 		__vdso_riscv_hwprobe;
 #endif
+		__vdso_getrandom;
 	local: *;
 	};
 }
diff --git a/arch/riscv/kernel/vdso/vgetrandom-chacha.S b/arch/riscv/kernel/vdso/vgetrandom-chacha.S
new file mode 100644
index 000000000000..29ec6525a257
--- /dev/null
+++ b/arch/riscv/kernel/vdso/vgetrandom-chacha.S
@@ -0,0 +1,244 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2025 Xi Ruoyao <xry111@xry111.site>. All Rights Reserved.
+ *
+ * Based on arch/loongarch/vdso/vgetrandom-chacha.S.
+ */
+
+#include <asm/asm.h>
+#include <linux/linkage.h>
+
+.text
+
+.macro	ROTRI	rd rs imm
+	slliw	t0, \rs, 32 - \imm
+	srliw	\rd, \rs, \imm
+	or	\rd, \rd, t0
+.endm
+
+.macro	OP_4REG	op d0 d1 d2 d3 s0 s1 s2 s3
+	\op	\d0, \d0, \s0
+	\op	\d1, \d1, \s1
+	\op	\d2, \d2, \s2
+	\op	\d3, \d3, \s3
+.endm
+
+/*
+ *	a0: output bytes
+ * 	a1: 32-byte key input
+ *	a2: 8-byte counter input/output
+ *	a3: number of 64-byte blocks to write to output
+ */
+SYM_FUNC_START(__arch_chacha20_blocks_nostack)
+
+#define output		a0
+#define key		a1
+#define counter		a2
+#define nblocks		a3
+#define i		a4
+#define state0		s0
+#define state1		s1
+#define state2		s2
+#define state3		s3
+#define state4		s4
+#define state5		s5
+#define state6		s6
+#define state7		s7
+#define state8		s8
+#define state9		s9
+#define state10		s10
+#define state11		s11
+#define state12		a5
+#define state13		a6
+#define state14		a7
+#define state15		t1
+#define cnt		t2
+#define copy0		t3
+#define copy1		t4
+#define copy2		t5
+#define copy3		t6
+
+/* Packs to be used with OP_4REG */
+#define line0		state0, state1, state2, state3
+#define line1		state4, state5, state6, state7
+#define line2		state8, state9, state10, state11
+#define line3		state12, state13, state14, state15
+
+#define line1_perm	state5, state6, state7, state4
+#define line2_perm	state10, state11, state8, state9
+#define line3_perm	state15, state12, state13, state14
+
+#define copy            copy0, copy1, copy2, copy3
+
+#define _16		16, 16, 16, 16
+#define _20		20, 20, 20, 20
+#define _24		24, 24, 24, 24
+#define _25		25, 25, 25, 25
+
+	addi		sp, sp, -12*SZREG
+	REG_S		s0,         (sp)
+	REG_S		s1,    SZREG(sp)
+	REG_S		s2,  2*SZREG(sp)
+	REG_S		s3,  3*SZREG(sp)
+	REG_S		s4,  4*SZREG(sp)
+	REG_S		s5,  5*SZREG(sp)
+	REG_S		s6,  6*SZREG(sp)
+	REG_S		s7,  7*SZREG(sp)
+	REG_S		s8,  8*SZREG(sp)
+	REG_S		s9,  9*SZREG(sp)
+	REG_S		s10, 10*SZREG(sp)
+	REG_S		s11, 11*SZREG(sp)
+
+	ld		cnt, (counter)
+
+	li		copy0, 0x61707865
+	li		copy1, 0x3320646e
+	li		copy2, 0x79622d32
+	li		copy3, 0x6b206574
+
+.Lblock:
+	/* state[0,1,2,3] = "expand 32-byte k" */
+	mv		state0, copy0
+	mv		state1, copy1
+	mv		state2, copy2
+	mv		state3, copy3
+
+	/* state[4,5,..,11] = key */
+	lw		state4,   (key)
+	lw		state5,  4(key)
+	lw		state6,  8(key)
+	lw		state7,  12(key)
+	lw		state8,  16(key)
+	lw		state9,  20(key)
+	lw		state10, 24(key)
+	lw		state11, 28(key)
+
+	/* state[12,13] = counter */
+	mv		state12, cnt
+	srli		state13, cnt, 32
+
+	/* state[14,15] = 0 */
+	mv		state14, zero
+	mv		state15, zero
+
+	li		i, 10
+.Lpermute:
+	/* odd round */
+	OP_4REG	addw	line0, line1
+	OP_4REG	xor	line3, line0
+	OP_4REG	ROTRI	line3, _16
+
+	OP_4REG	addw	line2, line3
+	OP_4REG	xor	line1, line2
+	OP_4REG	ROTRI	line1, _20
+
+	OP_4REG	addw	line0, line1
+	OP_4REG	xor	line3, line0
+	OP_4REG	ROTRI	line3, _24
+
+	OP_4REG	addw	line2, line3
+	OP_4REG	xor	line1, line2
+	OP_4REG	ROTRI	line1, _25
+
+	/* even round */
+	OP_4REG	addw	line0, line1_perm
+	OP_4REG	xor	line3_perm, line0
+	OP_4REG	ROTRI	line3_perm, _16
+
+	OP_4REG	addw	line2_perm, line3_perm
+	OP_4REG	xor	line1_perm, line2_perm
+	OP_4REG	ROTRI	line1_perm, _20
+
+	OP_4REG	addw	line0, line1_perm
+	OP_4REG	xor	line3_perm, line0
+	OP_4REG	ROTRI	line3_perm, _24
+
+	OP_4REG	addw	line2_perm, line3_perm
+	OP_4REG	xor	line1_perm, line2_perm
+	OP_4REG	ROTRI	line1_perm, _25
+
+	addi		i, i, -1
+	bnez		i, .Lpermute
+
+	/* output[0,1,2,3] = copy[0,1,2,3] + state[0,1,2,3] */
+	OP_4REG	addw	line0, copy
+	sw		state0,   (output)
+	sw		state1,  4(output)
+	sw		state2,  8(output)
+	sw		state3, 12(output)
+
+	/* from now on state[0,1,2,3] are scratch registers  */
+
+	/* state[0,1,2,3] = lo(key) */
+	lw		state0,   (key)
+	lw		state1,  4(key)
+	lw		state2,  8(key)
+	lw		state3, 12(key)
+
+	/* output[4,5,6,7] = state[0,1,2,3] + state[4,5,6,7] */
+	OP_4REG	addw	line1, line0
+	sw		state4, 16(output)
+	sw		state5, 20(output)
+	sw		state6, 24(output)
+	sw		state7, 28(output)
+
+	/* state[0,1,2,3] = hi(key) */
+	lw		state0, 16(key)
+	lw		state1, 20(key)
+	lw		state2, 24(key)
+	lw		state3, 28(key)
+
+	/* output[8,9,10,11] = tmp[0,1,2,3] + state[8,9,10,11] */
+	OP_4REG	addw	line2, line0
+	sw		state8,  32(output)
+	sw		state9,  36(output)
+	sw		state10, 40(output)
+	sw		state11, 44(output)
+
+	/* output[12,13,14,15] = state[12,13,14,15] + [cnt_lo, cnt_hi, 0, 0] */
+	addw		state12, state12, cnt
+	srli		state0, cnt, 32
+	addw		state13, state13, state0
+	sw		state12, 48(output)
+	sw		state13, 52(output)
+	sw		state14, 56(output)
+	sw		state15, 60(output)
+
+	/* ++counter */
+	addi		cnt, cnt, 1
+
+	/* output += 64 */
+	addi		output, output, 64
+	/* --nblocks */
+	addi		nblocks, nblocks, -1
+	bnez		nblocks, .Lblock
+
+	/* counter = [cnt_lo, cnt_hi] */
+	sd		cnt, (counter)
+
+	/* Zero out the potentially sensitive regs, in case nothing uses these
+	 * again.  As at now copy[0,1,2,3] just contains "expand 32-byte k" and
+	 * state[0,...,11] are s0-s11 those we'll restore in the epilogue, we
+	 * only need to zero state[12,...,15].
+	 */
+	mv		state12, zero
+	mv		state13, zero
+	mv		state14, zero
+	mv		state15, zero
+
+	REG_L		s0,         (sp)
+	REG_L		s1,    SZREG(sp)
+	REG_L		s2,  2*SZREG(sp)
+	REG_L		s3,  3*SZREG(sp)
+	REG_L		s4,  4*SZREG(sp)
+	REG_L		s5,  5*SZREG(sp)
+	REG_L		s6,  6*SZREG(sp)
+	REG_L		s7,  7*SZREG(sp)
+	REG_L		s8,  8*SZREG(sp)
+	REG_L		s9,  9*SZREG(sp)
+	REG_L		s10, 10*SZREG(sp)
+	REG_L		s11, 11*SZREG(sp)
+	addi		sp, sp, 12*SZREG
+
+	ret
+SYM_FUNC_END(__arch_chacha20_blocks_nostack)
diff --git a/tools/testing/selftests/vDSO/vgetrandom-chacha.S b/tools/testing/selftests/vDSO/vgetrandom-chacha.S
index d6e09af7c0a9..3633f2d37fe8 100644
--- a/tools/testing/selftests/vDSO/vgetrandom-chacha.S
+++ b/tools/testing/selftests/vDSO/vgetrandom-chacha.S
@@ -9,6 +9,8 @@
 #include "../../../../arch/arm64/kernel/vdso/vgetrandom-chacha.S"
 #elif defined(__loongarch__)
 #include "../../../../arch/loongarch/vdso/vgetrandom-chacha.S"
+#elif defined(__riscv)
+#include "../../../../arch/riscv/kernel/vdso/vgetrandom-chacha.S"
 #elif defined(__powerpc__) || defined(__powerpc64__)
 #include "../../../../arch/powerpc/kernel/vdso/vgetrandom-chacha.S"
 #elif defined(__s390x__)
-- 
2.48.1
Re: [PATCH] RISC-V: vDSO: Wire up getrandom() vDSO implementation
Posted by kernel test robot 11 months, 1 week ago 
Hi Xi,

kernel test robot noticed the following build errors:

[auto build test ERROR on crng-random/master]
[also build test ERROR on shuah-kselftest/next shuah-kselftest/fixes linus/master v6.14-rc4 next-20250228]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Xi-Ruoyao/RISC-V-vDSO-Wire-up-getrandom-vDSO-implementation/20250224-203232
base:   https://git.kernel.org/pub/scm/linux/kernel/git/crng/random.git master
patch link:    https://lore.kernel.org/r/20250224122541.65045-1-xry111%40xry111.site
patch subject: [PATCH] RISC-V: vDSO: Wire up getrandom() vDSO implementation
config: riscv-randconfig-r122-20250302 (https://download.01.org/0day-ci/archive/20250302/202503020759.lCd4bDgK-lkp@intel.com/config)
compiler: riscv32-linux-gcc (GCC) 14.2.0
reproduce: (https://download.01.org/0day-ci/archive/20250302/202503020759.lCd4bDgK-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202503020759.lCd4bDgK-lkp@intel.com/

All errors (new ones prefixed by >>):

   arch/riscv/kernel/vdso/getrandom.c:7:9: warning: no previous prototype for '__vdso_getrandom' [-Wmissing-prototypes]
       7 | ssize_t __vdso_getrandom(void *buffer, size_t len, unsigned int flags, void *opaque_state, size_t opaque_len)
         |         ^~~~~~~~~~~~~~~~
   arch/riscv/kernel/vdso/getrandom.c: In function '__vdso_getrandom':
>> arch/riscv/kernel/vdso/getrandom.c:9:16: error: implicit declaration of function '__cvdso_getrandom'; did you mean '__vdso_getrandom'? [-Wimplicit-function-declaration]
       9 |         return __cvdso_getrandom(buffer, len, flags, opaque_state, opaque_len);
         |                ^~~~~~~~~~~~~~~~~
         |                __vdso_getrandom
   arch/riscv/kernel/vdso/vgetrandom-chacha.S: Assembler messages:
>> arch/riscv/kernel/vdso/vgetrandom-chacha.S:92: Error: unrecognized opcode `ld t2,(a2)'
>> arch/riscv/kernel/vdso/vgetrandom-chacha.S:118: Error: improper shift amount (32)
>> arch/riscv/kernel/vdso/vgetrandom-chacha.S:20: Error: unrecognized opcode `addw s0,s0,s4'
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:127:  Info: macro invoked from here
>> arch/riscv/kernel/vdso/vgetrandom-chacha.S:21: Error: unrecognized opcode `addw s1,s1,s5'
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:127:  Info: macro invoked from here
>> arch/riscv/kernel/vdso/vgetrandom-chacha.S:22: Error: unrecognized opcode `addw s2,s2,s6'
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:127:  Info: macro invoked from here
>> arch/riscv/kernel/vdso/vgetrandom-chacha.S:23: Error: unrecognized opcode `addw s3,s3,s7'
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:127:  Info: macro invoked from here
>> arch/riscv/kernel/vdso/vgetrandom-chacha.S:14: Error: unrecognized opcode `slliw t0,a5,32-16'
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:20:  Info: macro invoked from here
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:129:   Info: macro invoked from here
>> arch/riscv/kernel/vdso/vgetrandom-chacha.S:15: Error: unrecognized opcode `srliw a5,a5,16'
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:20:  Info: macro invoked from here
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:129:   Info: macro invoked from here
>> arch/riscv/kernel/vdso/vgetrandom-chacha.S:14: Error: unrecognized opcode `slliw t0,a6,32-16'
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:21:  Info: macro invoked from here
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:129:   Info: macro invoked from here
>> arch/riscv/kernel/vdso/vgetrandom-chacha.S:15: Error: unrecognized opcode `srliw a6,a6,16'
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:21:  Info: macro invoked from here
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:129:   Info: macro invoked from here
>> arch/riscv/kernel/vdso/vgetrandom-chacha.S:14: Error: unrecognized opcode `slliw t0,a7,32-16'
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:22:  Info: macro invoked from here
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:129:   Info: macro invoked from here
>> arch/riscv/kernel/vdso/vgetrandom-chacha.S:15: Error: unrecognized opcode `srliw a7,a7,16'
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:22:  Info: macro invoked from here
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:129:   Info: macro invoked from here
>> arch/riscv/kernel/vdso/vgetrandom-chacha.S:14: Error: unrecognized opcode `slliw t0,t1,32-16'
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:23:  Info: macro invoked from here
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:129:   Info: macro invoked from here
>> arch/riscv/kernel/vdso/vgetrandom-chacha.S:15: Error: unrecognized opcode `srliw t1,t1,16'
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:23:  Info: macro invoked from here
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:129:   Info: macro invoked from here
>> arch/riscv/kernel/vdso/vgetrandom-chacha.S:20: Error: unrecognized opcode `addw s8,s8,a5'
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:131:  Info: macro invoked from here
>> arch/riscv/kernel/vdso/vgetrandom-chacha.S:21: Error: unrecognized opcode `addw s9,s9,a6'
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:131:  Info: macro invoked from here
>> arch/riscv/kernel/vdso/vgetrandom-chacha.S:22: Error: unrecognized opcode `addw s10,s10,a7'
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:131:  Info: macro invoked from here
>> arch/riscv/kernel/vdso/vgetrandom-chacha.S:23: Error: unrecognized opcode `addw s11,s11,t1'
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:131:  Info: macro invoked from here
>> arch/riscv/kernel/vdso/vgetrandom-chacha.S:14: Error: unrecognized opcode `slliw t0,s4,32-20'
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:20:  Info: macro invoked from here
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:133:   Info: macro invoked from here
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:15: Error: unrecognized opcode `srliw s4,s4,20'
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:20:  Info: macro invoked from here
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:133:   Info: macro invoked from here
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:14: Error: unrecognized opcode `slliw t0,s5,32-20'
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:21:  Info: macro invoked from here
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:133:   Info: macro invoked from here
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:15: Error: unrecognized opcode `srliw s5,s5,20'
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:21:  Info: macro invoked from here
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:133:   Info: macro invoked from here
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:14: Error: unrecognized opcode `slliw t0,s6,32-20'
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:22:  Info: macro invoked from here
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:133:   Info: macro invoked from here
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:15: Error: unrecognized opcode `srliw s6,s6,20'
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:22:  Info: macro invoked from here
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:133:   Info: macro invoked from here
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:14: Error: unrecognized opcode `slliw t0,s7,32-20'
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:23:  Info: macro invoked from here
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:133:   Info: macro invoked from here
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:15: Error: unrecognized opcode `srliw s7,s7,20'
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:23:  Info: macro invoked from here
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:133:   Info: macro invoked from here
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:20: Error: unrecognized opcode `addw s0,s0,s4'
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:135:  Info: macro invoked from here
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:21: Error: unrecognized opcode `addw s1,s1,s5'
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:135:  Info: macro invoked from here
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:22: Error: unrecognized opcode `addw s2,s2,s6'
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:135:  Info: macro invoked from here
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:23: Error: unrecognized opcode `addw s3,s3,s7'
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:135:  Info: macro invoked from here
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:14: Error: unrecognized opcode `slliw t0,a5,32-24'
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:20:  Info: macro invoked from here
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:137:   Info: macro invoked from here
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:15: Error: unrecognized opcode `srliw a5,a5,24'
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:20:  Info: macro invoked from here
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:137:   Info: macro invoked from here
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:14: Error: unrecognized opcode `slliw t0,a6,32-24'
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:21:  Info: macro invoked from here
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:137:   Info: macro invoked from here
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:15: Error: unrecognized opcode `srliw a6,a6,24'
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:21:  Info: macro invoked from here
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:137:   Info: macro invoked from here
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:14: Error: unrecognized opcode `slliw t0,a7,32-24'
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:22:  Info: macro invoked from here
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:137:   Info: macro invoked from here
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:15: Error: unrecognized opcode `srliw a7,a7,24'
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:22:  Info: macro invoked from here
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:137:   Info: macro invoked from here
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:14: Error: unrecognized opcode `slliw t0,t1,32-24'
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:23:  Info: macro invoked from here
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:137:   Info: macro invoked from here
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:15: Error: unrecognized opcode `srliw t1,t1,24'
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:23:  Info: macro invoked from here
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:137:   Info: macro invoked from here
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:20: Error: unrecognized opcode `addw s8,s8,a5'
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:139:  Info: macro invoked from here
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:21: Error: unrecognized opcode `addw s9,s9,a6'
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:139:  Info: macro invoked from here
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:22: Error: unrecognized opcode `addw s10,s10,a7'
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:139:  Info: macro invoked from here
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:23: Error: unrecognized opcode `addw s11,s11,t1'
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:139:  Info: macro invoked from here
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:14: Error: unrecognized opcode `slliw t0,s4,32-25'
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:20:  Info: macro invoked from here
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:141:   Info: macro invoked from here
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:15: Error: unrecognized opcode `srliw s4,s4,25'
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:20:  Info: macro invoked from here
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:141:   Info: macro invoked from here
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:14: Error: unrecognized opcode `slliw t0,s5,32-25'
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:21:  Info: macro invoked from here
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:141:   Info: macro invoked from here
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:15: Error: unrecognized opcode `srliw s5,s5,25'
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:21:  Info: macro invoked from here
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:141:   Info: macro invoked from here
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:14: Error: unrecognized opcode `slliw t0,s6,32-25'
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:22:  Info: macro invoked from here
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:141:   Info: macro invoked from here
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:15: Error: unrecognized opcode `srliw s6,s6,25'
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:22:  Info: macro invoked from here
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:141:   Info: macro invoked from here
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:14: Error: unrecognized opcode `slliw t0,s7,32-25'
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:23:  Info: macro invoked from here
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:141:   Info: macro invoked from here
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:15: Error: unrecognized opcode `srliw s7,s7,25'
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:23:  Info: macro invoked from here
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:141:   Info: macro invoked from here
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:20: Error: unrecognized opcode `addw s0,s0,s5'
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:144:  Info: macro invoked from here
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:21: Error: unrecognized opcode `addw s1,s1,s6'
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:144:  Info: macro invoked from here
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:22: Error: unrecognized opcode `addw s2,s2,s7'
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:144:  Info: macro invoked from here
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:23: Error: unrecognized opcode `addw s3,s3,s4'
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:144:  Info: macro invoked from here
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:14: Error: unrecognized opcode `slliw t0,t1,32-16'
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:20:  Info: macro invoked from here
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:146:   Info: macro invoked from here
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:15: Error: unrecognized opcode `srliw t1,t1,16'
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:20:  Info: macro invoked from here


vim +9 arch/riscv/kernel/vdso/getrandom.c

     6	
     7	ssize_t __vdso_getrandom(void *buffer, size_t len, unsigned int flags, void *opaque_state, size_t opaque_len)
     8	{
   > 9		return __cvdso_getrandom(buffer, len, flags, opaque_state, opaque_len);

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
Re: [PATCH] RISC-V: vDSO: Wire up getrandom() vDSO implementation
Posted by kernel test robot 11 months, 1 week ago 
Hi Xi,

kernel test robot noticed the following build errors:

[auto build test ERROR on crng-random/master]
[also build test ERROR on shuah-kselftest/next shuah-kselftest/fixes linus/master v6.14-rc4 next-20250228]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Xi-Ruoyao/RISC-V-vDSO-Wire-up-getrandom-vDSO-implementation/20250224-203232
base:   https://git.kernel.org/pub/scm/linux/kernel/git/crng/random.git master
patch link:    https://lore.kernel.org/r/20250224122541.65045-1-xry111%40xry111.site
patch subject: [PATCH] RISC-V: vDSO: Wire up getrandom() vDSO implementation
config: riscv-randconfig-001-20250302 (https://download.01.org/0day-ci/archive/20250302/202503020317.POudjwvT-lkp@intel.com/config)
compiler: clang version 21.0.0git (https://github.com/llvm/llvm-project 14170b16028c087ca154878f5ed93d3089a965c6)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250302/202503020317.POudjwvT-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202503020317.POudjwvT-lkp@intel.com/

All errors (new ones prefixed by >>):

>> arch/riscv/kernel/vdso/vgetrandom-chacha.S:92:2: error: instruction requires the following: RV64I Base Instruction Set
    ld t2, (a2)
    ^
>> arch/riscv/kernel/vdso/vgetrandom-chacha.S:118:15: error: immediate must be an integer in the range [0, 31]
    srli a6, t2, 32
                 ^
>> <instantiation>:1:1: error: instruction requires the following: RV64I Base Instruction Set
   addw s0, s0, s4
   ^
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:127:2: note: while in macro instantiation
    OP_4REG addw s0, s1, s2, s3, s4, s5, s6, s7
    ^
   <instantiation>:2:2: error: instruction requires the following: RV64I Base Instruction Set
    addw s1, s1, s5
    ^
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:127:2: note: while in macro instantiation
    OP_4REG addw s0, s1, s2, s3, s4, s5, s6, s7
    ^
   <instantiation>:3:2: error: instruction requires the following: RV64I Base Instruction Set
    addw s2, s2, s6
    ^
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:127:2: note: while in macro instantiation
    OP_4REG addw s0, s1, s2, s3, s4, s5, s6, s7
    ^
   <instantiation>:4:2: error: instruction requires the following: RV64I Base Instruction Set
    addw s3, s3, s7
    ^
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:127:2: note: while in macro instantiation
    OP_4REG addw s0, s1, s2, s3, s4, s5, s6, s7
    ^
>> <instantiation>:1:1: error: instruction requires the following: RV64I Base Instruction Set
   slliw t0, a5, 32 - 16
   ^
   <instantiation>:1:1: note: while in macro instantiation
   ROTRI a5, a5, 16
   ^
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:129:2: note: while in macro instantiation
    OP_4REG ROTRI a5, a6, a7, t1, 16, 16, 16, 16
    ^
   <instantiation>:2:2: error: instruction requires the following: RV64I Base Instruction Set
    srliw a5, a5, 16
    ^
   <instantiation>:1:1: note: while in macro instantiation
   ROTRI a5, a5, 16
   ^
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:129:2: note: while in macro instantiation
    OP_4REG ROTRI a5, a6, a7, t1, 16, 16, 16, 16
    ^
>> <instantiation>:1:1: error: instruction requires the following: RV64I Base Instruction Set
   slliw t0, a6, 32 - 16
   ^
   <instantiation>:2:2: note: while in macro instantiation
    ROTRI a6, a6, 16
    ^
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:129:2: note: while in macro instantiation
    OP_4REG ROTRI a5, a6, a7, t1, 16, 16, 16, 16
    ^
   <instantiation>:2:2: error: instruction requires the following: RV64I Base Instruction Set
    srliw a6, a6, 16
    ^
   <instantiation>:2:2: note: while in macro instantiation
    ROTRI a6, a6, 16
    ^
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:129:2: note: while in macro instantiation
    OP_4REG ROTRI a5, a6, a7, t1, 16, 16, 16, 16
    ^
>> <instantiation>:1:1: error: instruction requires the following: RV64I Base Instruction Set
   slliw t0, a7, 32 - 16
   ^
   <instantiation>:3:2: note: while in macro instantiation
    ROTRI a7, a7, 16
    ^
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:129:2: note: while in macro instantiation
    OP_4REG ROTRI a5, a6, a7, t1, 16, 16, 16, 16
    ^
   <instantiation>:2:2: error: instruction requires the following: RV64I Base Instruction Set
    srliw a7, a7, 16
    ^
   <instantiation>:3:2: note: while in macro instantiation
    ROTRI a7, a7, 16
    ^
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:129:2: note: while in macro instantiation
    OP_4REG ROTRI a5, a6, a7, t1, 16, 16, 16, 16
    ^
>> <instantiation>:1:1: error: instruction requires the following: RV64I Base Instruction Set
   slliw t0, t1, 32 - 16
   ^
   <instantiation>:4:2: note: while in macro instantiation
    ROTRI t1, t1, 16
    ^
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:129:2: note: while in macro instantiation
    OP_4REG ROTRI a5, a6, a7, t1, 16, 16, 16, 16
    ^
   <instantiation>:2:2: error: instruction requires the following: RV64I Base Instruction Set
    srliw t1, t1, 16
    ^
   <instantiation>:4:2: note: while in macro instantiation
    ROTRI t1, t1, 16
    ^
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:129:2: note: while in macro instantiation
    OP_4REG ROTRI a5, a6, a7, t1, 16, 16, 16, 16
    ^
>> <instantiation>:1:1: error: instruction requires the following: RV64I Base Instruction Set
   addw s8, s8, a5
   ^
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:131:2: note: while in macro instantiation
    OP_4REG addw s8, s9, s10, s11, a5, a6, a7, t1
    ^
   <instantiation>:2:2: error: instruction requires the following: RV64I Base Instruction Set
    addw s9, s9, a6
    ^
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:131:2: note: while in macro instantiation
    OP_4REG addw s8, s9, s10, s11, a5, a6, a7, t1
    ^
   <instantiation>:3:2: error: instruction requires the following: RV64I Base Instruction Set
    addw s10, s10, a7
    ^
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:131:2: note: while in macro instantiation
    OP_4REG addw s8, s9, s10, s11, a5, a6, a7, t1
    ^
   <instantiation>:4:2: error: instruction requires the following: RV64I Base Instruction Set
    addw s11, s11, t1
    ^
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:131:2: note: while in macro instantiation
    OP_4REG addw s8, s9, s10, s11, a5, a6, a7, t1
    ^
>> <instantiation>:1:1: error: instruction requires the following: RV64I Base Instruction Set
   slliw t0, s4, 32 - 20
   ^
   <instantiation>:1:1: note: while in macro instantiation
   ROTRI s4, s4, 20
   ^
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:133:2: note: while in macro instantiation
    OP_4REG ROTRI s4, s5, s6, s7, 20, 20, 20, 20
    ^
   <instantiation>:2:2: error: instruction requires the following: RV64I Base Instruction Set
    srliw s4, s4, 20
    ^
   <instantiation>:1:1: note: while in macro instantiation
   ROTRI s4, s4, 20
   ^
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:133:2: note: while in macro instantiation
    OP_4REG ROTRI s4, s5, s6, s7, 20, 20, 20, 20
    ^
>> <instantiation>:1:1: error: instruction requires the following: RV64I Base Instruction Set
   slliw t0, s5, 32 - 20
   ^
   <instantiation>:2:2: note: while in macro instantiation
    ROTRI s5, s5, 20
    ^
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:133:2: note: while in macro instantiation
    OP_4REG ROTRI s4, s5, s6, s7, 20, 20, 20, 20
    ^
   <instantiation>:2:2: error: instruction requires the following: RV64I Base Instruction Set
    srliw s5, s5, 20
    ^
   <instantiation>:2:2: note: while in macro instantiation
    ROTRI s5, s5, 20
    ^
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:133:2: note: while in macro instantiation
    OP_4REG ROTRI s4, s5, s6, s7, 20, 20, 20, 20
    ^
>> <instantiation>:1:1: error: instruction requires the following: RV64I Base Instruction Set
   slliw t0, s6, 32 - 20
   ^
   <instantiation>:3:2: note: while in macro instantiation
    ROTRI s6, s6, 20
    ^
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:133:2: note: while in macro instantiation
    OP_4REG ROTRI s4, s5, s6, s7, 20, 20, 20, 20
    ^
   <instantiation>:2:2: error: instruction requires the following: RV64I Base Instruction Set
    srliw s6, s6, 20
    ^
   <instantiation>:3:2: note: while in macro instantiation
    ROTRI s6, s6, 20
    ^
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:133:2: note: while in macro instantiation
    OP_4REG ROTRI s4, s5, s6, s7, 20, 20, 20, 20
    ^
>> <instantiation>:1:1: error: instruction requires the following: RV64I Base Instruction Set
   slliw t0, s7, 32 - 20
   ^
   <instantiation>:4:2: note: while in macro instantiation
    ROTRI s7, s7, 20
    ^
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:133:2: note: while in macro instantiation
    OP_4REG ROTRI s4, s5, s6, s7, 20, 20, 20, 20
    ^
   <instantiation>:2:2: error: instruction requires the following: RV64I Base Instruction Set
    srliw s7, s7, 20
    ^
   <instantiation>:4:2: note: while in macro instantiation
    ROTRI s7, s7, 20
    ^
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:133:2: note: while in macro instantiation
    OP_4REG ROTRI s4, s5, s6, s7, 20, 20, 20, 20
    ^
>> <instantiation>:1:1: error: instruction requires the following: RV64I Base Instruction Set
   addw s0, s0, s4
   ^
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:135:2: note: while in macro instantiation
    OP_4REG addw s0, s1, s2, s3, s4, s5, s6, s7
    ^
   <instantiation>:2:2: error: instruction requires the following: RV64I Base Instruction Set
    addw s1, s1, s5
    ^
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:135:2: note: while in macro instantiation
    OP_4REG addw s0, s1, s2, s3, s4, s5, s6, s7
    ^
   <instantiation>:3:2: error: instruction requires the following: RV64I Base Instruction Set
    addw s2, s2, s6
    ^
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:135:2: note: while in macro instantiation
    OP_4REG addw s0, s1, s2, s3, s4, s5, s6, s7
    ^
   <instantiation>:4:2: error: instruction requires the following: RV64I Base Instruction Set
    addw s3, s3, s7
    ^
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:135:2: note: while in macro instantiation
    OP_4REG addw s0, s1, s2, s3, s4, s5, s6, s7
    ^
>> <instantiation>:1:1: error: instruction requires the following: RV64I Base Instruction Set
   slliw t0, a5, 32 - 24
   ^
   <instantiation>:1:1: note: while in macro instantiation
   ROTRI a5, a5, 24
   ^
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:137:2: note: while in macro instantiation
    OP_4REG ROTRI a5, a6, a7, t1, 24, 24, 24, 24
    ^
   <instantiation>:2:2: error: instruction requires the following: RV64I Base Instruction Set
    srliw a5, a5, 24
    ^
   <instantiation>:1:1: note: while in macro instantiation
   ROTRI a5, a5, 24
   ^
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:137:2: note: while in macro instantiation
    OP_4REG ROTRI a5, a6, a7, t1, 24, 24, 24, 24
    ^
>> <instantiation>:1:1: error: instruction requires the following: RV64I Base Instruction Set
   slliw t0, a6, 32 - 24
   ^
   <instantiation>:2:2: note: while in macro instantiation
    ROTRI a6, a6, 24
    ^
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:137:2: note: while in macro instantiation
    OP_4REG ROTRI a5, a6, a7, t1, 24, 24, 24, 24
    ^
   <instantiation>:2:2: error: instruction requires the following: RV64I Base Instruction Set
    srliw a6, a6, 24
    ^
   <instantiation>:2:2: note: while in macro instantiation
    ROTRI a6, a6, 24
    ^
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:137:2: note: while in macro instantiation
    OP_4REG ROTRI a5, a6, a7, t1, 24, 24, 24, 24
    ^
>> <instantiation>:1:1: error: instruction requires the following: RV64I Base Instruction Set
   slliw t0, a7, 32 - 24
   ^
   <instantiation>:3:2: note: while in macro instantiation
    ROTRI a7, a7, 24
    ^
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:137:2: note: while in macro instantiation
    OP_4REG ROTRI a5, a6, a7, t1, 24, 24, 24, 24
    ^
   <instantiation>:2:2: error: instruction requires the following: RV64I Base Instruction Set
    srliw a7, a7, 24
    ^
   <instantiation>:3:2: note: while in macro instantiation
    ROTRI a7, a7, 24
    ^
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:137:2: note: while in macro instantiation
    OP_4REG ROTRI a5, a6, a7, t1, 24, 24, 24, 24
    ^
>> <instantiation>:1:1: error: instruction requires the following: RV64I Base Instruction Set
   slliw t0, t1, 32 - 24
   ^
   <instantiation>:4:2: note: while in macro instantiation
    ROTRI t1, t1, 24
    ^
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:137:2: note: while in macro instantiation
    OP_4REG ROTRI a5, a6, a7, t1, 24, 24, 24, 24
    ^
   <instantiation>:2:2: error: instruction requires the following: RV64I Base Instruction Set
    srliw t1, t1, 24
    ^
   <instantiation>:4:2: note: while in macro instantiation
    ROTRI t1, t1, 24
    ^
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:137:2: note: while in macro instantiation
    OP_4REG ROTRI a5, a6, a7, t1, 24, 24, 24, 24
    ^
>> <instantiation>:1:1: error: instruction requires the following: RV64I Base Instruction Set
   addw s8, s8, a5
   ^
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:139:2: note: while in macro instantiation
    OP_4REG addw s8, s9, s10, s11, a5, a6, a7, t1
    ^
   <instantiation>:2:2: error: instruction requires the following: RV64I Base Instruction Set
    addw s9, s9, a6
    ^
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:139:2: note: while in macro instantiation
    OP_4REG addw s8, s9, s10, s11, a5, a6, a7, t1
    ^
   <instantiation>:3:2: error: instruction requires the following: RV64I Base Instruction Set
    addw s10, s10, a7
    ^
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:139:2: note: while in macro instantiation
    OP_4REG addw s8, s9, s10, s11, a5, a6, a7, t1
    ^
   <instantiation>:4:2: error: instruction requires the following: RV64I Base Instruction Set
    addw s11, s11, t1
    ^
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:139:2: note: while in macro instantiation
    OP_4REG addw s8, s9, s10, s11, a5, a6, a7, t1
    ^
>> <instantiation>:1:1: error: instruction requires the following: RV64I Base Instruction Set
   slliw t0, s4, 32 - 25
   ^
   <instantiation>:1:1: note: while in macro instantiation
   ROTRI s4, s4, 25
   ^
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:141:2: note: while in macro instantiation
    OP_4REG ROTRI s4, s5, s6, s7, 25, 25, 25, 25
    ^
   <instantiation>:2:2: error: instruction requires the following: RV64I Base Instruction Set
    srliw s4, s4, 25
    ^
   <instantiation>:1:1: note: while in macro instantiation
   ROTRI s4, s4, 25
   ^
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:141:2: note: while in macro instantiation
    OP_4REG ROTRI s4, s5, s6, s7, 25, 25, 25, 25
    ^
>> <instantiation>:1:1: error: instruction requires the following: RV64I Base Instruction Set
   slliw t0, s5, 32 - 25
   ^
   <instantiation>:2:2: note: while in macro instantiation
    ROTRI s5, s5, 25
    ^
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:141:2: note: while in macro instantiation
    OP_4REG ROTRI s4, s5, s6, s7, 25, 25, 25, 25
    ^
   <instantiation>:2:2: error: instruction requires the following: RV64I Base Instruction Set
    srliw s5, s5, 25
    ^
   <instantiation>:2:2: note: while in macro instantiation
    ROTRI s5, s5, 25
    ^
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:141:2: note: while in macro instantiation
    OP_4REG ROTRI s4, s5, s6, s7, 25, 25, 25, 25
    ^
   <instantiation>:1:1: error: instruction requires the following: RV64I Base Instruction Set
   slliw t0, s6, 32 - 25
   ^
   <instantiation>:3:2: note: while in macro instantiation
    ROTRI s6, s6, 25
    ^
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:141:2: note: while in macro instantiation
    OP_4REG ROTRI s4, s5, s6, s7, 25, 25, 25, 25
    ^
   <instantiation>:2:2: error: instruction requires the following: RV64I Base Instruction Set
    srliw s6, s6, 25
    ^
   <instantiation>:3:2: note: while in macro instantiation
    ROTRI s6, s6, 25
    ^
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:141:2: note: while in macro instantiation
    OP_4REG ROTRI s4, s5, s6, s7, 25, 25, 25, 25
    ^
   <instantiation>:1:1: error: instruction requires the following: RV64I Base Instruction Set
   slliw t0, s7, 32 - 25
   ^
   <instantiation>:4:2: note: while in macro instantiation
    ROTRI s7, s7, 25
    ^
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:141:2: note: while in macro instantiation
    OP_4REG ROTRI s4, s5, s6, s7, 25, 25, 25, 25
    ^
   <instantiation>:2:2: error: instruction requires the following: RV64I Base Instruction Set
    srliw s7, s7, 25
    ^
   <instantiation>:4:2: note: while in macro instantiation
    ROTRI s7, s7, 25
    ^
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:141:2: note: while in macro instantiation
    OP_4REG ROTRI s4, s5, s6, s7, 25, 25, 25, 25
    ^
   <instantiation>:1:1: error: instruction requires the following: RV64I Base Instruction Set
   addw s0, s0, s5
   ^
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:144:2: note: while in macro instantiation
    OP_4REG addw s0, s1, s2, s3, s5, s6, s7, s4
    ^
   <instantiation>:2:2: error: instruction requires the following: RV64I Base Instruction Set
    addw s1, s1, s6
    ^
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:144:2: note: while in macro instantiation
    OP_4REG addw s0, s1, s2, s3, s5, s6, s7, s4
    ^
   <instantiation>:3:2: error: instruction requires the following: RV64I Base Instruction Set
    addw s2, s2, s7
    ^
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:144:2: note: while in macro instantiation
    OP_4REG addw s0, s1, s2, s3, s5, s6, s7, s4
    ^
   <instantiation>:4:2: error: instruction requires the following: RV64I Base Instruction Set
    addw s3, s3, s4
    ^
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:144:2: note: while in macro instantiation
    OP_4REG addw s0, s1, s2, s3, s5, s6, s7, s4
    ^
   <instantiation>:1:1: error: instruction requires the following: RV64I Base Instruction Set
   slliw t0, t1, 32 - 16
   ^
   <instantiation>:1:1: note: while in macro instantiation
   ROTRI t1, t1, 16
   ^
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:146:2: note: while in macro instantiation
    OP_4REG ROTRI t1, a5, a6, a7, 16, 16, 16, 16
    ^
   <instantiation>:2:2: error: instruction requires the following: RV64I Base Instruction Set
    srliw t1, t1, 16
    ^
   <instantiation>:1:1: note: while in macro instantiation
   ROTRI t1, t1, 16
   ^
   arch/riscv/kernel/vdso/vgetrandom-chacha.S:146:2: note: while in macro instantiation
    OP_4REG ROTRI t1, a5, a6, a7, 16, 16, 16, 16
    ^
   <instantiation>:1:1: error: instruction requires the following: RV64I Base Instruction Set
   slliw t0, a5, 32 - 16
   ^
   <instantiation>:2:2: note: while in macro instantiation
    ROTRI a5, a5, 16


vim +92 arch/riscv/kernel/vdso/vgetrandom-chacha.S

    77	
    78		addi		sp, sp, -12*SZREG
    79		REG_S		s0,         (sp)
    80		REG_S		s1,    SZREG(sp)
    81		REG_S		s2,  2*SZREG(sp)
    82		REG_S		s3,  3*SZREG(sp)
    83		REG_S		s4,  4*SZREG(sp)
    84		REG_S		s5,  5*SZREG(sp)
    85		REG_S		s6,  6*SZREG(sp)
    86		REG_S		s7,  7*SZREG(sp)
    87		REG_S		s8,  8*SZREG(sp)
    88		REG_S		s9,  9*SZREG(sp)
    89		REG_S		s10, 10*SZREG(sp)
    90		REG_S		s11, 11*SZREG(sp)
    91	
  > 92		ld		cnt, (counter)
    93	
    94		li		copy0, 0x61707865
    95		li		copy1, 0x3320646e
    96		li		copy2, 0x79622d32
    97		li		copy3, 0x6b206574
    98	
    99	.Lblock:
   100		/* state[0,1,2,3] = "expand 32-byte k" */
   101		mv		state0, copy0
   102		mv		state1, copy1
   103		mv		state2, copy2
   104		mv		state3, copy3
   105	
   106		/* state[4,5,..,11] = key */
   107		lw		state4,   (key)
   108		lw		state5,  4(key)
   109		lw		state6,  8(key)
   110		lw		state7,  12(key)
   111		lw		state8,  16(key)
   112		lw		state9,  20(key)
   113		lw		state10, 24(key)
   114		lw		state11, 28(key)
   115	
   116		/* state[12,13] = counter */
   117		mv		state12, cnt
 > 118		srli		state13, cnt, 32

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
Re: [PATCH] RISC-V: vDSO: Wire up getrandom() vDSO implementation
Posted by Jason A. Donenfeld 11 months, 2 weeks ago 
On Mon, Feb 24, 2025 at 1:26 PM Xi Ruoyao <xry111@xry111.site> wrote:
>
> Hook up the generic vDSO implementation to the LoongArch vDSO data page
> by providing the required __arch_chacha20_blocks_nostack,
> __arch_get_k_vdso_rng_data, and getrandom_syscall implementations. Also
> wire up the selftests.

Thomas noted the LoongArch copypasta, but also, there's no
__arch_get_k_vdso_rng_data implementation here, like the message says,
presumably because of the generic data storage work.
Re: [PATCH] RISC-V: vDSO: Wire up getrandom() vDSO implementation
Posted by Thomas Weißschuh 11 months, 2 weeks ago 
Hi!

On Mon, Feb 24, 2025 at 08:25:41PM +0800, Xi Ruoyao wrote:
> Hook up the generic vDSO implementation to the LoongArch vDSO data page

LoongArch?

"to the generic vDSO getrandom implementation"

> by providing the required __arch_chacha20_blocks_nostack,
> __arch_get_k_vdso_rng_data, and getrandom_syscall implementations. Also
> wire up the selftests.
> 
> The benchmark result:
> 
> 	vdso: 25000000 times in 2.560024913 seconds
> 	libc: 25000000 times in 40.960524767 seconds
> 	syscall: 25000000 times in 40.380651864 seconds
> 
> 	vdso: 25000000 x 256 times in 171.830655321 seconds
> 	libc: 25000000 x 256 times in 2913.107080132 seconds
> 	syscall: 25000000 x 256 times in 2692.084323377 seconds
> 
> Note that it depends on Thomas Weißschuh's vDSO generic data storage
> implementation (now in the timers/vdso branch of tip).

The note should be below a "---" line, so it doesn't end up in the commit.

> Signed-off-by: Xi Ruoyao <xry111@xry111.site>
> ---
>  arch/riscv/Kconfig                            |   1 +
>  arch/riscv/include/asm/vdso/getrandom.h       |  30 +++
>  arch/riscv/kernel/vdso/Makefile               |   7 +-
>  arch/riscv/kernel/vdso/getrandom.c            |  10 +
>  arch/riscv/kernel/vdso/vdso.lds.S             |   1 +
>  arch/riscv/kernel/vdso/vgetrandom-chacha.S    | 244 ++++++++++++++++++
>  .../selftests/vDSO/vgetrandom-chacha.S        |   2 +
>  7 files changed, 294 insertions(+), 1 deletion(-)
>  create mode 100644 arch/riscv/include/asm/vdso/getrandom.h
>  create mode 100644 arch/riscv/kernel/vdso/getrandom.c
>  create mode 100644 arch/riscv/kernel/vdso/vgetrandom-chacha.S
> 
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index aa8ea53186c0..6fdd63e15fb4 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -213,6 +213,7 @@ config RISCV
>  	select THREAD_INFO_IN_TASK
>  	select TRACE_IRQFLAGS_SUPPORT
>  	select UACCESS_MEMCPY if !MMU
> +	select VDSO_GETRANDOM if HAVE_GENERIC_VDSO

Broken alphabetical ordering.

>  	select USER_STACKTRACE_SUPPORT
>  	select ZONE_DMA32 if 64BIT

<snip>
Re: [PATCH] RISC-V: vDSO: Wire up getrandom() vDSO implementation
Posted by Xi Ruoyao 11 months, 2 weeks ago 
On Mon, 2025-02-24 at 15:07 +0100, Thomas Weißschuh wrote:
> Hi!
> 
> On Mon, Feb 24, 2025 at 08:25:41PM +0800, Xi Ruoyao wrote:
> > Hook up the generic vDSO implementation to the LoongArch vDSO data
> > page
> 
> LoongArch?

Oops, pasto by "reusing" my own words in LoongArch commit :(.

> "to the generic vDSO getrandom implementation"
> 
> > by providing the required __arch_chacha20_blocks_nostack,
> > __arch_get_k_vdso_rng_data, and getrandom_syscall implementations.
> > Also
> > wire up the selftests.
> > 
> > The benchmark result:
> > 
> > 	vdso: 25000000 times in 2.560024913 seconds
> > 	libc: 25000000 times in 40.960524767 seconds
> > 	syscall: 25000000 times in 40.380651864 seconds
> > 
> > 	vdso: 25000000 x 256 times in 171.830655321 seconds
> > 	libc: 25000000 x 256 times in 2913.107080132 seconds
> > 	syscall: 25000000 x 256 times in 2692.084323377 seconds
> > 
> > Note that it depends on Thomas Weißschuh's vDSO generic data storage
> > implementation (now in the timers/vdso branch of tip).
> 
> The note should be below a "---" line, so it doesn't end up in the
> commit.

> 
> > Signed-off-by: Xi Ruoyao <xry111@xry111.site>
> > ---
> >  arch/riscv/Kconfig                            |   1 +
> >  arch/riscv/include/asm/vdso/getrandom.h       |  30 +++
> >  arch/riscv/kernel/vdso/Makefile               |   7 +-
> >  arch/riscv/kernel/vdso/getrandom.c            |  10 +
> >  arch/riscv/kernel/vdso/vdso.lds.S             |   1 +
> >  arch/riscv/kernel/vdso/vgetrandom-chacha.S    | 244
> > ++++++++++++++++++
> >  .../selftests/vDSO/vgetrandom-chacha.S        |   2 +
> >  7 files changed, 294 insertions(+), 1 deletion(-)
> >  create mode 100644 arch/riscv/include/asm/vdso/getrandom.h
> >  create mode 100644 arch/riscv/kernel/vdso/getrandom.c
> >  create mode 100644 arch/riscv/kernel/vdso/vgetrandom-chacha.S
> > 
> > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> > index aa8ea53186c0..6fdd63e15fb4 100644
> > --- a/arch/riscv/Kconfig
> > +++ b/arch/riscv/Kconfig
> > @@ -213,6 +213,7 @@ config RISCV
> >  	select THREAD_INFO_IN_TASK
> >  	select TRACE_IRQFLAGS_SUPPORT
> >  	select UACCESS_MEMCPY if !MMU
> > +	select VDSO_GETRANDOM if HAVE_GENERIC_VDSO
> 
> Broken alphabetical ordering.

I'm still investigating some CI failures (at lease some of them seem not
just caused by missing the generic data storage implementation).  I'll
fix them and the errors you found in V2.

-- 
Xi Ruoyao <xry111@xry111.site>
School of Aerospace Science and Technology, Xidian University

Patchew 2.1-devel-b67e4c2

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