From: Qiang Yu <quic_qianyu@quicinc.com>
Some QCOM PCIe PHYs support no_csr reset. Unlike BCR reset which resets the
whole PHY (hardware and register), no_csr reset only resets PHY hardware
but retains register values, which means PHY setting can be skipped during
PHY init if PCIe link is enabled in booltloader and only no_csr is toggled
after that.
Hence, determine whether the PHY has been enabled in bootloader by
verifying QPHY_START_CTRL register. If it's programmed and no_csr reset is
available, skip BCR reset and PHY register setting to establish the PCIe
link with bootloader - programmed PHY settings.
Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com>
Signed-off-by: Wenbin Yao <quic_wenbyao@quicinc.com>
---
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 60 +++++++++++++++++++-----
1 file changed, 49 insertions(+), 11 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
index 219266125cf2..6938b72df7fa 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
@@ -2805,6 +2805,7 @@ struct qmp_pcie {
const struct qmp_phy_cfg *cfg;
bool tcsr_4ln_config;
+ bool skip_init;
void __iomem *serdes;
void __iomem *pcs;
@@ -3976,7 +3977,9 @@ static int qmp_pcie_init(struct phy *phy)
{
struct qmp_pcie *qmp = phy_get_drvdata(phy);
const struct qmp_phy_cfg *cfg = qmp->cfg;
+ void __iomem *pcs = qmp->pcs;
int ret;
+ bool phy_initialized;
ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
if (ret) {
@@ -3984,10 +3987,18 @@ static int qmp_pcie_init(struct phy *phy)
return ret;
}
- ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets);
- if (ret) {
- dev_err(qmp->dev, "reset assert failed\n");
- goto err_disable_regulators;
+ phy_initialized = !!(readl(pcs + cfg->regs[QPHY_START_CTRL]));
+ qmp->skip_init = qmp->nocsr_reset && phy_initialized;
+ /*
+ * Toggle BCR reset for PHY that doesn't support no_csr
+ * reset or has not been initialized
+ */
+ if (!qmp->skip_init) {
+ ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets);
+ if (ret) {
+ dev_err(qmp->dev, "reset assert failed\n");
+ goto err_disable_regulators;
+ }
}
ret = reset_control_assert(qmp->nocsr_reset);
@@ -3998,10 +4009,12 @@ static int qmp_pcie_init(struct phy *phy)
usleep_range(200, 300);
- ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets);
- if (ret) {
- dev_err(qmp->dev, "reset deassert failed\n");
- goto err_assert_reset;
+ if (!qmp->skip_init) {
+ ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets);
+ if (ret) {
+ dev_err(qmp->dev, "reset deassert failed\n");
+ goto err_assert_reset;
+ }
}
ret = clk_bulk_prepare_enable(ARRAY_SIZE(qmp_pciephy_clk_l), qmp->clks);
@@ -4011,7 +4024,8 @@ static int qmp_pcie_init(struct phy *phy)
return 0;
err_assert_reset:
- reset_control_bulk_assert(cfg->num_resets, qmp->resets);
+ if (!qmp->skip_init)
+ reset_control_bulk_assert(cfg->num_resets, qmp->resets);
err_disable_regulators:
regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
@@ -4023,7 +4037,10 @@ static int qmp_pcie_exit(struct phy *phy)
struct qmp_pcie *qmp = phy_get_drvdata(phy);
const struct qmp_phy_cfg *cfg = qmp->cfg;
- reset_control_bulk_assert(cfg->num_resets, qmp->resets);
+ if (qmp->nocsr_reset)
+ reset_control_assert(qmp->nocsr_reset);
+ else
+ reset_control_bulk_assert(cfg->num_resets, qmp->resets);
clk_bulk_disable_unprepare(ARRAY_SIZE(qmp_pciephy_clk_l), qmp->clks);
@@ -4042,6 +4059,13 @@ static int qmp_pcie_power_on(struct phy *phy)
unsigned int mask, val;
int ret;
+ /*
+ * Write CSR register for PHY that doesn't support no_csr
+ * reset or has not been initialized
+ */
+ if (qmp->skip_init)
+ goto skip_tbls_init;
+
qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
cfg->pwrdn_ctrl);
@@ -4053,6 +4077,7 @@ static int qmp_pcie_power_on(struct phy *phy)
qmp_pcie_init_registers(qmp, &cfg->tbls);
qmp_pcie_init_registers(qmp, mode_tbls);
+skip_tbls_init:
ret = clk_bulk_prepare_enable(qmp->num_pipe_clks, qmp->pipe_clks);
if (ret)
return ret;
@@ -4063,6 +4088,9 @@ static int qmp_pcie_power_on(struct phy *phy)
goto err_disable_pipe_clk;
}
+ if (qmp->skip_init)
+ goto skip_serdes_start;
+
/* Pull PHY out of reset state */
qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
@@ -4072,6 +4100,7 @@ static int qmp_pcie_power_on(struct phy *phy)
if (!cfg->skip_start_delay)
usleep_range(1000, 1200);
+skip_serdes_start:
status = pcs + cfg->regs[QPHY_PCS_STATUS];
mask = cfg->phy_status;
ret = readl_poll_timeout(status, val, !(val & mask), 200,
@@ -4096,7 +4125,15 @@ static int qmp_pcie_power_off(struct phy *phy)
clk_bulk_disable_unprepare(qmp->num_pipe_clks, qmp->pipe_clks);
- /* PHY reset */
+ /* When PHY is powered off, only qmp->nocsr_reset needs to be checked.
+ * In this way, no matter whether the PHY settings were initially
+ * programmed by bootloader or PHY driver itself, we can reuse them
+ * when PHY is powered on next time.
+ */
+ if (qmp->nocsr_reset)
+ goto skip_phy_deinit;
+
+ /* PHY reset */
qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
/* stop SerDes and Phy-Coding-Sublayer */
@@ -4107,6 +4144,7 @@ static int qmp_pcie_power_off(struct phy *phy)
qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
cfg->pwrdn_ctrl);
+skip_phy_deinit:
return 0;
}
--
2.34.1On Thu, Feb 20, 2025 at 06:22:53PM +0800, Wenbin Yao wrote:
> From: Qiang Yu <quic_qianyu@quicinc.com>
>
> Some QCOM PCIe PHYs support no_csr reset. Unlike BCR reset which resets the
> whole PHY (hardware and register), no_csr reset only resets PHY hardware
> but retains register values, which means PHY setting can be skipped during
> PHY init if PCIe link is enabled in booltloader and only no_csr is toggled
> after that.
>
> Hence, determine whether the PHY has been enabled in bootloader by
> verifying QPHY_START_CTRL register. If it's programmed and no_csr reset is
> available, skip BCR reset and PHY register setting to establish the PCIe
> link with bootloader - programmed PHY settings.
>
> Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com>
> Signed-off-by: Wenbin Yao <quic_wenbyao@quicinc.com>
Some nitpicks below.
> ---
> drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 60 +++++++++++++++++++-----
> 1 file changed, 49 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> index 219266125cf2..6938b72df7fa 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> @@ -2805,6 +2805,7 @@ struct qmp_pcie {
>
> const struct qmp_phy_cfg *cfg;
> bool tcsr_4ln_config;
> + bool skip_init;
>
> void __iomem *serdes;
> void __iomem *pcs;
> @@ -3976,7 +3977,9 @@ static int qmp_pcie_init(struct phy *phy)
> {
> struct qmp_pcie *qmp = phy_get_drvdata(phy);
> const struct qmp_phy_cfg *cfg = qmp->cfg;
> + void __iomem *pcs = qmp->pcs;
> int ret;
> + bool phy_initialized;
>
> ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
> if (ret) {
> @@ -3984,10 +3987,18 @@ static int qmp_pcie_init(struct phy *phy)
> return ret;
> }
>
> - ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets);
> - if (ret) {
> - dev_err(qmp->dev, "reset assert failed\n");
> - goto err_disable_regulators;
> + phy_initialized = !!(readl(pcs + cfg->regs[QPHY_START_CTRL]));
> + qmp->skip_init = qmp->nocsr_reset && phy_initialized;
> + /*
> + * Toggle BCR reset for PHY that doesn't support no_csr
> + * reset or has not been initialized
Please make use of 80 column width.
> + */
> + if (!qmp->skip_init) {
> + ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets);
> + if (ret) {
> + dev_err(qmp->dev, "reset assert failed\n");
> + goto err_disable_regulators;
> + }
> }
>
> ret = reset_control_assert(qmp->nocsr_reset);
> @@ -3998,10 +4009,12 @@ static int qmp_pcie_init(struct phy *phy)
>
> usleep_range(200, 300);
>
> - ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets);
> - if (ret) {
> - dev_err(qmp->dev, "reset deassert failed\n");
> - goto err_assert_reset;
> + if (!qmp->skip_init) {
> + ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets);
> + if (ret) {
> + dev_err(qmp->dev, "reset deassert failed\n");
> + goto err_assert_reset;
> + }
> }
>
> ret = clk_bulk_prepare_enable(ARRAY_SIZE(qmp_pciephy_clk_l), qmp->clks);
> @@ -4011,7 +4024,8 @@ static int qmp_pcie_init(struct phy *phy)
> return 0;
>
> err_assert_reset:
> - reset_control_bulk_assert(cfg->num_resets, qmp->resets);
> + if (!qmp->skip_init)
> + reset_control_bulk_assert(cfg->num_resets, qmp->resets);
> err_disable_regulators:
> regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
>
> @@ -4023,7 +4037,10 @@ static int qmp_pcie_exit(struct phy *phy)
> struct qmp_pcie *qmp = phy_get_drvdata(phy);
> const struct qmp_phy_cfg *cfg = qmp->cfg;
>
> - reset_control_bulk_assert(cfg->num_resets, qmp->resets);
> + if (qmp->nocsr_reset)
> + reset_control_assert(qmp->nocsr_reset);
> + else
> + reset_control_bulk_assert(cfg->num_resets, qmp->resets);
>
> clk_bulk_disable_unprepare(ARRAY_SIZE(qmp_pciephy_clk_l), qmp->clks);
>
> @@ -4042,6 +4059,13 @@ static int qmp_pcie_power_on(struct phy *phy)
> unsigned int mask, val;
> int ret;
>
> + /*
> + * Write CSR register for PHY that doesn't support no_csr
> + * reset or has not been initialized
Same here.
> + */
> + if (qmp->skip_init)
> + goto skip_tbls_init;
> +
> qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
> cfg->pwrdn_ctrl);
>
> @@ -4053,6 +4077,7 @@ static int qmp_pcie_power_on(struct phy *phy)
> qmp_pcie_init_registers(qmp, &cfg->tbls);
> qmp_pcie_init_registers(qmp, mode_tbls);
>
> +skip_tbls_init:
> ret = clk_bulk_prepare_enable(qmp->num_pipe_clks, qmp->pipe_clks);
> if (ret)
> return ret;
> @@ -4063,6 +4088,9 @@ static int qmp_pcie_power_on(struct phy *phy)
> goto err_disable_pipe_clk;
> }
>
> + if (qmp->skip_init)
> + goto skip_serdes_start;
> +
> /* Pull PHY out of reset state */
> qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
>
> @@ -4072,6 +4100,7 @@ static int qmp_pcie_power_on(struct phy *phy)
> if (!cfg->skip_start_delay)
> usleep_range(1000, 1200);
>
> +skip_serdes_start:
> status = pcs + cfg->regs[QPHY_PCS_STATUS];
> mask = cfg->phy_status;
> ret = readl_poll_timeout(status, val, !(val & mask), 200,
> @@ -4096,7 +4125,15 @@ static int qmp_pcie_power_off(struct phy *phy)
>
> clk_bulk_disable_unprepare(qmp->num_pipe_clks, qmp->pipe_clks);
>
> - /* PHY reset */
> + /* When PHY is powered off, only qmp->nocsr_reset needs to be checked.
s/'When PHY is powered off,'/'While powering off the PHY,'
> + * In this way, no matter whether the PHY settings were initially
> + * programmed by bootloader or PHY driver itself, we can reuse them
It is really possible to have bootloader not programming the init sequence for
no_csr reset platforms? The comment sounds like it is possible. But I heard the
opposite.
> + * when PHY is powered on next time.
> + */
> + if (qmp->nocsr_reset)
> + goto skip_phy_deinit;
> +
> + /* PHY reset */
Spurious tab before the start of the comment.
- Mani
--
மணிவண்ணன் சதாசிவம்
On 2/24/2025 3:33 PM, Manivannan Sadhasivam wrote:
> On Thu, Feb 20, 2025 at 06:22:53PM +0800, Wenbin Yao wrote:
>> From: Qiang Yu <quic_qianyu@quicinc.com>
>>
>> Some QCOM PCIe PHYs support no_csr reset. Unlike BCR reset which resets the
>> whole PHY (hardware and register), no_csr reset only resets PHY hardware
>> but retains register values, which means PHY setting can be skipped during
>> PHY init if PCIe link is enabled in booltloader and only no_csr is toggled
>> after that.
>>
>> Hence, determine whether the PHY has been enabled in bootloader by
>> verifying QPHY_START_CTRL register. If it's programmed and no_csr reset is
>> available, skip BCR reset and PHY register setting to establish the PCIe
>> link with bootloader - programmed PHY settings.
>>
>> Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com>
>> Signed-off-by: Wenbin Yao <quic_wenbyao@quicinc.com>
> Some nitpicks below.
>
>> ---
>> drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 60 +++++++++++++++++++-----
>> 1 file changed, 49 insertions(+), 11 deletions(-)
>>
>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
>> index 219266125cf2..6938b72df7fa 100644
>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
>> @@ -2805,6 +2805,7 @@ struct qmp_pcie {
>>
>> const struct qmp_phy_cfg *cfg;
>> bool tcsr_4ln_config;
>> + bool skip_init;
>>
>> void __iomem *serdes;
>> void __iomem *pcs;
>> @@ -3976,7 +3977,9 @@ static int qmp_pcie_init(struct phy *phy)
>> {
>> struct qmp_pcie *qmp = phy_get_drvdata(phy);
>> const struct qmp_phy_cfg *cfg = qmp->cfg;
>> + void __iomem *pcs = qmp->pcs;
>> int ret;
>> + bool phy_initialized;
>>
>> ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
>> if (ret) {
>> @@ -3984,10 +3987,18 @@ static int qmp_pcie_init(struct phy *phy)
>> return ret;
>> }
>>
>> - ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets);
>> - if (ret) {
>> - dev_err(qmp->dev, "reset assert failed\n");
>> - goto err_disable_regulators;
>> + phy_initialized = !!(readl(pcs + cfg->regs[QPHY_START_CTRL]));
>> + qmp->skip_init = qmp->nocsr_reset && phy_initialized;
>> + /*
>> + * Toggle BCR reset for PHY that doesn't support no_csr
>> + * reset or has not been initialized
> Please make use of 80 column width.
Will fix it.
>
>> + */
>> + if (!qmp->skip_init) {
>> + ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets);
>> + if (ret) {
>> + dev_err(qmp->dev, "reset assert failed\n");
>> + goto err_disable_regulators;
>> + }
>> }
>>
>> ret = reset_control_assert(qmp->nocsr_reset);
>> @@ -3998,10 +4009,12 @@ static int qmp_pcie_init(struct phy *phy)
>>
>> usleep_range(200, 300);
>>
>> - ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets);
>> - if (ret) {
>> - dev_err(qmp->dev, "reset deassert failed\n");
>> - goto err_assert_reset;
>> + if (!qmp->skip_init) {
>> + ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets);
>> + if (ret) {
>> + dev_err(qmp->dev, "reset deassert failed\n");
>> + goto err_assert_reset;
>> + }
>> }
>>
>> ret = clk_bulk_prepare_enable(ARRAY_SIZE(qmp_pciephy_clk_l), qmp->clks);
>> @@ -4011,7 +4024,8 @@ static int qmp_pcie_init(struct phy *phy)
>> return 0;
>>
>> err_assert_reset:
>> - reset_control_bulk_assert(cfg->num_resets, qmp->resets);
>> + if (!qmp->skip_init)
>> + reset_control_bulk_assert(cfg->num_resets, qmp->resets);
>> err_disable_regulators:
>> regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
>>
>> @@ -4023,7 +4037,10 @@ static int qmp_pcie_exit(struct phy *phy)
>> struct qmp_pcie *qmp = phy_get_drvdata(phy);
>> const struct qmp_phy_cfg *cfg = qmp->cfg;
>>
>> - reset_control_bulk_assert(cfg->num_resets, qmp->resets);
>> + if (qmp->nocsr_reset)
>> + reset_control_assert(qmp->nocsr_reset);
>> + else
>> + reset_control_bulk_assert(cfg->num_resets, qmp->resets);
>>
>> clk_bulk_disable_unprepare(ARRAY_SIZE(qmp_pciephy_clk_l), qmp->clks);
>>
>> @@ -4042,6 +4059,13 @@ static int qmp_pcie_power_on(struct phy *phy)
>> unsigned int mask, val;
>> int ret;
>>
>> + /*
>> + * Write CSR register for PHY that doesn't support no_csr
>> + * reset or has not been initialized
> Same here.
Will fix it.
>
>> + */
>> + if (qmp->skip_init)
>> + goto skip_tbls_init;
>> +
>> qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
>> cfg->pwrdn_ctrl);
>>
>> @@ -4053,6 +4077,7 @@ static int qmp_pcie_power_on(struct phy *phy)
>> qmp_pcie_init_registers(qmp, &cfg->tbls);
>> qmp_pcie_init_registers(qmp, mode_tbls);
>>
>> +skip_tbls_init:
>> ret = clk_bulk_prepare_enable(qmp->num_pipe_clks, qmp->pipe_clks);
>> if (ret)
>> return ret;
>> @@ -4063,6 +4088,9 @@ static int qmp_pcie_power_on(struct phy *phy)
>> goto err_disable_pipe_clk;
>> }
>>
>> + if (qmp->skip_init)
>> + goto skip_serdes_start;
>> +
>> /* Pull PHY out of reset state */
>> qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
>>
>> @@ -4072,6 +4100,7 @@ static int qmp_pcie_power_on(struct phy *phy)
>> if (!cfg->skip_start_delay)
>> usleep_range(1000, 1200);
>>
>> +skip_serdes_start:
>> status = pcs + cfg->regs[QPHY_PCS_STATUS];
>> mask = cfg->phy_status;
>> ret = readl_poll_timeout(status, val, !(val & mask), 200,
>> @@ -4096,7 +4125,15 @@ static int qmp_pcie_power_off(struct phy *phy)
>>
>> clk_bulk_disable_unprepare(qmp->num_pipe_clks, qmp->pipe_clks);
>>
>> - /* PHY reset */
>> + /* When PHY is powered off, only qmp->nocsr_reset needs to be checked.
> s/'When PHY is powered off,'/'While powering off the PHY,'
Will fix it.
>
>> + * In this way, no matter whether the PHY settings were initially
>> + * programmed by bootloader or PHY driver itself, we can reuse them
> It is really possible to have bootloader not programming the init sequence for
> no_csr reset platforms? The comment sounds like it is possible. But I heard the
> opposite.
PCIe3 on X1E80100 QCP is disabled by default in UEFI. We need to enable it
manually in UEFI shell if we want.
>
>> + * when PHY is powered on next time.
>> + */
>> + if (qmp->nocsr_reset)
>> + goto skip_phy_deinit;
>> +
>> + /* PHY reset */
> Spurious tab before the start of the comment.
Will fix it.
>
> - Mani
>
--
With best wishes
Wenbin
On 24.02.2025 9:46 AM, Wenbin Yao (Consultant) wrote: > On 2/24/2025 3:33 PM, Manivannan Sadhasivam wrote: >> On Thu, Feb 20, 2025 at 06:22:53PM +0800, Wenbin Yao wrote: >>> From: Qiang Yu <quic_qianyu@quicinc.com> >>> >>> Some QCOM PCIe PHYs support no_csr reset. Unlike BCR reset which resets the >>> whole PHY (hardware and register), no_csr reset only resets PHY hardware >>> but retains register values, which means PHY setting can be skipped during >>> PHY init if PCIe link is enabled in booltloader and only no_csr is toggled >>> after that. >>> >>> Hence, determine whether the PHY has been enabled in bootloader by >>> verifying QPHY_START_CTRL register. If it's programmed and no_csr reset is >>> available, skip BCR reset and PHY register setting to establish the PCIe >>> link with bootloader - programmed PHY settings. >>> >>> Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com> >>> Signed-off-by: Wenbin Yao <quic_wenbyao@quicinc.com> >> Some nitpicks below. >> >>> --- [...] >> >>> + * In this way, no matter whether the PHY settings were initially >>> + * programmed by bootloader or PHY driver itself, we can reuse them >> It is really possible to have bootloader not programming the init sequence for >> no_csr reset platforms? The comment sounds like it is possible. But I heard the >> opposite. > > PCIe3 on X1E80100 QCP is disabled by default in UEFI. We need to enable it > manually in UEFI shell if we want. IIUC this will not be a concern going forward, and this is a special case Konrad
On Mon, Feb 24, 2025 at 12:46:44PM +0100, Konrad Dybcio wrote: > On 24.02.2025 9:46 AM, Wenbin Yao (Consultant) wrote: > > On 2/24/2025 3:33 PM, Manivannan Sadhasivam wrote: > >> On Thu, Feb 20, 2025 at 06:22:53PM +0800, Wenbin Yao wrote: > >>> From: Qiang Yu <quic_qianyu@quicinc.com> > >>> > >>> Some QCOM PCIe PHYs support no_csr reset. Unlike BCR reset which resets the > >>> whole PHY (hardware and register), no_csr reset only resets PHY hardware > >>> but retains register values, which means PHY setting can be skipped during > >>> PHY init if PCIe link is enabled in booltloader and only no_csr is toggled > >>> after that. > >>> > >>> Hence, determine whether the PHY has been enabled in bootloader by > >>> verifying QPHY_START_CTRL register. If it's programmed and no_csr reset is > >>> available, skip BCR reset and PHY register setting to establish the PCIe > >>> link with bootloader - programmed PHY settings. > >>> > >>> Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com> > >>> Signed-off-by: Wenbin Yao <quic_wenbyao@quicinc.com> > >> Some nitpicks below. > >> > >>> --- > > [...] > > >> > >>> + * In this way, no matter whether the PHY settings were initially > >>> + * programmed by bootloader or PHY driver itself, we can reuse them > >> It is really possible to have bootloader not programming the init sequence for > >> no_csr reset platforms? The comment sounds like it is possible. But I heard the > >> opposite. > > > > PCIe3 on X1E80100 QCP is disabled by default in UEFI. We need to enable it > > manually in UEFI shell if we want. > > IIUC this will not be a concern going forward, and this is a special case > I'm wondering how many *special* cases we may have to deal with going forward. Anyhow, I would propose to atleast throw an error and fail probe() if: * the platform has no_csr reset AND * bootloader has not initialized the PHY AND * there are no init sequences in the kernel - Mani -- மணிவண்ணன் சதாசிவம்
On 2/24/2025 8:24 PM, Manivannan Sadhasivam wrote: > On Mon, Feb 24, 2025 at 12:46:44PM +0100, Konrad Dybcio wrote: >> On 24.02.2025 9:46 AM, Wenbin Yao (Consultant) wrote: >>> On 2/24/2025 3:33 PM, Manivannan Sadhasivam wrote: >>>> On Thu, Feb 20, 2025 at 06:22:53PM +0800, Wenbin Yao wrote: >>>>> From: Qiang Yu <quic_qianyu@quicinc.com> >>>>> >>>>> Some QCOM PCIe PHYs support no_csr reset. Unlike BCR reset which resets the >>>>> whole PHY (hardware and register), no_csr reset only resets PHY hardware >>>>> but retains register values, which means PHY setting can be skipped during >>>>> PHY init if PCIe link is enabled in booltloader and only no_csr is toggled >>>>> after that. >>>>> >>>>> Hence, determine whether the PHY has been enabled in bootloader by >>>>> verifying QPHY_START_CTRL register. If it's programmed and no_csr reset is >>>>> available, skip BCR reset and PHY register setting to establish the PCIe >>>>> link with bootloader - programmed PHY settings. >>>>> >>>>> Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com> >>>>> Signed-off-by: Wenbin Yao <quic_wenbyao@quicinc.com> >>>> Some nitpicks below. >>>> >>>>> --- >> [...] >> >>>>> + * In this way, no matter whether the PHY settings were initially >>>>> + * programmed by bootloader or PHY driver itself, we can reuse them >>>> It is really possible to have bootloader not programming the init sequence for >>>> no_csr reset platforms? The comment sounds like it is possible. But I heard the >>>> opposite. >>> PCIe3 on X1E80100 QCP is disabled by default in UEFI. We need to enable it >>> manually in UEFI shell if we want. >> IIUC this will not be a concern going forward, and this is a special case >> > I'm wondering how many *special* cases we may have to deal with going forward. > Anyhow, I would propose to atleast throw an error and fail probe() if: > > * the platform has no_csr reset AND > * bootloader has not initialized the PHY AND > * there are no init sequences in the kernel > > - Mani Hmmm, regardless of whether it's a special case, we can't assume that UEFI will enable the PHY supporting no_csr reset on all platforms. It's a bit risky. If we make such an assumption, we also won't need to check whether the PHY is enabled by UEFI during powering on. We just need to check whether no_csr reset is available. But it makes sense to check the exsitence of PHY senquence. How about adding the check in qmp_pcie_init, if a PHY supports no_csr reset and isn't initialized in UEFI and there is no cfg->tbls, return error and print some error log so that the PCIe controller will fail to probe. -- With best wishes Wenbin
On Tue, Feb 25, 2025 at 04:06:16PM +0800, Wenbin Yao (Consultant) wrote: > On 2/24/2025 8:24 PM, Manivannan Sadhasivam wrote: > > On Mon, Feb 24, 2025 at 12:46:44PM +0100, Konrad Dybcio wrote: > > > On 24.02.2025 9:46 AM, Wenbin Yao (Consultant) wrote: > > > > On 2/24/2025 3:33 PM, Manivannan Sadhasivam wrote: > > > > > On Thu, Feb 20, 2025 at 06:22:53PM +0800, Wenbin Yao wrote: > > > > > > From: Qiang Yu <quic_qianyu@quicinc.com> > > > > > > > > > > > > Some QCOM PCIe PHYs support no_csr reset. Unlike BCR reset which resets the > > > > > > whole PHY (hardware and register), no_csr reset only resets PHY hardware > > > > > > but retains register values, which means PHY setting can be skipped during > > > > > > PHY init if PCIe link is enabled in booltloader and only no_csr is toggled > > > > > > after that. > > > > > > > > > > > > Hence, determine whether the PHY has been enabled in bootloader by > > > > > > verifying QPHY_START_CTRL register. If it's programmed and no_csr reset is > > > > > > available, skip BCR reset and PHY register setting to establish the PCIe > > > > > > link with bootloader - programmed PHY settings. > > > > > > > > > > > > Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com> > > > > > > Signed-off-by: Wenbin Yao <quic_wenbyao@quicinc.com> > > > > > Some nitpicks below. > > > > > > > > > > > --- > > > [...] > > > > > > > > > + * In this way, no matter whether the PHY settings were initially > > > > > > + * programmed by bootloader or PHY driver itself, we can reuse them > > > > > It is really possible to have bootloader not programming the init sequence for > > > > > no_csr reset platforms? The comment sounds like it is possible. But I heard the > > > > > opposite. > > > > PCIe3 on X1E80100 QCP is disabled by default in UEFI. We need to enable it > > > > manually in UEFI shell if we want. > > > IIUC this will not be a concern going forward, and this is a special case > > > > > I'm wondering how many *special* cases we may have to deal with going forward. > > Anyhow, I would propose to atleast throw an error and fail probe() if: > > > > * the platform has no_csr reset AND > > * bootloader has not initialized the PHY AND > > * there are no init sequences in the kernel > > > > - Mani > > Hmmm, regardless of whether it's a special case, we can't assume that UEFI > will enable the PHY supporting no_csr reset on all platforms. It's a bit > risky. If we make such an assumption, we also won't need to check whether > the PHY is enabled by UEFI during powering on. We just need to check > whether no_csr reset is available. > I am not supportive of this assumption to be clear. While I am OK with relying on no_csr reset and bootloader programming the PHY, we should also make sure to catch if the PHY doesn't initialize it. Otherwise, the driver would assume that the PHY is working, but the users won't see any PCIe devices. > But it makes sense to check the exsitence of PHY senquence. How about > adding the check in qmp_pcie_init, if a PHY supports no_csr reset and isn't > initialized in UEFI and there is no cfg->tbls, return error and print some > error log so that the PCIe controller will fail to probe. > Sounds good to me. - Mani -- மணிவண்ணன் சதாசிவம்
On 2/25/2025 4:17 PM, Manivannan Sadhasivam wrote: > On Tue, Feb 25, 2025 at 04:06:16PM +0800, Wenbin Yao (Consultant) wrote: >> On 2/24/2025 8:24 PM, Manivannan Sadhasivam wrote: >>> On Mon, Feb 24, 2025 at 12:46:44PM +0100, Konrad Dybcio wrote: >>>> On 24.02.2025 9:46 AM, Wenbin Yao (Consultant) wrote: >>>>> On 2/24/2025 3:33 PM, Manivannan Sadhasivam wrote: >>>>>> On Thu, Feb 20, 2025 at 06:22:53PM +0800, Wenbin Yao wrote: >>>>>>> From: Qiang Yu <quic_qianyu@quicinc.com> >>>>>>> >>>>>>> Some QCOM PCIe PHYs support no_csr reset. Unlike BCR reset which resets the >>>>>>> whole PHY (hardware and register), no_csr reset only resets PHY hardware >>>>>>> but retains register values, which means PHY setting can be skipped during >>>>>>> PHY init if PCIe link is enabled in booltloader and only no_csr is toggled >>>>>>> after that. >>>>>>> >>>>>>> Hence, determine whether the PHY has been enabled in bootloader by >>>>>>> verifying QPHY_START_CTRL register. If it's programmed and no_csr reset is >>>>>>> available, skip BCR reset and PHY register setting to establish the PCIe >>>>>>> link with bootloader - programmed PHY settings. >>>>>>> >>>>>>> Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com> >>>>>>> Signed-off-by: Wenbin Yao <quic_wenbyao@quicinc.com> >>>>>> Some nitpicks below. >>>>>> >>>>>>> --- >>>> [...] >>>> >>>>>>> + * In this way, no matter whether the PHY settings were initially >>>>>>> + * programmed by bootloader or PHY driver itself, we can reuse them >>>>>> It is really possible to have bootloader not programming the init sequence for >>>>>> no_csr reset platforms? The comment sounds like it is possible. But I heard the >>>>>> opposite. >>>>> PCIe3 on X1E80100 QCP is disabled by default in UEFI. We need to enable it >>>>> manually in UEFI shell if we want. >>>> IIUC this will not be a concern going forward, and this is a special case >>>> >>> I'm wondering how many *special* cases we may have to deal with going forward. >>> Anyhow, I would propose to atleast throw an error and fail probe() if: >>> >>> * the platform has no_csr reset AND >>> * bootloader has not initialized the PHY AND >>> * there are no init sequences in the kernel >>> >>> - Mani >> Hmmm, regardless of whether it's a special case, we can't assume that UEFI >> will enable the PHY supporting no_csr reset on all platforms. It's a bit >> risky. If we make such an assumption, we also won't need to check whether >> the PHY is enabled by UEFI during powering on. We just need to check >> whether no_csr reset is available. >> > I am not supportive of this assumption to be clear. While I am OK with relying > on no_csr reset and bootloader programming the PHY, we should also make sure to > catch if the PHY doesn't initialize it. Otherwise, the driver would assume that > the PHY is working, but the users won't see any PCIe devices. > >> But it makes sense to check the exsitence of PHY senquence. How about >> adding the check in qmp_pcie_init, if a PHY supports no_csr reset and isn't >> initialized in UEFI and there is no cfg->tbls, return error and print some >> error log so that the PCIe controller will fail to probe. >> > Sounds good to me. I'm wondering is it necessary to add this check? In current PHY driver, for PHY that doesn't suppot no_csr reset there is also no such check. If a PHY supports no_csr reset and isn't init in UEFI and there is no cfg->tbls, the worst issue is link training fail and PCIe controller will also fail to probe. Adding sucj check seems not change the result. Thanks, Qiang > > - Mani >
On Tue, Feb 25, 2025 at 06:08:03PM +0800, Qiang Yu wrote: > > On 2/25/2025 4:17 PM, Manivannan Sadhasivam wrote: > > On Tue, Feb 25, 2025 at 04:06:16PM +0800, Wenbin Yao (Consultant) wrote: > > > On 2/24/2025 8:24 PM, Manivannan Sadhasivam wrote: > > > > On Mon, Feb 24, 2025 at 12:46:44PM +0100, Konrad Dybcio wrote: > > > > > On 24.02.2025 9:46 AM, Wenbin Yao (Consultant) wrote: > > > > > > On 2/24/2025 3:33 PM, Manivannan Sadhasivam wrote: > > > > > > > On Thu, Feb 20, 2025 at 06:22:53PM +0800, Wenbin Yao wrote: > > > > > > > > From: Qiang Yu <quic_qianyu@quicinc.com> > > > > > > > > > > > > > > > > Some QCOM PCIe PHYs support no_csr reset. Unlike BCR reset which resets the > > > > > > > > whole PHY (hardware and register), no_csr reset only resets PHY hardware > > > > > > > > but retains register values, which means PHY setting can be skipped during > > > > > > > > PHY init if PCIe link is enabled in booltloader and only no_csr is toggled > > > > > > > > after that. > > > > > > > > > > > > > > > > Hence, determine whether the PHY has been enabled in bootloader by > > > > > > > > verifying QPHY_START_CTRL register. If it's programmed and no_csr reset is > > > > > > > > available, skip BCR reset and PHY register setting to establish the PCIe > > > > > > > > link with bootloader - programmed PHY settings. > > > > > > > > > > > > > > > > Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com> > > > > > > > > Signed-off-by: Wenbin Yao <quic_wenbyao@quicinc.com> > > > > > > > Some nitpicks below. > > > > > > > > > > > > > > > --- > > > > > [...] > > > > > > > > > > > > > + * In this way, no matter whether the PHY settings were initially > > > > > > > > + * programmed by bootloader or PHY driver itself, we can reuse them > > > > > > > It is really possible to have bootloader not programming the init sequence for > > > > > > > no_csr reset platforms? The comment sounds like it is possible. But I heard the > > > > > > > opposite. > > > > > > PCIe3 on X1E80100 QCP is disabled by default in UEFI. We need to enable it > > > > > > manually in UEFI shell if we want. > > > > > IIUC this will not be a concern going forward, and this is a special case > > > > > > > > > I'm wondering how many *special* cases we may have to deal with going forward. > > > > Anyhow, I would propose to atleast throw an error and fail probe() if: > > > > > > > > * the platform has no_csr reset AND > > > > * bootloader has not initialized the PHY AND > > > > * there are no init sequences in the kernel > > > > > > > > - Mani > > > Hmmm, regardless of whether it's a special case, we can't assume that UEFI > > > will enable the PHY supporting no_csr reset on all platforms. It's a bit > > > risky. If we make such an assumption, we also won't need to check whether > > > the PHY is enabled by UEFI during powering on. We just need to check > > > whether no_csr reset is available. > > > > > I am not supportive of this assumption to be clear. While I am OK with relying > > on no_csr reset and bootloader programming the PHY, we should also make sure to > > catch if the PHY doesn't initialize it. Otherwise, the driver would assume that > > the PHY is working, but the users won't see any PCIe devices. > > > > > But it makes sense to check the exsitence of PHY senquence. How about > > > adding the check in qmp_pcie_init, if a PHY supports no_csr reset and isn't > > > initialized in UEFI and there is no cfg->tbls, return error and print some > > > error log so that the PCIe controller will fail to probe. > > > > > Sounds good to me. > I'm wondering is it necessary to add this check? In current PHY driver, > for PHY that doesn't suppot no_csr reset there is also no such check. > If a PHY supports no_csr reset and isn't init in UEFI and there is no > cfg->tbls, the worst issue is link training fail and PCIe controller will > also fail to probe. Adding sucj check seems not change the result. Failing the training is a random error which can mean a lot, e.g. the missing voltage rail. An explicit check is beneficial, it helps developers (and users) to better understand the reason of the failure. -- With best wishes Dmitry
On 2/25/2025 7:46 PM, Dmitry Baryshkov wrote: > On Tue, Feb 25, 2025 at 06:08:03PM +0800, Qiang Yu wrote: >> On 2/25/2025 4:17 PM, Manivannan Sadhasivam wrote: >>> On Tue, Feb 25, 2025 at 04:06:16PM +0800, Wenbin Yao (Consultant) wrote: >>>> On 2/24/2025 8:24 PM, Manivannan Sadhasivam wrote: >>>>> On Mon, Feb 24, 2025 at 12:46:44PM +0100, Konrad Dybcio wrote: >>>>>> On 24.02.2025 9:46 AM, Wenbin Yao (Consultant) wrote: >>>>>>> On 2/24/2025 3:33 PM, Manivannan Sadhasivam wrote: >>>>>>>> On Thu, Feb 20, 2025 at 06:22:53PM +0800, Wenbin Yao wrote: >>>>>>>>> From: Qiang Yu <quic_qianyu@quicinc.com> >>>>>>>>> >>>>>>>>> Some QCOM PCIe PHYs support no_csr reset. Unlike BCR reset which resets the >>>>>>>>> whole PHY (hardware and register), no_csr reset only resets PHY hardware >>>>>>>>> but retains register values, which means PHY setting can be skipped during >>>>>>>>> PHY init if PCIe link is enabled in booltloader and only no_csr is toggled >>>>>>>>> after that. >>>>>>>>> >>>>>>>>> Hence, determine whether the PHY has been enabled in bootloader by >>>>>>>>> verifying QPHY_START_CTRL register. If it's programmed and no_csr reset is >>>>>>>>> available, skip BCR reset and PHY register setting to establish the PCIe >>>>>>>>> link with bootloader - programmed PHY settings. >>>>>>>>> >>>>>>>>> Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com> >>>>>>>>> Signed-off-by: Wenbin Yao <quic_wenbyao@quicinc.com> >>>>>>>> Some nitpicks below. >>>>>>>> >>>>>>>>> --- >>>>>> [...] >>>>>> >>>>>>>>> + * In this way, no matter whether the PHY settings were initially >>>>>>>>> + * programmed by bootloader or PHY driver itself, we can reuse them >>>>>>>> It is really possible to have bootloader not programming the init sequence for >>>>>>>> no_csr reset platforms? The comment sounds like it is possible. But I heard the >>>>>>>> opposite. >>>>>>> PCIe3 on X1E80100 QCP is disabled by default in UEFI. We need to enable it >>>>>>> manually in UEFI shell if we want. >>>>>> IIUC this will not be a concern going forward, and this is a special case >>>>>> >>>>> I'm wondering how many *special* cases we may have to deal with going forward. >>>>> Anyhow, I would propose to atleast throw an error and fail probe() if: >>>>> >>>>> * the platform has no_csr reset AND >>>>> * bootloader has not initialized the PHY AND >>>>> * there are no init sequences in the kernel >>>>> >>>>> - Mani >>>> Hmmm, regardless of whether it's a special case, we can't assume that UEFI >>>> will enable the PHY supporting no_csr reset on all platforms. It's a bit >>>> risky. If we make such an assumption, we also won't need to check whether >>>> the PHY is enabled by UEFI during powering on. We just need to check >>>> whether no_csr reset is available. >>>> >>> I am not supportive of this assumption to be clear. While I am OK with relying >>> on no_csr reset and bootloader programming the PHY, we should also make sure to >>> catch if the PHY doesn't initialize it. Otherwise, the driver would assume that >>> the PHY is working, but the users won't see any PCIe devices. >>> >>>> But it makes sense to check the exsitence of PHY senquence. How about >>>> adding the check in qmp_pcie_init, if a PHY supports no_csr reset and isn't >>>> initialized in UEFI and there is no cfg->tbls, return error and print some >>>> error log so that the PCIe controller will fail to probe. >>>> >>> Sounds good to me. >> I'm wondering is it necessary to add this check? In current PHY driver, >> for PHY that doesn't suppot no_csr reset there is also no such check. >> If a PHY supports no_csr reset and isn't init in UEFI and there is no >> cfg->tbls, the worst issue is link training fail and PCIe controller will >> also fail to probe. Adding sucj check seems not change the result. > Failing the training is a random error which can mean a lot, e.g. the > missing voltage rail. An explicit check is beneficial, it helps > developers (and users) to better understand the reason of the failure. In the struct qmp_phy_cfg, tbls is not a pointer, we can't directly check if tbls == NULL to determine if the PHY init sequence is available. Can we add a separate patch to change the definition from "const struct qmp_phy_cfg_tbls tbls" to "const struct qmp_phy_cfg_tbls *tbls" like tlbs_rc and tbls_ep, even though this will affect all platforms?
On Wed, Feb 26, 2025 at 11:12:18AM +0800, Qiang Yu wrote: > > On 2/25/2025 7:46 PM, Dmitry Baryshkov wrote: > > On Tue, Feb 25, 2025 at 06:08:03PM +0800, Qiang Yu wrote: > > > On 2/25/2025 4:17 PM, Manivannan Sadhasivam wrote: > > > > On Tue, Feb 25, 2025 at 04:06:16PM +0800, Wenbin Yao (Consultant) wrote: > > > > > On 2/24/2025 8:24 PM, Manivannan Sadhasivam wrote: > > > > > > On Mon, Feb 24, 2025 at 12:46:44PM +0100, Konrad Dybcio wrote: > > > > > > > On 24.02.2025 9:46 AM, Wenbin Yao (Consultant) wrote: > > > > > > > > On 2/24/2025 3:33 PM, Manivannan Sadhasivam wrote: > > > > > > > > > On Thu, Feb 20, 2025 at 06:22:53PM +0800, Wenbin Yao wrote: > > > > > > > > > > From: Qiang Yu <quic_qianyu@quicinc.com> > > > > > > > > > > > > > > > > > > > > Some QCOM PCIe PHYs support no_csr reset. Unlike BCR reset which resets the > > > > > > > > > > whole PHY (hardware and register), no_csr reset only resets PHY hardware > > > > > > > > > > but retains register values, which means PHY setting can be skipped during > > > > > > > > > > PHY init if PCIe link is enabled in booltloader and only no_csr is toggled > > > > > > > > > > after that. > > > > > > > > > > > > > > > > > > > > Hence, determine whether the PHY has been enabled in bootloader by > > > > > > > > > > verifying QPHY_START_CTRL register. If it's programmed and no_csr reset is > > > > > > > > > > available, skip BCR reset and PHY register setting to establish the PCIe > > > > > > > > > > link with bootloader - programmed PHY settings. > > > > > > > > > > > > > > > > > > > > Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com> > > > > > > > > > > Signed-off-by: Wenbin Yao <quic_wenbyao@quicinc.com> > > > > > > > > > Some nitpicks below. > > > > > > > > > > > > > > > > > > > --- > > > > > > > [...] > > > > > > > > > > > > > > > > > + * In this way, no matter whether the PHY settings were initially > > > > > > > > > > + * programmed by bootloader or PHY driver itself, we can reuse them > > > > > > > > > It is really possible to have bootloader not programming the init sequence for > > > > > > > > > no_csr reset platforms? The comment sounds like it is possible. But I heard the > > > > > > > > > opposite. > > > > > > > > PCIe3 on X1E80100 QCP is disabled by default in UEFI. We need to enable it > > > > > > > > manually in UEFI shell if we want. > > > > > > > IIUC this will not be a concern going forward, and this is a special case > > > > > > > > > > > > > I'm wondering how many *special* cases we may have to deal with going forward. > > > > > > Anyhow, I would propose to atleast throw an error and fail probe() if: > > > > > > > > > > > > * the platform has no_csr reset AND > > > > > > * bootloader has not initialized the PHY AND > > > > > > * there are no init sequences in the kernel > > > > > > > > > > > > - Mani > > > > > Hmmm, regardless of whether it's a special case, we can't assume that UEFI > > > > > will enable the PHY supporting no_csr reset on all platforms. It's a bit > > > > > risky. If we make such an assumption, we also won't need to check whether > > > > > the PHY is enabled by UEFI during powering on. We just need to check > > > > > whether no_csr reset is available. > > > > > > > > > I am not supportive of this assumption to be clear. While I am OK with relying > > > > on no_csr reset and bootloader programming the PHY, we should also make sure to > > > > catch if the PHY doesn't initialize it. Otherwise, the driver would assume that > > > > the PHY is working, but the users won't see any PCIe devices. > > > > > > > > > But it makes sense to check the exsitence of PHY senquence. How about > > > > > adding the check in qmp_pcie_init, if a PHY supports no_csr reset and isn't > > > > > initialized in UEFI and there is no cfg->tbls, return error and print some > > > > > error log so that the PCIe controller will fail to probe. > > > > > > > > > Sounds good to me. > > > I'm wondering is it necessary to add this check? In current PHY driver, > > > for PHY that doesn't suppot no_csr reset there is also no such check. > > > If a PHY supports no_csr reset and isn't init in UEFI and there is no > > > cfg->tbls, the worst issue is link training fail and PCIe controller will > > > also fail to probe. Adding sucj check seems not change the result. > > Failing the training is a random error which can mean a lot, e.g. the > > missing voltage rail. An explicit check is beneficial, it helps > > developers (and users) to better understand the reason of the failure. > In the struct qmp_phy_cfg, tbls is not a pointer, we can't directly check > if tbls == NULL to determine if the PHY init sequence is available. Can we > add a separate patch to change the definition from > "const struct qmp_phy_cfg_tbls tbls" to > "const struct qmp_phy_cfg_tbls *tbls" like tlbs_rc and tbls_ep, even though > this will affect all platforms? Of course no. There is no need to introduce extra indirection. Checking for qmp_phy_cfg.tbls.serdes_num should be more than enough. No matter what, the PHY with a proper configuration tables will have non-empty SERDES table. -- With best wishes Dmitry
On Wed, Feb 26, 2025 at 07:19:11AM +0200, Dmitry Baryshkov wrote: > On Wed, Feb 26, 2025 at 11:12:18AM +0800, Qiang Yu wrote: > > > > On 2/25/2025 7:46 PM, Dmitry Baryshkov wrote: > > > On Tue, Feb 25, 2025 at 06:08:03PM +0800, Qiang Yu wrote: > > > > On 2/25/2025 4:17 PM, Manivannan Sadhasivam wrote: > > > > > On Tue, Feb 25, 2025 at 04:06:16PM +0800, Wenbin Yao (Consultant) wrote: > > > > > > On 2/24/2025 8:24 PM, Manivannan Sadhasivam wrote: > > > > > > > On Mon, Feb 24, 2025 at 12:46:44PM +0100, Konrad Dybcio wrote: > > > > > > > > On 24.02.2025 9:46 AM, Wenbin Yao (Consultant) wrote: > > > > > > > > > On 2/24/2025 3:33 PM, Manivannan Sadhasivam wrote: > > > > > > > > > > On Thu, Feb 20, 2025 at 06:22:53PM +0800, Wenbin Yao wrote: > > > > > > > > > > > From: Qiang Yu <quic_qianyu@quicinc.com> > > > > > > > > > > > > > > > > > > > > > > Some QCOM PCIe PHYs support no_csr reset. Unlike BCR reset which resets the > > > > > > > > > > > whole PHY (hardware and register), no_csr reset only resets PHY hardware > > > > > > > > > > > but retains register values, which means PHY setting can be skipped during > > > > > > > > > > > PHY init if PCIe link is enabled in booltloader and only no_csr is toggled > > > > > > > > > > > after that. > > > > > > > > > > > > > > > > > > > > > > Hence, determine whether the PHY has been enabled in bootloader by > > > > > > > > > > > verifying QPHY_START_CTRL register. If it's programmed and no_csr reset is > > > > > > > > > > > available, skip BCR reset and PHY register setting to establish the PCIe > > > > > > > > > > > link with bootloader - programmed PHY settings. > > > > > > > > > > > > > > > > > > > > > > Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com> > > > > > > > > > > > Signed-off-by: Wenbin Yao <quic_wenbyao@quicinc.com> > > > > > > > > > > Some nitpicks below. > > > > > > > > > > > > > > > > > > > > > --- > > > > > > > > [...] > > > > > > > > > > > > > > > > > > > + * In this way, no matter whether the PHY settings were initially > > > > > > > > > > > + * programmed by bootloader or PHY driver itself, we can reuse them > > > > > > > > > > It is really possible to have bootloader not programming the init sequence for > > > > > > > > > > no_csr reset platforms? The comment sounds like it is possible. But I heard the > > > > > > > > > > opposite. > > > > > > > > > PCIe3 on X1E80100 QCP is disabled by default in UEFI. We need to enable it > > > > > > > > > manually in UEFI shell if we want. > > > > > > > > IIUC this will not be a concern going forward, and this is a special case > > > > > > > > > > > > > > > I'm wondering how many *special* cases we may have to deal with going forward. > > > > > > > Anyhow, I would propose to atleast throw an error and fail probe() if: > > > > > > > > > > > > > > * the platform has no_csr reset AND > > > > > > > * bootloader has not initialized the PHY AND > > > > > > > * there are no init sequences in the kernel > > > > > > > > > > > > > > - Mani > > > > > > Hmmm, regardless of whether it's a special case, we can't assume that UEFI > > > > > > will enable the PHY supporting no_csr reset on all platforms. It's a bit > > > > > > risky. If we make such an assumption, we also won't need to check whether > > > > > > the PHY is enabled by UEFI during powering on. We just need to check > > > > > > whether no_csr reset is available. > > > > > > > > > > > I am not supportive of this assumption to be clear. While I am OK with relying > > > > > on no_csr reset and bootloader programming the PHY, we should also make sure to > > > > > catch if the PHY doesn't initialize it. Otherwise, the driver would assume that > > > > > the PHY is working, but the users won't see any PCIe devices. > > > > > > > > > > > But it makes sense to check the exsitence of PHY senquence. How about > > > > > > adding the check in qmp_pcie_init, if a PHY supports no_csr reset and isn't > > > > > > initialized in UEFI and there is no cfg->tbls, return error and print some > > > > > > error log so that the PCIe controller will fail to probe. > > > > > > > > > > > Sounds good to me. > > > > I'm wondering is it necessary to add this check? In current PHY driver, > > > > for PHY that doesn't suppot no_csr reset there is also no such check. > > > > If a PHY supports no_csr reset and isn't init in UEFI and there is no > > > > cfg->tbls, the worst issue is link training fail and PCIe controller will > > > > also fail to probe. Adding sucj check seems not change the result. > > > Failing the training is a random error which can mean a lot, e.g. the > > > missing voltage rail. An explicit check is beneficial, it helps > > > developers (and users) to better understand the reason of the failure. > > In the struct qmp_phy_cfg, tbls is not a pointer, we can't directly check > > if tbls == NULL to determine if the PHY init sequence is available. Can we > > add a separate patch to change the definition from > > "const struct qmp_phy_cfg_tbls tbls" to > > "const struct qmp_phy_cfg_tbls *tbls" like tlbs_rc and tbls_ep, even though > > this will affect all platforms? > > Of course no. There is no need to introduce extra indirection. Checking > for qmp_phy_cfg.tbls.serdes_num should be more than enough. No matter > what, the PHY with a proper configuration tables will have non-empty > SERDES table. > +1. The check needs to be present in this series itself and it makes absolute sense to have it. Otherwise, it will become a hard to debug issue. - Mani -- மணிவண்ணன் சதாசிவம்
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