arm64: dts: apple: Add CPU cache information for Apple A7-A11, T2 SoCs

[PATCH 0/9] arm64: dts: apple: Add CPU cache information for Apple A7-A11, T2 SoCs

Posted by Nick Chan 10 months ago

Add CPU cache information for Apple A7-A11, T2 SoCs. On Apple
A10 (T8010), A10X (T8011), T2 (T8012), only the caches in one of the
CPU clusters can be used due to the "Apple Fusion Architecture"
big.LITTLE switcher. The values for the P-cluster is used in this
case.

Signed-off-by: Nick Chan <towinchenmi@gmail.com>
---
Nick Chan (9):
      arm64: dts: apple: s5l8960x: Add CPU caches
      arm64: dts: apple: t7000: Add CPU caches
      arm64: dts: apple: t7001: Add CPU caches
      arm64: dts: apple: s800-0-3: Add CPU caches
      arm64: dts: apple: s8001: Add CPU caches
      arm64: dts: apple: t8010: Add CPU caches
      arm64: dts: apple: t8011: Add CPU caches
      arm64: dts: apple: t8012: Add CPU caches
      arm64: dts: apple: t8015: Add CPU caches

 arch/arm64/boot/dts/apple/s5l8960x.dtsi | 13 +++++++++++++
 arch/arm64/boot/dts/apple/s800-0-3.dtsi | 13 +++++++++++++
 arch/arm64/boot/dts/apple/s8001.dtsi    | 13 +++++++++++++
 arch/arm64/boot/dts/apple/t7000.dtsi    | 13 +++++++++++++
 arch/arm64/boot/dts/apple/t7001.dtsi    | 16 ++++++++++++++++
 arch/arm64/boot/dts/apple/t8010.dtsi    | 13 +++++++++++++
 arch/arm64/boot/dts/apple/t8011.dtsi    | 16 ++++++++++++++++
 arch/arm64/boot/dts/apple/t8012.dtsi    | 13 +++++++++++++
 arch/arm64/boot/dts/apple/t8015.dtsi    | 32 ++++++++++++++++++++++++++++++++
 9 files changed, 142 insertions(+)
---
base-commit: 3febe9de5ca5267618675650871a626d0901f8cb
change-id: 20250220-caches-bea5d32f91fb

Best regards,
-- 
Nick Chan <towinchenmi@gmail.com>

Re: [PATCH 0/9] arm64: dts: apple: Add CPU cache information for Apple A7-A11, T2 SoCs

Posted by Sven Peter 9 months, 3 weeks ago

Hi,

On Thu, Feb 20, 2025, at 13:21, Nick Chan wrote:
> Add CPU cache information for Apple A7-A11, T2 SoCs. On Apple
> A10 (T8010), A10X (T8011), T2 (T8012), only the caches in one of the
> CPU clusters can be used due to the "Apple Fusion Architecture"
> big.LITTLE switcher. The values for the P-cluster is used in this
> case.

So this means that the cache information will be "wrong" when the CPU
is in the lower power states and only correct for the higher ones?
I'm not familiar with how these values are used; are you and do you
know if this will have any weird or unexpected effects?
Would it be better to use the cache size for the lower rather than
the higher states or does this not matter much?

Best,

Sven

Re: [PATCH 0/9] arm64: dts: apple: Add CPU cache information for Apple A7-A11, T2 SoCs

Posted by Nick Chan 9 months, 3 weeks ago

Sven Peter 於 2025/3/1 夜晚7:11 寫道:
> Hi,
>
> On Thu, Feb 20, 2025, at 13:21, Nick Chan wrote:
>> Add CPU cache information for Apple A7-A11, T2 SoCs. On Apple
>> A10 (T8010), A10X (T8011), T2 (T8012), only the caches in one of the
>> CPU clusters can be used due to the "Apple Fusion Architecture"
>> big.LITTLE switcher. The values for the P-cluster is used in this
>> case.
> So this means that the cache information will be "wrong" when the CPU
> is in the lower power states and only correct for the higher ones?
> I'm not familiar with how these values are used; are you and do you
> know if this will have any weird or unexpected effects?
> Would it be better to use the cache size for the lower rather than
> the higher states or does this not matter much?
The information in the device tree is only used for reporting cache sizes in /sys/devices/system/cpu.
It represents the physical cache size which may not be the same as the architecturally visible cache
size. Cache operations in the kernel consult ccsidr_el1 and csselr_el1, so it should be fine.
>
>
>
> Best,
>
>
> Sven
Nick Chan