---Summary---
Mainstream Intel processors have been using Family 6 for a couple of decades.
This series is an audit of all the arch/x86 Intel Family-model checks to get
ready for the upcoming Family 18 and 19 models. It also converts the last
reamaining Intel x86_model checks to VFM ones.

Patch 1-8 : Include Dave Hansen's Acked-by.
Patch 9-15: Almost ready to merge but don't have review tags yet.

---v3 changes---
* Reordered the patches and moved the Acked ones to the front since they are
  likely to get applied sooner.
* Patches 11 and 14 have a slightly different approach now. 
* Improved commit messages overall.
* Dropped the drivers/ fixes. Will post them separately.

---Previous versions---
Refer the v2 cover letter for more background.

v2: https://lore.kernel.org/lkml/20250211194407.2577252-1-sohil.mehta@intel.com/
RFC-v1: https://lore.kernel.org/lkml/20241220213711.1892696-1-sohil.mehta@intel.com/

Sohil Mehta (15):
  x86/apic: Fix 32-bit APIC initialization for extended Intel Families
  x86/cpu/intel: Fix the movsl alignment preference for extended
    Families
  x86/microcode: Update the Intel processor flag scan check
  x86/mtrr: Modify a x86_model check to an Intel VFM check
  x86/cpu/intel: Replace early Family 6 checks with VFM ones
  x86/cpu/intel: Replace Family 15 checks with VFM ones
  x86/cpu/intel: Replace Family 5 model checks with VFM ones
  x86/acpi/cstate: Improve Intel Family model checks
  x86/smpboot: Remove confusing quirk usage in INIT delay
  x86/smpboot: Fix INIT delay assignment for extended Intel Families
  x86/cpu/intel: Fix fast string initialization for extended Families
  x86/pat: Replace Intel x86_model checks with VFM ones
  x86/cpu/intel: Bound the non-architectural constant_tsc model checks
  perf/x86: Simplify Intel PMU initialization
  perf/x86/p4: Replace Pentium 4 model checks with VFM ones

 arch/x86/events/intel/core.c          | 16 ++++--
 arch/x86/events/intel/p4.c            |  7 +--
 arch/x86/events/intel/p6.c            | 26 ++--------
 arch/x86/include/asm/intel-family.h   | 21 +++++++-
 arch/x86/kernel/acpi/cstate.c         |  8 +--
 arch/x86/kernel/apic/apic.c           |  4 +-
 arch/x86/kernel/cpu/intel.c           | 74 +++++++++++++--------------
 arch/x86/kernel/cpu/microcode/intel.c |  2 +-
 arch/x86/kernel/cpu/mtrr/generic.c    |  4 +-
 arch/x86/kernel/smpboot.c             | 17 +++---
 arch/x86/mm/pat/memtype.c             |  6 +--
 11 files changed, 93 insertions(+), 92 deletions(-)

-- 
2.43.0

On 2/19/2025 10:41 AM, Sohil Mehta wrote:
> ---Summary---
> Mainstream Intel processors have been using Family 6 for a couple of decades.
> This series is an audit of all the arch/x86 Intel Family-model checks to get
> ready for the upcoming Family 18 and 19 models. It also converts the last
> reamaining Intel x86_model checks to VFM ones.
> 
> Patch 1-8 : Include Dave Hansen's Acked-by.
> Patch 9-15: Almost ready to merge but don't have review tags yet.
> 

Is there any additional feedback?

Most patches have review tags now or are simple enough that they might
not need one. Patch 11 can probably use another look.

Patch 14 is the only one that has a minor change. Seeking additional
input before spinning another revision.

> ---v3 changes---
> * Reordered the patches and moved the Acked ones to the front since they are
>   likely to get applied sooner.
> * Patches 11 and 14 have a slightly different approach now. 
> * Improved commit messages overall.
> * Dropped the drivers/ fixes. Will post them separately.
> 
> ---Previous versions---
> Refer the v2 cover letter for more background.
> 
> v2: https://lore.kernel.org/lkml/20250211194407.2577252-1-sohil.mehta@intel.com/
> RFC-v1: https://lore.kernel.org/lkml/20241220213711.1892696-1-sohil.mehta@intel.com/
> 
> Sohil Mehta (15):
>   x86/apic: Fix 32-bit APIC initialization for extended Intel Families
>   x86/cpu/intel: Fix the movsl alignment preference for extended
>     Families
>   x86/microcode: Update the Intel processor flag scan check
>   x86/mtrr: Modify a x86_model check to an Intel VFM check
>   x86/cpu/intel: Replace early Family 6 checks with VFM ones
>   x86/cpu/intel: Replace Family 15 checks with VFM ones
>   x86/cpu/intel: Replace Family 5 model checks with VFM ones
>   x86/acpi/cstate: Improve Intel Family model checks
>   x86/smpboot: Remove confusing quirk usage in INIT delay
>   x86/smpboot: Fix INIT delay assignment for extended Intel Families
>   x86/cpu/intel: Fix fast string initialization for extended Families
>   x86/pat: Replace Intel x86_model checks with VFM ones
>   x86/cpu/intel: Bound the non-architectural constant_tsc model checks
>   perf/x86: Simplify Intel PMU initialization
>   perf/x86/p4: Replace Pentium 4 model checks with VFM ones
>

* Sohil Mehta <sohil.mehta@intel.com> wrote:

> On 2/19/2025 10:41 AM, Sohil Mehta wrote:
> > ---Summary---
> > Mainstream Intel processors have been using Family 6 for a couple of decades.
> > This series is an audit of all the arch/x86 Intel Family-model checks to get
> > ready for the upcoming Family 18 and 19 models. It also converts the last
> > reamaining Intel x86_model checks to VFM ones.
> > 
> > Patch 1-8 : Include Dave Hansen's Acked-by.
> > Patch 9-15: Almost ready to merge but don't have review tags yet.
> > 
> 
> Is there any additional feedback?

Looks mostly good to me.

> Most patches have review tags now or are simple enough that they might
> not need one. Patch 11 can probably use another look.

LGTM, but I've extended the Cc: list to make more people aware.

(I did the same for some of the other patches that could use extra eyes.)

> Patch 14 is the only one that has a minor change. Seeking additional
> input before spinning another revision.

I've applied the first 13 patches to tip:x86/cpu to help move this 
along. I fixed a handful of typos, but haven't noticed any functional 
problems so far, so unless there's problems in -next this might be OK
for the merge window. (Famous last words.)

Thanks,

	Ingo

On 3/18/2025 11:35 AM, Ingo Molnar wrote:

>> Most patches have review tags now or are simple enough that they might
>> not need one. Patch 11 can probably use another look.
> 
> LGTM, but I've extended the Cc: list to make more people aware.
> 
> (I did the same for some of the other patches that could use extra eyes.)
> 

Appreciate it.

>> Patch 14 is the only one that has a minor change. Seeking additional
>> input before spinning another revision.
> 
> I've applied the first 13 patches to tip:x86/cpu to help move this 
> along. I fixed a handful of typos, but haven't noticed any functional 
> problems so far, so unless there's problems in -next this might be OK
> for the merge window. (Famous last words.)
> 

Many thanks.. Fingers crossed!

-Sohil

* Sohil Mehta <sohil.mehta@intel.com> wrote:

> > I've applied the first 13 patches to tip:x86/cpu to help move this 
> > along. I fixed a handful of typos, but haven't noticed any 
> > functional problems so far, so unless there's problems in -next 
> > this might be OK for the merge window. (Famous last words.)
> > 
> 
> Many thanks.. Fingers crossed!

You are welcome, and please send the remaining patches in a day or so, 
on top of tip:x86/cpu.

Thanks,

	Ingo

On 3/18/2025 1:13 PM, Ingo Molnar wrote:
> 
> * Sohil Mehta <sohil.mehta@intel.com> wrote:
> 
>>> I've applied the first 13 patches to tip:x86/cpu to help move this 
>>> along. I fixed a handful of typos, but haven't noticed any 
>>> functional problems so far, so unless there's problems in -next 
>>> this might be OK for the merge window. (Famous last words.)
>>>
>>
>> Many thanks.. Fingers crossed!
> 
> You are welcome, and please send the remaining patches in a day or so, 
> on top of tip:x86/cpu.
> 

Sent the v4 series with the couple of leftover patches. When sent, the
patches were based on tip:x86/cpu, but that seems to have been merged
into x86/core. I have verified that patches apply cleanly on updated
tip:x86/core as well.

Sohil

* Sohil Mehta <sohil.mehta@intel.com> wrote:

> On 3/18/2025 1:13 PM, Ingo Molnar wrote:
> > 
> > * Sohil Mehta <sohil.mehta@intel.com> wrote:
> > 
> >>> I've applied the first 13 patches to tip:x86/cpu to help move this 
> >>> along. I fixed a handful of typos, but haven't noticed any 
> >>> functional problems so far, so unless there's problems in -next 
> >>> this might be OK for the merge window. (Famous last words.)
> >>>
> >>
> >> Many thanks.. Fingers crossed!
> > 
> > You are welcome, and please send the remaining patches in a day or so, 
> > on top of tip:x86/cpu.
> > 
> 
> Sent the v4 series with the couple of leftover patches. When sent, the
> patches were based on tip:x86/cpu, but that seems to have been merged
> into x86/core.

Correct, we had to back out a broken patch, and a rebase of a number of 
patches, including yours, was the cleanest option. It should be the 
same tree content-wise.

> I have verified that patches apply cleanly on updated tip:x86/core as 
> well.

Thank you!

	Ingo