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[RESEND PATCH] clk: socfpga: clk-pll: Optimize local variables

Thorsten Blum posted 1 patch 9 months, 4 weeks ago 
drivers/clk/socfpga/clk-pll.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
[RESEND PATCH] clk: socfpga: clk-pll: Optimize local variables
Posted by Thorsten Blum 9 months, 4 weeks ago 
Since readl() returns a u32, the local variables reg and bypass can also
have the data type u32. Furthermore, divf and divq are derived from reg
and can also be a u32.

Since do_div() casts the divisor to u32 anyway, changing the data type
of divq to u32 removes the following Coccinelle/coccicheck warning
reported by do_div.cocci:

  WARNING: do_div() does a 64-by-32 division, please consider using div64_ul instead

Compile-tested only.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Thorsten Blum <thorsten.blum@linux.dev>
---
 drivers/clk/socfpga/clk-pll.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/socfpga/clk-pll.c b/drivers/clk/socfpga/clk-pll.c
index 9dcc1b2d2cc0..03a96139a576 100644
--- a/drivers/clk/socfpga/clk-pll.c
+++ b/drivers/clk/socfpga/clk-pll.c
@@ -39,9 +39,9 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk,
 					 unsigned long parent_rate)
 {
 	struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
-	unsigned long divf, divq, reg;
+	u32 divf, divq, reg;
 	unsigned long long vco_freq;
-	unsigned long bypass;
+	u32 bypass;
 
 	reg = readl(socfpgaclk->hw.reg);
 	bypass = readl(clk_mgr_base_addr + CLKMGR_BYPASS);
-- 
2.48.1
Re: [RESEND PATCH] clk: socfpga: clk-pll: Optimize local variables
Posted by Dinh Nguyen 9 months, 4 weeks ago 
On 2/19/25 04:42, Thorsten Blum wrote:
> Since readl() returns a u32, the local variables reg and bypass can also
> have the data type u32. Furthermore, divf and divq are derived from reg
> and can also be a u32.
> 
> Since do_div() casts the divisor to u32 anyway, changing the data type
> of divq to u32 removes the following Coccinelle/coccicheck warning
> reported by do_div.cocci:
> 
>    WARNING: do_div() does a 64-by-32 division, please consider using div64_ul instead
> 
> Compile-tested only.
> 
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Signed-off-by: Thorsten Blum <thorsten.blum@linux.dev>
> ---
>   drivers/clk/socfpga/clk-pll.c | 4 ++--

Applied!

Thanks,
Dinh
Re: [RESEND PATCH] clk: socfpga: clk-pll: Optimize local variables
Posted by Thorsten Blum 8 months, 1 week ago 
Hi Dinh,

On 19. Feb 2025, at 13:42, Dinh Nguyen wrote:
> On 2/19/25 04:42, Thorsten Blum wrote:
>> Since readl() returns a u32, the local variables reg and bypass can also
>> have the data type u32. Furthermore, divf and divq are derived from reg
>> and can also be a u32.
>> Since do_div() casts the divisor to u32 anyway, changing the data type
>> of divq to u32 removes the following Coccinelle/coccicheck warning
>> reported by do_div.cocci:
>>  WARNING: do_div() does a 64-by-32 division, please consider using div64_ul instead
>> Compile-tested only.
>> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>> Signed-off-by: Thorsten Blum <thorsten.blum@linux.dev>
>> ---
>> drivers/clk/socfpga/clk-pll.c | 4 ++--
> 
> Applied!

Did this patch and [*] get lost somehow?

They aren't in -next and also didn't make it into the last merge window.

Thanks,
Thorsten

[*] https://lore.kernel.org/lkml/20250219104435.1525-2-thorsten.blum@linux.dev/
Re: [RESEND PATCH] clk: socfpga: clk-pll: Optimize local variables
Posted by Thorsten Blum 7 months, 3 weeks ago 
On 8. Apr 2025, at 19:45, Thorsten Blum wrote:
> On 19. Feb 2025, at 13:42, Dinh Nguyen wrote:
>> On 2/19/25 04:42, Thorsten Blum wrote:
>>> Since readl() returns a u32, the local variables reg and bypass can also
>>> have the data type u32. Furthermore, divf and divq are derived from reg
>>> and can also be a u32.
>>> Since do_div() casts the divisor to u32 anyway, changing the data type
>>> of divq to u32 removes the following Coccinelle/coccicheck warning
>>> reported by do_div.cocci:
>>> WARNING: do_div() does a 64-by-32 division, please consider using div64_ul instead
>>> Compile-tested only.
>>> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>>> Signed-off-by: Thorsten Blum <thorsten.blum@linux.dev>
>>> ---
>>> drivers/clk/socfpga/clk-pll.c | 4 ++--
>> 
>> Applied!
> 
> Did this patch and [*] get lost somehow?
> 
> They aren't in -next and also didn't make it into the last merge window.

Does anybody else know what happened or where I could find them?

Thanks,
Thorsten

> [*] https://lore.kernel.org/lkml/20250219104435.1525-2-thorsten.blum@linux.dev/
Re: [RESEND PATCH] clk: socfpga: clk-pll: Optimize local variables
Posted by Dinh Nguyen 7 months, 3 weeks ago 
On 4/22/25 07:22, Thorsten Blum wrote:
> On 8. Apr 2025, at 19:45, Thorsten Blum wrote:
>> On 19. Feb 2025, at 13:42, Dinh Nguyen wrote:
>>> On 2/19/25 04:42, Thorsten Blum wrote:
>>>> Since readl() returns a u32, the local variables reg and bypass can also
>>>> have the data type u32. Furthermore, divf and divq are derived from reg
>>>> and can also be a u32.
>>>> Since do_div() casts the divisor to u32 anyway, changing the data type
>>>> of divq to u32 removes the following Coccinelle/coccicheck warning
>>>> reported by do_div.cocci:
>>>> WARNING: do_div() does a 64-by-32 division, please consider using div64_ul instead
>>>> Compile-tested only.
>>>> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>>>> Signed-off-by: Thorsten Blum <thorsten.blum@linux.dev>
>>>> ---
>>>> drivers/clk/socfpga/clk-pll.c | 4 ++--
>>>
>>> Applied!
>>
>> Did this patch and [*] get lost somehow?
>>
>> They aren't in -next and also didn't make it into the last merge window.
> 
> Does anybody else know what happened or where I could find them?
> 

This is my bad. I missed the merge window for the PR. I'll resend it 
this time.

Dinh

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