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[PATCH v7 6/7] arm64: dts: agilex: add dts enabling PCIe Root Port

Matthew Gerlach posted 7 patches 10 months, 1 week ago
Only 6 patches received!
There is a newer version of this series
[PATCH v7 6/7] arm64: dts: agilex: add dts enabling PCIe Root Port
Posted by Matthew Gerlach 10 months, 1 week ago 
Add a device tree enabling PCIe Root Port support on an Agilex F-series
Development Kit which has the P-tile variant of the PCIe IP.

Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
---
v7:
 - Create and use appropriate board compatibility and use of model.

v6:
 - Fix SPDX header.
 - Make compatible property first.
 - Fix comment line wrapping.
 - Don't include .dts.

v3:
 - Remove accepted patches from patch set.
---
 arch/arm64/boot/dts/intel/Makefile            |   1 +
 .../socfpga_agilex7f_socdk_pcie_root_port.dts | 147 ++++++++++++++++++
 2 files changed, 148 insertions(+)
 create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex7f_socdk_pcie_root_port.dts

diff --git a/arch/arm64/boot/dts/intel/Makefile b/arch/arm64/boot/dts/intel/Makefile
index d39cfb723f5b..737e81c3c3f7 100644
--- a/arch/arm64/boot/dts/intel/Makefile
+++ b/arch/arm64/boot/dts/intel/Makefile
@@ -2,6 +2,7 @@
 dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_agilex_n6000.dtb \
 				socfpga_agilex_socdk.dtb \
 				socfpga_agilex_socdk_nand.dtb \
+				socfpga_agilex7f_socdk_pcie_root_port.dtb \
 				socfpga_agilex5_socdk.dtb \
 				socfpga_n5x_socdk.dtb
 dtb-$(CONFIG_ARCH_KEEMBAY) += keembay-evm.dtb
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex7f_socdk_pcie_root_port.dts b/arch/arm64/boot/dts/intel/socfpga_agilex7f_socdk_pcie_root_port.dts
new file mode 100644
index 000000000000..19b14f88e32d
--- /dev/null
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex7f_socdk_pcie_root_port.dts
@@ -0,0 +1,147 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2024, Intel Corporation
+ */
+#include "socfpga_agilex.dtsi"
+#include "socfpga_agilex_pcie_root_port.dtsi"
+
+/ {
+	model = "SoCFPGA Agilex SoCDK";
+	compatible = "intel,socfpga-agilex7f-socdk-pcie-root-port", "intel,socfpga-agilex";
+
+	aliases {
+		serial0 = &uart0;
+		ethernet0 = &gmac0;
+		ethernet1 = &gmac1;
+		ethernet2 = &gmac2;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		led0 {
+			label = "hps_led0";
+			gpios = <&portb 20 GPIO_ACTIVE_HIGH>;
+		};
+
+		led1 {
+			label = "hps_led1";
+			gpios = <&portb 19 GPIO_ACTIVE_HIGH>;
+		};
+
+		led2 {
+			label = "hps_led2";
+			gpios = <&portb 21 GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		/* We expect the bootloader to fill in the reg */
+		reg = <0 0x80000000 0 0>;
+	};
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&gmac0 {
+	status = "okay";
+	phy-mode = "rgmii";
+	phy-handle = <&phy0>;
+
+	max-frame-size = <9000>;
+
+	mdio0 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "snps,dwmac-mdio";
+		phy0: ethernet-phy@0 {
+			reg = <4>;
+
+			txd0-skew-ps = <0>; /* -420ps */
+			txd1-skew-ps = <0>; /* -420ps */
+			txd2-skew-ps = <0>; /* -420ps */
+			txd3-skew-ps = <0>; /* -420ps */
+			rxd0-skew-ps = <420>; /* 0ps */
+			rxd1-skew-ps = <420>; /* 0ps */
+			rxd2-skew-ps = <420>; /* 0ps */
+			rxd3-skew-ps = <420>; /* 0ps */
+			txen-skew-ps = <0>; /* -420ps */
+			txc-skew-ps = <900>; /* 0ps */
+			rxdv-skew-ps = <420>; /* 0ps */
+			rxc-skew-ps = <1680>; /* 780ps */
+		};
+	};
+};
+
+&mmc {
+	status = "okay";
+	cap-sd-highspeed;
+	broken-cd;
+	bus-width = <4>;
+	clk-phase-sd-hs = <0>, <135>;
+};
+
+&osc1 {
+	clock-frequency = <25000000>;
+	status = "okay";
+};
+
+&pcie_0_msi_irq {
+	status = "okay";
+};
+
+&pcie_0_pcie_aglx {
+	compatible = "altr,pcie-root-port-3.0-p-tile";
+	status = "okay";
+};
+
+&qspi {
+	status = "okay";
+	flash@0 {
+		compatible = "micron,mt25qu02g", "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <100000000>;
+
+		m25p,fast-read;
+		cdns,read-delay = <2>;
+		cdns,tshsl-ns = <50>;
+		cdns,tsd2d-ns = <50>;
+		cdns,tchsh-ns = <4>;
+		cdns,tslch-ns = <4>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			qspi_boot: partition@0 {
+				label = "Boot and fpga data";
+				reg = <0x0 0x04200000>;
+			};
+
+			root: partition@4200000 {
+				label = "Root Filesystem - UBIFS";
+				reg = <0x04200000 0x0BE00000>;
+			};
+		};
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&usb0 {
+	status = "okay";
+	disable-over-current;
+};
+
+&watchdog0 {
+	status = "okay";
+};
-- 
2.34.1
Re: [PATCH v7 6/7] arm64: dts: agilex: add dts enabling PCIe Root Port
Posted by Krzysztof Kozlowski 10 months ago 
On Sat, Feb 15, 2025 at 09:53:58AM -0600, Matthew Gerlach wrote:
> Add a device tree enabling PCIe Root Port support on an Agilex F-series
> Development Kit which has the P-tile variant of the PCIe IP.
> 
> Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
> ---
> v7:
>  - Create and use appropriate board compatibility and use of model.
> 
> v6:
>  - Fix SPDX header.
>  - Make compatible property first.
>  - Fix comment line wrapping.
>  - Don't include .dts.
> 
> v3:
>  - Remove accepted patches from patch set.
> ---
>  arch/arm64/boot/dts/intel/Makefile            |   1 +
>  .../socfpga_agilex7f_socdk_pcie_root_port.dts | 147 ++++++++++++++++++
>  2 files changed, 148 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex7f_socdk_pcie_root_port.dts
> 
> diff --git a/arch/arm64/boot/dts/intel/Makefile b/arch/arm64/boot/dts/intel/Makefile
> index d39cfb723f5b..737e81c3c3f7 100644
> --- a/arch/arm64/boot/dts/intel/Makefile
> +++ b/arch/arm64/boot/dts/intel/Makefile
> @@ -2,6 +2,7 @@
>  dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_agilex_n6000.dtb \
>  				socfpga_agilex_socdk.dtb \
>  				socfpga_agilex_socdk_nand.dtb \
> +				socfpga_agilex7f_socdk_pcie_root_port.dtb \
>  				socfpga_agilex5_socdk.dtb \
>  				socfpga_n5x_socdk.dtb
>  dtb-$(CONFIG_ARCH_KEEMBAY) += keembay-evm.dtb
> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex7f_socdk_pcie_root_port.dts b/arch/arm64/boot/dts/intel/socfpga_agilex7f_socdk_pcie_root_port.dts
> new file mode 100644
> index 000000000000..19b14f88e32d
> --- /dev/null
> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex7f_socdk_pcie_root_port.dts
> @@ -0,0 +1,147 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2024, Intel Corporation
> + */
> +#include "socfpga_agilex.dtsi"
> +#include "socfpga_agilex_pcie_root_port.dtsi"
> +
> +/ {
> +	model = "SoCFPGA Agilex SoCDK";
> +	compatible = "intel,socfpga-agilex7f-socdk-pcie-root-port", "intel,socfpga-agilex";

So that's different SoC (Agilex F series)? Why isn't this expressed in
compatibles? Is it different or the same board? If different, why
"root-port" in board name? Is this how the product is named?

Best regards,
Krzysztof
Re: [PATCH v7 6/7] arm64: dts: agilex: add dts enabling PCIe Root Port
Posted by matthew.gerlach@linux.intel.com 10 months ago 

On Sun, 16 Feb 2025, Krzysztof Kozlowski wrote:

> On Sat, Feb 15, 2025 at 09:53:58AM -0600, Matthew Gerlach wrote:
>> Add a device tree enabling PCIe Root Port support on an Agilex F-series
>> Development Kit which has the P-tile variant of the PCIe IP.
>>
>> Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
>> ---
>> v7:
>>  - Create and use appropriate board compatibility and use of model.
>>
>> v6:
>>  - Fix SPDX header.
>>  - Make compatible property first.
>>  - Fix comment line wrapping.
>>  - Don't include .dts.
>>
>> v3:
>>  - Remove accepted patches from patch set.
>> ---
>>  arch/arm64/boot/dts/intel/Makefile            |   1 +
>>  .../socfpga_agilex7f_socdk_pcie_root_port.dts | 147 ++++++++++++++++++
>>  2 files changed, 148 insertions(+)
>>  create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex7f_socdk_pcie_root_port.dts
>>
>> diff --git a/arch/arm64/boot/dts/intel/Makefile b/arch/arm64/boot/dts/intel/Makefile
>> index d39cfb723f5b..737e81c3c3f7 100644
>> --- a/arch/arm64/boot/dts/intel/Makefile
>> +++ b/arch/arm64/boot/dts/intel/Makefile
>> @@ -2,6 +2,7 @@
>>  dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_agilex_n6000.dtb \
>>  				socfpga_agilex_socdk.dtb \
>>  				socfpga_agilex_socdk_nand.dtb \
>> +				socfpga_agilex7f_socdk_pcie_root_port.dtb \
>>  				socfpga_agilex5_socdk.dtb \
>>  				socfpga_n5x_socdk.dtb
>>  dtb-$(CONFIG_ARCH_KEEMBAY) += keembay-evm.dtb
>> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex7f_socdk_pcie_root_port.dts b/arch/arm64/boot/dts/intel/socfpga_agilex7f_socdk_pcie_root_port.dts
>> new file mode 100644
>> index 000000000000..19b14f88e32d
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex7f_socdk_pcie_root_port.dts
>> @@ -0,0 +1,147 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Copyright (C) 2024, Intel Corporation
>> + */
>> +#include "socfpga_agilex.dtsi"
>> +#include "socfpga_agilex_pcie_root_port.dtsi"
>> +
>> +/ {
>> +	model = "SoCFPGA Agilex SoCDK";
>> +	compatible = "intel,socfpga-agilex7f-socdk-pcie-root-port", "intel,socfpga-agilex";
>
> So that's different SoC (Agilex F series)? Why isn't this expressed in
What was formally known as Agilex is now more precisely referred Agilex 7 
F series, Agilex 7 I series, or Agilex 7 M series. Yes, this should me 
reflected in the compatibles.

> compatibles? Is it different or the same board? If different, why
> "root-port" in board name? Is this how the product is named?

"root-port" refers to a particular board combined with a specific FPGA 
image and possibly a daughter card and cables. I am not sure that FPGA 
image specific DTS or DTSI should be in the kernel tree.

>
> Best regards,
> Krzysztof
>
>

Thanks for the feedback,
Matthew Gerlach

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