All Agilex SoCs have the fixed-clocks defined in socfpga_agilex.dsti,
but the board specific DTS determines which fixed-clocks are actually
used and at what frequency. Fix the schema check warning about fixed-clock
nodes requiring a clock-frequency by disabling all the fixed-clocks in the
DTSI and enabling clocks used by a board in the board specific DTS.

Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
---
v7:
 - Disable fixed-clock in DTSI instead of setting clock-frequency = <0>;

v6:
 - New patch to series
---
 arch/arm64/boot/dts/intel/socfpga_agilex.dtsi           | 4 ++++
 arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts      | 1 +
 arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts      | 1 +
 arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dts | 1 +
 4 files changed, 7 insertions(+)

diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
index 1235ba5a9865..202b4404577e 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
@@ -114,21 +114,25 @@ clocks {
 		cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {
 			#clock-cells = <0>;
 			compatible = "fixed-clock";
+			status = "disabled";
 		};
 
 		cb_intosc_ls_clk: cb-intosc-ls-clk {
 			#clock-cells = <0>;
 			compatible = "fixed-clock";
+			status = "disabled";
 		};
 
 		f2s_free_clk: f2s-free-clk {
 			#clock-cells = <0>;
 			compatible = "fixed-clock";
+			status = "disabled";
 		};
 
 		osc1: osc1 {
 			#clock-cells = <0>;
 			compatible = "fixed-clock";
+			status = "disabled";
 		};
 
 		qspi_clk: qspi-clk {
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts
index d22de06e9839..55f825c5245f 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts
@@ -47,6 +47,7 @@ dma-controller@0 {
 
 &osc1 {
 	clock-frequency = <25000000>;
+	status = "okay";
 };
 
 &uart0 {
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts
index b31cfa6b802d..3337b19836af 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts
@@ -88,6 +88,7 @@ &mmc {
 
 &osc1 {
 	clock-frequency = <25000000>;
+	status = "okay";
 };
 
 &uart0 {
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dts
index 0f9020bd0c52..40be9eb41aab 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dts
@@ -100,6 +100,7 @@ partition@200000 {
 
 &osc1 {
 	clock-frequency = <25000000>;
+	status = "okay";
 };
 
 &uart0 {
-- 
2.34.1

On Sat, Feb 15, 2025 at 09:53:55AM -0600, Matthew Gerlach wrote:
> All Agilex SoCs have the fixed-clocks defined in socfpga_agilex.dsti,


That's not what I asked / talked about. If the clocks are in SoC, they
cannot be disabled.

If they clocks are not in SoC, they should not be in DTSI.

These were my statements last time and this patch does not comple.
Commit msg does not explain why this should be done differently.

Best regards,
Krzysztof

On Sun, 16 Feb 2025, Krzysztof Kozlowski wrote:

> On Sat, Feb 15, 2025 at 09:53:55AM -0600, Matthew Gerlach wrote:
>> All Agilex SoCs have the fixed-clocks defined in socfpga_agilex.dsti,
>
>
> That's not what I asked / talked about. If the clocks are in SoC, they
> cannot be disabled.

There are two clocks, cb_intoosc_hs_div2_clk and cb_intosc_ls_clk, in the 
SoC with a known frequency. These warnings can be fixed in the DTSI.

>
> If they clocks are not in SoC, they should not be in DTSI.

The two clocks, f2s_free_clk and osc1, are not in the SoC; so they should 
be removed from DTSI.

>
> These were my statements last time and this patch does not comple.
> Commit msg does not explain why this should be done differently.
>
> Best regards,
> Krzysztof
>
>

Thanks for the feedback,
Matthew Gerlach

On Tue, 18 Feb 2025, matthew.gerlach@linux.intel.com wrote:

>
>
> On Sun, 16 Feb 2025, Krzysztof Kozlowski wrote:
>
>> On Sat, Feb 15, 2025 at 09:53:55AM -0600, Matthew Gerlach wrote:
>>> All Agilex SoCs have the fixed-clocks defined in socfpga_agilex.dsti,
>> 
>> 
>> That's not what I asked / talked about. If the clocks are in SoC, they
>> cannot be disabled.
>
> There are two clocks, cb_intoosc_hs_div2_clk and cb_intosc_ls_clk, in the SoC 
> with a known frequency. These warnings can be fixed in the DTSI.
>
>> 
>> If they clocks are not in SoC, they should not be in DTSI.
>
> The two clocks, f2s_free_clk and osc1, are not in the SoC; so they should be 
> removed from DTSI.

Since these clock changes are not directly related to adding PCIe Root 
Port support to Agilex chips, I think they should be in their patch set.

Matthew Gerlach

>
>> 
>> These were my statements last time and this patch does not comple.
>> Commit msg does not explain why this should be done differently.
>> 
>> Best regards,
>> Krzysztof
>> 
>> 
>
> Thanks for the feedback,
> Matthew Gerlach
>