On Fri, Feb 14, 2025 at 06:52:32PM -0600, Mario Limonciello wrote:
> From: Mario Limonciello <mario.limonciello@amd.com>
>
> The `cppc_cap1_cached` variable isn't used at all, there is no
> need to read it at initialization for each CPU.
>
> Reviewed-by: Dhananjay Ugwekar <dhananjay.ugwekar@amd.com>
> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Thanks for this cleanup.
Reviewed-by: Gautham R. Shenoy <gautham.shenoy@amd.com>
--
Thanks and Regards
gautham.
> ---
> drivers/cpufreq/amd-pstate.c | 5 -----
> drivers/cpufreq/amd-pstate.h | 2 --
> 2 files changed, 7 deletions(-)
>
> diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c
> index 044091806f14f..e5983e5c77ba2 100644
> --- a/drivers/cpufreq/amd-pstate.c
> +++ b/drivers/cpufreq/amd-pstate.c
> @@ -1510,11 +1510,6 @@ static int amd_pstate_epp_cpu_init(struct cpufreq_policy *policy)
> if (ret)
> return ret;
> WRITE_ONCE(cpudata->cppc_req_cached, value);
> -
> - ret = rdmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_CAP1, &value);
> - if (ret)
> - return ret;
> - WRITE_ONCE(cpudata->cppc_cap1_cached, value);
> }
> ret = amd_pstate_set_epp(cpudata, cpudata->epp_default);
> if (ret)
> diff --git a/drivers/cpufreq/amd-pstate.h b/drivers/cpufreq/amd-pstate.h
> index 8421c83c07919..1a52582dbac9d 100644
> --- a/drivers/cpufreq/amd-pstate.h
> +++ b/drivers/cpufreq/amd-pstate.h
> @@ -74,7 +74,6 @@ struct amd_aperf_mperf {
> * AMD P-State driver supports preferred core featue.
> * @epp_cached: Cached CPPC energy-performance preference value
> * @policy: Cpufreq policy value
> - * @cppc_cap1_cached Cached MSR_AMD_CPPC_CAP1 register value
> *
> * The amd_cpudata is key private data for each CPU thread in AMD P-State, and
> * represents all the attributes and goals that AMD P-State requests at runtime.
> @@ -103,7 +102,6 @@ struct amd_cpudata {
> /* EPP feature related attributes*/
> u8 epp_cached;
> u32 policy;
> - u64 cppc_cap1_cached;
> bool suspended;
> u8 epp_default;
> };
> --
> 2.43.0
>