During the GDSC FSM state, the GDSC hardware waits for an ACK from the
respective subsystem core. In some scenarios, this ACK can be delayed.
To handle such delays, increase the GDSC status poll timeout from 1500us
to 2000us as per the design recommendation.

Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
---
 drivers/clk/qcom/gdsc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c
index 1fd40b755082a4658cca581e920635e1bdfbc922..2e3128ed16c4d78f1bca799b4e716e9034b4a6b9 100644
--- a/drivers/clk/qcom/gdsc.c
+++ b/drivers/clk/qcom/gdsc.c
@@ -46,7 +46,7 @@
 #define RETAIN_MEM		BIT(14)
 #define RETAIN_PERIPH		BIT(13)
 
-#define STATUS_POLL_TIMEOUT_US	1500
+#define STATUS_POLL_TIMEOUT_US	2000
 #define TIMEOUT_US		500
 
 #define domain_to_gdsc(domain) container_of(domain, struct gdsc, pd)

-- 
2.48.1

On 2/14/2025 9:57 AM, Taniya Das wrote:
> During the GDSC FSM state, the GDSC hardware waits for an ACK from the
> respective subsystem core. In some scenarios, this ACK can be delayed.
> To handle such delays, increase the GDSC status poll timeout from 1500us
> to 2000us as per the design recommendation.
> 
> Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
> ---
>  drivers/clk/qcom/gdsc.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 

Reviewed-by: Imran Shaik <quic_imrashai@quicinc.com>
Tested-by: Imran Shaik <quic_imrashai@quicinc.com> # on QCS8300