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[RESEND PATCH 0/7] perf vendor events riscv: Update SiFive CPU PMU events

Samuel Holland posted 7 patches 10 months, 1 week ago 
tools/perf/pmu-events/arch/riscv/mapfile.csv  |  6 +-
.../cycle-and-instruction-count.json          | 12 +++
.../arch/riscv/sifive/bullet-07/firmware.json |  1 +
.../riscv/sifive/bullet-07/instruction.json   |  1 +
.../arch/riscv/sifive/bullet-07/memory.json   |  1 +
.../riscv/sifive/bullet-07/microarch.json     | 62 +++++++++++++
.../riscv/sifive/bullet-07/watchpoint.json    | 42 +++++++++
.../cycle-and-instruction-count.json          |  1 +
.../arch/riscv/sifive/bullet-0d/firmware.json |  1 +
.../riscv/sifive/bullet-0d/instruction.json   |  1 +
.../arch/riscv/sifive/bullet-0d/memory.json   |  1 +
.../riscv/sifive/bullet-0d/microarch.json     | 72 +++++++++++++++
.../riscv/sifive/bullet-0d/watchpoint.json    |  1 +
.../sifive/{u74 => bullet}/firmware.json      |  0
.../arch/riscv/sifive/bullet/instruction.json | 92 +++++++++++++++++++
.../arch/riscv/sifive/bullet/memory.json      | 32 +++++++
.../arch/riscv/sifive/bullet/microarch.json   | 57 ++++++++++++
.../arch/riscv/sifive/p550/firmware.json      |  1 +
.../arch/riscv/sifive/p550/instruction.json   |  1 +
.../arch/riscv/sifive/p550/memory.json        | 47 ++++++++++
.../arch/riscv/sifive/p550/microarch.json     |  1 +
.../p650/cycle-and-instruction-count.json     |  1 +
.../arch/riscv/sifive/p650/firmware.json      |  1 +
.../arch/riscv/sifive/p650/instruction.json   |  1 +
.../arch/riscv/sifive/p650/memory.json        | 57 ++++++++++++
.../arch/riscv/sifive/p650/microarch.json     | 62 +++++++++++++
.../arch/riscv/sifive/p650/watchpoint.json    |  1 +
.../arch/riscv/sifive/u74/instructions.json   | 92 -------------------
.../arch/riscv/sifive/u74/memory.json         | 32 -------
.../arch/riscv/sifive/u74/microarch.json      | 57 ------------
30 files changed, 555 insertions(+), 182 deletions(-)
create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/cycle-and-instruction-count.json
create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/firmware.json
create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/instruction.json
create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/memory.json
create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/microarch.json
create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/watchpoint.json
create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/cycle-and-instruction-count.json
create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/firmware.json
create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/instruction.json
create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/memory.json
create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/microarch.json
create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/watchpoint.json
rename tools/perf/pmu-events/arch/riscv/sifive/{u74 => bullet}/firmware.json (100%)
create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet/instruction.json
create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet/memory.json
create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet/microarch.json
create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p550/firmware.json
create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p550/instruction.json
create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/p550/memory.json
create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p550/microarch.json
create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p650/cycle-and-instruction-count.json
create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p650/firmware.json
create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p650/instruction.json
create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/p650/memory.json
create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/p650/microarch.json
create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p650/watchpoint.json
delete mode 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/instructions.json
delete mode 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/memory.json
delete mode 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/microarch.json
[RESEND PATCH 0/7] perf vendor events riscv: Update SiFive CPU PMU events
Posted by Samuel Holland 10 months, 1 week ago 
This series updates the PMU event JSON files to add support for newer
SiFive CPUs, including those used in the HiFive Premier P550 board.
Since most changes are incremental, symbolic links are used when a set
of events is unchanged from the previous CPU series.

I originally sent this series about a year ago[1], but received no
feedback. The P550 board is now available (and I have tested this series
on it), so it would be good to get perf support for it upstream.

[1]: https://lore.kernel.org/linux-perf-users/20240509021531.680920-1-samuel.holland@sifive.com/


Eric Lin (5):
  perf vendor events riscv: Update SiFive Bullet events
  perf vendor events riscv: Add SiFive Bullet version 0x07 events
  perf vendor events riscv: Add SiFive Bullet version 0x0d events
  perf vendor events riscv: Add SiFive P550 events
  perf vendor events riscv: Add SiFive P650 events

Samuel Holland (2):
  perf vendor events riscv: Rename U74 to Bullet
  perf vendor events riscv: Remove leading zeroes

 tools/perf/pmu-events/arch/riscv/mapfile.csv  |  6 +-
 .../cycle-and-instruction-count.json          | 12 +++
 .../arch/riscv/sifive/bullet-07/firmware.json |  1 +
 .../riscv/sifive/bullet-07/instruction.json   |  1 +
 .../arch/riscv/sifive/bullet-07/memory.json   |  1 +
 .../riscv/sifive/bullet-07/microarch.json     | 62 +++++++++++++
 .../riscv/sifive/bullet-07/watchpoint.json    | 42 +++++++++
 .../cycle-and-instruction-count.json          |  1 +
 .../arch/riscv/sifive/bullet-0d/firmware.json |  1 +
 .../riscv/sifive/bullet-0d/instruction.json   |  1 +
 .../arch/riscv/sifive/bullet-0d/memory.json   |  1 +
 .../riscv/sifive/bullet-0d/microarch.json     | 72 +++++++++++++++
 .../riscv/sifive/bullet-0d/watchpoint.json    |  1 +
 .../sifive/{u74 => bullet}/firmware.json      |  0
 .../arch/riscv/sifive/bullet/instruction.json | 92 +++++++++++++++++++
 .../arch/riscv/sifive/bullet/memory.json      | 32 +++++++
 .../arch/riscv/sifive/bullet/microarch.json   | 57 ++++++++++++
 .../arch/riscv/sifive/p550/firmware.json      |  1 +
 .../arch/riscv/sifive/p550/instruction.json   |  1 +
 .../arch/riscv/sifive/p550/memory.json        | 47 ++++++++++
 .../arch/riscv/sifive/p550/microarch.json     |  1 +
 .../p650/cycle-and-instruction-count.json     |  1 +
 .../arch/riscv/sifive/p650/firmware.json      |  1 +
 .../arch/riscv/sifive/p650/instruction.json   |  1 +
 .../arch/riscv/sifive/p650/memory.json        | 57 ++++++++++++
 .../arch/riscv/sifive/p650/microarch.json     | 62 +++++++++++++
 .../arch/riscv/sifive/p650/watchpoint.json    |  1 +
 .../arch/riscv/sifive/u74/instructions.json   | 92 -------------------
 .../arch/riscv/sifive/u74/memory.json         | 32 -------
 .../arch/riscv/sifive/u74/microarch.json      | 57 ------------
 30 files changed, 555 insertions(+), 182 deletions(-)
 create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/cycle-and-instruction-count.json
 create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/firmware.json
 create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/instruction.json
 create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/memory.json
 create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/microarch.json
 create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/watchpoint.json
 create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/cycle-and-instruction-count.json
 create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/firmware.json
 create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/instruction.json
 create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/memory.json
 create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/microarch.json
 create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/watchpoint.json
 rename tools/perf/pmu-events/arch/riscv/sifive/{u74 => bullet}/firmware.json (100%)
 create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet/instruction.json
 create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet/memory.json
 create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet/microarch.json
 create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p550/firmware.json
 create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p550/instruction.json
 create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/p550/memory.json
 create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p550/microarch.json
 create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p650/cycle-and-instruction-count.json
 create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p650/firmware.json
 create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p650/instruction.json
 create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/p650/memory.json
 create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/p650/microarch.json
 create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p650/watchpoint.json
 delete mode 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/instructions.json
 delete mode 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/memory.json
 delete mode 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/microarch.json

-- 
2.47.0
Re: [RESEND PATCH 0/7] perf vendor events riscv: Update SiFive CPU PMU events
Posted by Namhyung Kim 10 months ago 
Hello,

On Wed, Feb 12, 2025 at 05:21:33PM -0800, Samuel Holland wrote:
> This series updates the PMU event JSON files to add support for newer
> SiFive CPUs, including those used in the HiFive Premier P550 board.
> Since most changes are incremental, symbolic links are used when a set
> of events is unchanged from the previous CPU series.
> 
> I originally sent this series about a year ago[1], but received no
> feedback. The P550 board is now available (and I have tested this series
> on it), so it would be good to get perf support for it upstream.
> 
> [1]: https://lore.kernel.org/linux-perf-users/20240509021531.680920-1-samuel.holland@sifive.com/
> 
> 
> Eric Lin (5):
>   perf vendor events riscv: Update SiFive Bullet events
>   perf vendor events riscv: Add SiFive Bullet version 0x07 events
>   perf vendor events riscv: Add SiFive Bullet version 0x0d events
>   perf vendor events riscv: Add SiFive P550 events
>   perf vendor events riscv: Add SiFive P650 events
> 
> Samuel Holland (2):
>   perf vendor events riscv: Rename U74 to Bullet
>   perf vendor events riscv: Remove leading zeroes

It'd be nice if anyone in the RISC-V community can review this.

Thanks,
Namhyung

> 
>  tools/perf/pmu-events/arch/riscv/mapfile.csv  |  6 +-
>  .../cycle-and-instruction-count.json          | 12 +++
>  .../arch/riscv/sifive/bullet-07/firmware.json |  1 +
>  .../riscv/sifive/bullet-07/instruction.json   |  1 +
>  .../arch/riscv/sifive/bullet-07/memory.json   |  1 +
>  .../riscv/sifive/bullet-07/microarch.json     | 62 +++++++++++++
>  .../riscv/sifive/bullet-07/watchpoint.json    | 42 +++++++++
>  .../cycle-and-instruction-count.json          |  1 +
>  .../arch/riscv/sifive/bullet-0d/firmware.json |  1 +
>  .../riscv/sifive/bullet-0d/instruction.json   |  1 +
>  .../arch/riscv/sifive/bullet-0d/memory.json   |  1 +
>  .../riscv/sifive/bullet-0d/microarch.json     | 72 +++++++++++++++
>  .../riscv/sifive/bullet-0d/watchpoint.json    |  1 +
>  .../sifive/{u74 => bullet}/firmware.json      |  0
>  .../arch/riscv/sifive/bullet/instruction.json | 92 +++++++++++++++++++
>  .../arch/riscv/sifive/bullet/memory.json      | 32 +++++++
>  .../arch/riscv/sifive/bullet/microarch.json   | 57 ++++++++++++
>  .../arch/riscv/sifive/p550/firmware.json      |  1 +
>  .../arch/riscv/sifive/p550/instruction.json   |  1 +
>  .../arch/riscv/sifive/p550/memory.json        | 47 ++++++++++
>  .../arch/riscv/sifive/p550/microarch.json     |  1 +
>  .../p650/cycle-and-instruction-count.json     |  1 +
>  .../arch/riscv/sifive/p650/firmware.json      |  1 +
>  .../arch/riscv/sifive/p650/instruction.json   |  1 +
>  .../arch/riscv/sifive/p650/memory.json        | 57 ++++++++++++
>  .../arch/riscv/sifive/p650/microarch.json     | 62 +++++++++++++
>  .../arch/riscv/sifive/p650/watchpoint.json    |  1 +
>  .../arch/riscv/sifive/u74/instructions.json   | 92 -------------------
>  .../arch/riscv/sifive/u74/memory.json         | 32 -------
>  .../arch/riscv/sifive/u74/microarch.json      | 57 ------------
>  30 files changed, 555 insertions(+), 182 deletions(-)
>  create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/cycle-and-instruction-count.json
>  create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/firmware.json
>  create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/instruction.json
>  create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/memory.json
>  create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/microarch.json
>  create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/watchpoint.json
>  create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/cycle-and-instruction-count.json
>  create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/firmware.json
>  create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/instruction.json
>  create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/memory.json
>  create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/microarch.json
>  create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/watchpoint.json
>  rename tools/perf/pmu-events/arch/riscv/sifive/{u74 => bullet}/firmware.json (100%)
>  create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet/instruction.json
>  create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet/memory.json
>  create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet/microarch.json
>  create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p550/firmware.json
>  create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p550/instruction.json
>  create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/p550/memory.json
>  create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p550/microarch.json
>  create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p650/cycle-and-instruction-count.json
>  create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p650/firmware.json
>  create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p650/instruction.json
>  create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/p650/memory.json
>  create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/p650/microarch.json
>  create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p650/watchpoint.json
>  delete mode 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/instructions.json
>  delete mode 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/memory.json
>  delete mode 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/microarch.json
> 
> -- 
> 2.47.0
>
Re: [RESEND PATCH 0/7] perf vendor events riscv: Update SiFive CPU PMU events
Posted by Atish Patra 9 months, 3 weeks ago 
On Wed, Feb 19, 2025 at 1:27 PM Namhyung Kim <namhyung@kernel.org> wrote:
>
> Hello,
>
> On Wed, Feb 12, 2025 at 05:21:33PM -0800, Samuel Holland wrote:
> > This series updates the PMU event JSON files to add support for newer
> > SiFive CPUs, including those used in the HiFive Premier P550 board.
> > Since most changes are incremental, symbolic links are used when a set
> > of events is unchanged from the previous CPU series.
> >
> > I originally sent this series about a year ago[1], but received no
> > feedback. The P550 board is now available (and I have tested this series
> > on it), so it would be good to get perf support for it upstream.
> >
> > [1]: https://lore.kernel.org/linux-perf-users/20240509021531.680920-1-samuel.holland@sifive.com/
> >

Tested the patches that are part of sifive's release tree for p550.
Both perf stat/record seems to work fine
for a bunch of events.

Based on that
Tested-by: Atish Patra <atishp@rivosinc.com>

@Samuel Holland : perf report that the following two events are not
supported on the p550 board.

cycle and instruction count:
  core_clock_cycles
       [Counts core clock cycles]
  instructions_retired
       [Counts instructions retired]

I assumed that these are raw events cycle/instruction retired events
that can support
perf sampling as well. Maybe I am missing something ? DT binding ?

> >
> > Eric Lin (5):
> >   perf vendor events riscv: Update SiFive Bullet events
> >   perf vendor events riscv: Add SiFive Bullet version 0x07 events
> >   perf vendor events riscv: Add SiFive Bullet version 0x0d events
> >   perf vendor events riscv: Add SiFive P550 events
> >   perf vendor events riscv: Add SiFive P650 events
> >
> > Samuel Holland (2):
> >   perf vendor events riscv: Rename U74 to Bullet
> >   perf vendor events riscv: Remove leading zeroes
>
> It'd be nice if anyone in the RISC-V community can review this.
>
> Thanks,
> Namhyung
>
> >
> >  tools/perf/pmu-events/arch/riscv/mapfile.csv  |  6 +-
> >  .../cycle-and-instruction-count.json          | 12 +++
> >  .../arch/riscv/sifive/bullet-07/firmware.json |  1 +
> >  .../riscv/sifive/bullet-07/instruction.json   |  1 +
> >  .../arch/riscv/sifive/bullet-07/memory.json   |  1 +
> >  .../riscv/sifive/bullet-07/microarch.json     | 62 +++++++++++++
> >  .../riscv/sifive/bullet-07/watchpoint.json    | 42 +++++++++
> >  .../cycle-and-instruction-count.json          |  1 +
> >  .../arch/riscv/sifive/bullet-0d/firmware.json |  1 +
> >  .../riscv/sifive/bullet-0d/instruction.json   |  1 +
> >  .../arch/riscv/sifive/bullet-0d/memory.json   |  1 +
> >  .../riscv/sifive/bullet-0d/microarch.json     | 72 +++++++++++++++
> >  .../riscv/sifive/bullet-0d/watchpoint.json    |  1 +
> >  .../sifive/{u74 => bullet}/firmware.json      |  0
> >  .../arch/riscv/sifive/bullet/instruction.json | 92 +++++++++++++++++++
> >  .../arch/riscv/sifive/bullet/memory.json      | 32 +++++++
> >  .../arch/riscv/sifive/bullet/microarch.json   | 57 ++++++++++++
> >  .../arch/riscv/sifive/p550/firmware.json      |  1 +
> >  .../arch/riscv/sifive/p550/instruction.json   |  1 +
> >  .../arch/riscv/sifive/p550/memory.json        | 47 ++++++++++
> >  .../arch/riscv/sifive/p550/microarch.json     |  1 +
> >  .../p650/cycle-and-instruction-count.json     |  1 +
> >  .../arch/riscv/sifive/p650/firmware.json      |  1 +
> >  .../arch/riscv/sifive/p650/instruction.json   |  1 +
> >  .../arch/riscv/sifive/p650/memory.json        | 57 ++++++++++++
> >  .../arch/riscv/sifive/p650/microarch.json     | 62 +++++++++++++
> >  .../arch/riscv/sifive/p650/watchpoint.json    |  1 +
> >  .../arch/riscv/sifive/u74/instructions.json   | 92 -------------------
> >  .../arch/riscv/sifive/u74/memory.json         | 32 -------
> >  .../arch/riscv/sifive/u74/microarch.json      | 57 ------------
> >  30 files changed, 555 insertions(+), 182 deletions(-)
> >  create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/cycle-and-instruction-count.json
> >  create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/firmware.json
> >  create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/instruction.json
> >  create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/memory.json
> >  create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/microarch.json
> >  create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/watchpoint.json
> >  create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/cycle-and-instruction-count.json
> >  create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/firmware.json
> >  create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/instruction.json
> >  create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/memory.json
> >  create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/microarch.json
> >  create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/watchpoint.json
> >  rename tools/perf/pmu-events/arch/riscv/sifive/{u74 => bullet}/firmware.json (100%)
> >  create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet/instruction.json
> >  create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet/memory.json
> >  create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet/microarch.json
> >  create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p550/firmware.json
> >  create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p550/instruction.json
> >  create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/p550/memory.json
> >  create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p550/microarch.json
> >  create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p650/cycle-and-instruction-count.json
> >  create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p650/firmware.json
> >  create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p650/instruction.json
> >  create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/p650/memory.json
> >  create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/p650/microarch.json
> >  create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p650/watchpoint.json
> >  delete mode 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/instructions.json
> >  delete mode 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/memory.json
> >  delete mode 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/microarch.json
> >
> > --
> > 2.47.0
> >
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv



--
Regards,
Atish
Re: [RESEND PATCH 0/7] perf vendor events riscv: Update SiFive CPU PMU events
Posted by Samuel Holland 9 months, 2 weeks ago 
Hi Atish,

On 2025-03-01 3:21 AM, Atish Patra wrote:
> On Wed, Feb 19, 2025 at 1:27 PM Namhyung Kim <namhyung@kernel.org> wrote:
>>
>> Hello,
>>
>> On Wed, Feb 12, 2025 at 05:21:33PM -0800, Samuel Holland wrote:
>>> This series updates the PMU event JSON files to add support for newer
>>> SiFive CPUs, including those used in the HiFive Premier P550 board.
>>> Since most changes are incremental, symbolic links are used when a set
>>> of events is unchanged from the previous CPU series.
>>>
>>> I originally sent this series about a year ago[1], but received no
>>> feedback. The P550 board is now available (and I have tested this series
>>> on it), so it would be good to get perf support for it upstream.
>>>
>>> [1]: https://lore.kernel.org/linux-perf-users/20240509021531.680920-1-samuel.holland@sifive.com/
>>>
> 
> Tested the patches that are part of sifive's release tree for p550.
> Both perf stat/record seems to work fine
> for a bunch of events.
> 
> Based on that
> Tested-by: Atish Patra <atishp@rivosinc.com>

Thanks for testing!

> @Samuel Holland : perf report that the following two events are not
> supported on the p550 board.
> 
> cycle and instruction count:
>   core_clock_cycles
>        [Counts core clock cycles]
>   instructions_retired
>        [Counts instructions retired]
> 
> I assumed that these are raw events cycle/instruction retired events
> that can support
> perf sampling as well. Maybe I am missing something ? DT binding ?

perf is correct. Those two events are not supported on P550, only by the newer
cores (bulled-0d and p650). Yes, those are aliases of cycles and instructions
that were added to support sampling.

Regards,
Samuel

>>>
>>> Eric Lin (5):
>>>   perf vendor events riscv: Update SiFive Bullet events
>>>   perf vendor events riscv: Add SiFive Bullet version 0x07 events
>>>   perf vendor events riscv: Add SiFive Bullet version 0x0d events
>>>   perf vendor events riscv: Add SiFive P550 events
>>>   perf vendor events riscv: Add SiFive P650 events
>>>
>>> Samuel Holland (2):
>>>   perf vendor events riscv: Rename U74 to Bullet
>>>   perf vendor events riscv: Remove leading zeroes
>>
>> It'd be nice if anyone in the RISC-V community can review this.
>>
>> Thanks,
>> Namhyung
>>
>>>
>>>  tools/perf/pmu-events/arch/riscv/mapfile.csv  |  6 +-
>>>  .../cycle-and-instruction-count.json          | 12 +++
>>>  .../arch/riscv/sifive/bullet-07/firmware.json |  1 +
>>>  .../riscv/sifive/bullet-07/instruction.json   |  1 +
>>>  .../arch/riscv/sifive/bullet-07/memory.json   |  1 +
>>>  .../riscv/sifive/bullet-07/microarch.json     | 62 +++++++++++++
>>>  .../riscv/sifive/bullet-07/watchpoint.json    | 42 +++++++++
>>>  .../cycle-and-instruction-count.json          |  1 +
>>>  .../arch/riscv/sifive/bullet-0d/firmware.json |  1 +
>>>  .../riscv/sifive/bullet-0d/instruction.json   |  1 +
>>>  .../arch/riscv/sifive/bullet-0d/memory.json   |  1 +
>>>  .../riscv/sifive/bullet-0d/microarch.json     | 72 +++++++++++++++
>>>  .../riscv/sifive/bullet-0d/watchpoint.json    |  1 +
>>>  .../sifive/{u74 => bullet}/firmware.json      |  0
>>>  .../arch/riscv/sifive/bullet/instruction.json | 92 +++++++++++++++++++
>>>  .../arch/riscv/sifive/bullet/memory.json      | 32 +++++++
>>>  .../arch/riscv/sifive/bullet/microarch.json   | 57 ++++++++++++
>>>  .../arch/riscv/sifive/p550/firmware.json      |  1 +
>>>  .../arch/riscv/sifive/p550/instruction.json   |  1 +
>>>  .../arch/riscv/sifive/p550/memory.json        | 47 ++++++++++
>>>  .../arch/riscv/sifive/p550/microarch.json     |  1 +
>>>  .../p650/cycle-and-instruction-count.json     |  1 +
>>>  .../arch/riscv/sifive/p650/firmware.json      |  1 +
>>>  .../arch/riscv/sifive/p650/instruction.json   |  1 +
>>>  .../arch/riscv/sifive/p650/memory.json        | 57 ++++++++++++
>>>  .../arch/riscv/sifive/p650/microarch.json     | 62 +++++++++++++
>>>  .../arch/riscv/sifive/p650/watchpoint.json    |  1 +
>>>  .../arch/riscv/sifive/u74/instructions.json   | 92 -------------------
>>>  .../arch/riscv/sifive/u74/memory.json         | 32 -------
>>>  .../arch/riscv/sifive/u74/microarch.json      | 57 ------------
>>>  30 files changed, 555 insertions(+), 182 deletions(-)
>>>  create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/cycle-and-instruction-count.json
>>>  create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/firmware.json
>>>  create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/instruction.json
>>>  create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/memory.json
>>>  create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/microarch.json
>>>  create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/watchpoint.json
>>>  create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/cycle-and-instruction-count.json
>>>  create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/firmware.json
>>>  create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/instruction.json
>>>  create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/memory.json
>>>  create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/microarch.json
>>>  create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/watchpoint.json
>>>  rename tools/perf/pmu-events/arch/riscv/sifive/{u74 => bullet}/firmware.json (100%)
>>>  create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet/instruction.json
>>>  create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet/memory.json
>>>  create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet/microarch.json
>>>  create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p550/firmware.json
>>>  create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p550/instruction.json
>>>  create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/p550/memory.json
>>>  create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p550/microarch.json
>>>  create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p650/cycle-and-instruction-count.json
>>>  create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p650/firmware.json
>>>  create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p650/instruction.json
>>>  create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/p650/memory.json
>>>  create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/p650/microarch.json
>>>  create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p650/watchpoint.json
>>>  delete mode 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/instructions.json
>>>  delete mode 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/memory.json
>>>  delete mode 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/microarch.json
>>>
>>> --
>>> 2.47.0
>>>
>>
>> _______________________________________________
>> linux-riscv mailing list
>> linux-riscv@lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-riscv
> 
> 
> 
> --
> Regards,
> Atish
Re: [RESEND PATCH 0/7] perf vendor events riscv: Update SiFive CPU PMU events
Posted by Atish Patra 9 months ago 
On Fri, Mar 7, 2025 at 1:19 AM Samuel Holland <samuel.holland@sifive.com> wrote:
>
> Hi Atish,
>
> On 2025-03-01 3:21 AM, Atish Patra wrote:
> > On Wed, Feb 19, 2025 at 1:27 PM Namhyung Kim <namhyung@kernel.org> wrote:
> >>
> >> Hello,
> >>
> >> On Wed, Feb 12, 2025 at 05:21:33PM -0800, Samuel Holland wrote:
> >>> This series updates the PMU event JSON files to add support for newer
> >>> SiFive CPUs, including those used in the HiFive Premier P550 board.
> >>> Since most changes are incremental, symbolic links are used when a set
> >>> of events is unchanged from the previous CPU series.
> >>>
> >>> I originally sent this series about a year ago[1], but received no
> >>> feedback. The P550 board is now available (and I have tested this series
> >>> on it), so it would be good to get perf support for it upstream.
> >>>
> >>> [1]: https://lore.kernel.org/linux-perf-users/20240509021531.680920-1-samuel.holland@sifive.com/
> >>>
> >
> > Tested the patches that are part of sifive's release tree for p550.
> > Both perf stat/record seems to work fine
> > for a bunch of events.
> >
> > Based on that
> > Tested-by: Atish Patra <atishp@rivosinc.com>
>
> Thanks for testing!
>
> > @Samuel Holland : perf report that the following two events are not
> > supported on the p550 board.
> >
> > cycle and instruction count:
> >   core_clock_cycles
> >        [Counts core clock cycles]
> >   instructions_retired
> >        [Counts instructions retired]
> >
> > I assumed that these are raw events cycle/instruction retired events
> > that can support
> > perf sampling as well. Maybe I am missing something ? DT binding ?
>
> perf is correct. Those two events are not supported on P550, only by the newer
> cores (bulled-0d and p650). Yes, those are aliases of cycles and instructions
> that were added to support sampling.
>

Thanks for the confirmation. Are there other events that can be used to sample
instruction count on P550 ? I did not find anything in the perf list
or the json file.
I am not sure if I missed something.

> Regards,
> Samuel
>
> >>>
> >>> Eric Lin (5):
> >>>   perf vendor events riscv: Update SiFive Bullet events
> >>>   perf vendor events riscv: Add SiFive Bullet version 0x07 events
> >>>   perf vendor events riscv: Add SiFive Bullet version 0x0d events
> >>>   perf vendor events riscv: Add SiFive P550 events
> >>>   perf vendor events riscv: Add SiFive P650 events
> >>>
> >>> Samuel Holland (2):
> >>>   perf vendor events riscv: Rename U74 to Bullet
> >>>   perf vendor events riscv: Remove leading zeroes
> >>
> >> It'd be nice if anyone in the RISC-V community can review this.
> >>
> >> Thanks,
> >> Namhyung
> >>
> >>>
> >>>  tools/perf/pmu-events/arch/riscv/mapfile.csv  |  6 +-
> >>>  .../cycle-and-instruction-count.json          | 12 +++
> >>>  .../arch/riscv/sifive/bullet-07/firmware.json |  1 +
> >>>  .../riscv/sifive/bullet-07/instruction.json   |  1 +
> >>>  .../arch/riscv/sifive/bullet-07/memory.json   |  1 +
> >>>  .../riscv/sifive/bullet-07/microarch.json     | 62 +++++++++++++
> >>>  .../riscv/sifive/bullet-07/watchpoint.json    | 42 +++++++++
> >>>  .../cycle-and-instruction-count.json          |  1 +
> >>>  .../arch/riscv/sifive/bullet-0d/firmware.json |  1 +
> >>>  .../riscv/sifive/bullet-0d/instruction.json   |  1 +
> >>>  .../arch/riscv/sifive/bullet-0d/memory.json   |  1 +
> >>>  .../riscv/sifive/bullet-0d/microarch.json     | 72 +++++++++++++++
> >>>  .../riscv/sifive/bullet-0d/watchpoint.json    |  1 +
> >>>  .../sifive/{u74 => bullet}/firmware.json      |  0
> >>>  .../arch/riscv/sifive/bullet/instruction.json | 92 +++++++++++++++++++
> >>>  .../arch/riscv/sifive/bullet/memory.json      | 32 +++++++
> >>>  .../arch/riscv/sifive/bullet/microarch.json   | 57 ++++++++++++
> >>>  .../arch/riscv/sifive/p550/firmware.json      |  1 +
> >>>  .../arch/riscv/sifive/p550/instruction.json   |  1 +
> >>>  .../arch/riscv/sifive/p550/memory.json        | 47 ++++++++++
> >>>  .../arch/riscv/sifive/p550/microarch.json     |  1 +
> >>>  .../p650/cycle-and-instruction-count.json     |  1 +
> >>>  .../arch/riscv/sifive/p650/firmware.json      |  1 +
> >>>  .../arch/riscv/sifive/p650/instruction.json   |  1 +
> >>>  .../arch/riscv/sifive/p650/memory.json        | 57 ++++++++++++
> >>>  .../arch/riscv/sifive/p650/microarch.json     | 62 +++++++++++++
> >>>  .../arch/riscv/sifive/p650/watchpoint.json    |  1 +
> >>>  .../arch/riscv/sifive/u74/instructions.json   | 92 -------------------
> >>>  .../arch/riscv/sifive/u74/memory.json         | 32 -------
> >>>  .../arch/riscv/sifive/u74/microarch.json      | 57 ------------
> >>>  30 files changed, 555 insertions(+), 182 deletions(-)
> >>>  create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/cycle-and-instruction-count.json
> >>>  create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/firmware.json
> >>>  create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/instruction.json
> >>>  create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/memory.json
> >>>  create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/microarch.json
> >>>  create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/watchpoint.json
> >>>  create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/cycle-and-instruction-count.json
> >>>  create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/firmware.json
> >>>  create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/instruction.json
> >>>  create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/memory.json
> >>>  create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/microarch.json
> >>>  create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/watchpoint.json
> >>>  rename tools/perf/pmu-events/arch/riscv/sifive/{u74 => bullet}/firmware.json (100%)
> >>>  create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet/instruction.json
> >>>  create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet/memory.json
> >>>  create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet/microarch.json
> >>>  create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p550/firmware.json
> >>>  create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p550/instruction.json
> >>>  create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/p550/memory.json
> >>>  create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p550/microarch.json
> >>>  create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p650/cycle-and-instruction-count.json
> >>>  create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p650/firmware.json
> >>>  create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p650/instruction.json
> >>>  create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/p650/memory.json
> >>>  create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/p650/microarch.json
> >>>  create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p650/watchpoint.json
> >>>  delete mode 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/instructions.json
> >>>  delete mode 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/memory.json
> >>>  delete mode 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/microarch.json
> >>>
> >>> --
> >>> 2.47.0
> >>>
> >>
> >> _______________________________________________
> >> linux-riscv mailing list
> >> linux-riscv@lists.infradead.org
> >> http://lists.infradead.org/mailman/listinfo/linux-riscv
> >
> >
> >
> > --
> > Regards,
> > Atish
>


-- 
Regards,
Atish
Re: [RESEND PATCH 0/7] perf vendor events riscv: Update SiFive CPU PMU events
Posted by Samuel Holland 9 months ago 
Hi Atish,

On 2025-03-21 1:31 PM, Atish Patra wrote:
> On Fri, Mar 7, 2025 at 1:19 AM Samuel Holland <samuel.holland@sifive.com> wrote:
>> On 2025-03-01 3:21 AM, Atish Patra wrote:
>>> On Wed, Feb 19, 2025 at 1:27 PM Namhyung Kim <namhyung@kernel.org> wrote:
>>>> On Wed, Feb 12, 2025 at 05:21:33PM -0800, Samuel Holland wrote:
>>>>> This series updates the PMU event JSON files to add support for newer
>>>>> SiFive CPUs, including those used in the HiFive Premier P550 board.
>>>>> Since most changes are incremental, symbolic links are used when a set
>>>>> of events is unchanged from the previous CPU series.
>>>>>
>>>>> I originally sent this series about a year ago[1], but received no
>>>>> feedback. The P550 board is now available (and I have tested this series
>>>>> on it), so it would be good to get perf support for it upstream.
>>>>>
>>>>> [1]: https://lore.kernel.org/linux-perf-users/20240509021531.680920-1-samuel.holland@sifive.com/
>>>>>
>>>
>>> Tested the patches that are part of sifive's release tree for p550.
>>> Both perf stat/record seems to work fine
>>> for a bunch of events.
>>>
>>> Based on that
>>> Tested-by: Atish Patra <atishp@rivosinc.com>
>>
>> Thanks for testing!
>>
>>> @Samuel Holland : perf report that the following two events are not
>>> supported on the p550 board.
>>>
>>> cycle and instruction count:
>>>   core_clock_cycles
>>>        [Counts core clock cycles]
>>>   instructions_retired
>>>        [Counts instructions retired]
>>>
>>> I assumed that these are raw events cycle/instruction retired events
>>> that can support
>>> perf sampling as well. Maybe I am missing something ? DT binding ?
>>
>> perf is correct. Those two events are not supported on P550, only by the newer
>> cores (bulled-0d and p650). Yes, those are aliases of cycles and instructions
>> that were added to support sampling.
>>
> 
> Thanks for the confirmation. Are there other events that can be used to sample
> instruction count on P550 ? I did not find anything in the perf list
> or the json file.
> I am not sure if I missed something.

Likely the closest approximation is ORing together the instruction class
retirement events from instruction.json: cpu/r0x3fffe00/. The difference between
that and "instructions" looks to be well within 1% for CPU-intensive workloads.
Maybe it makes sense to add an entry for this combination in the JSON? Would it
be appropriate to call it "instructions_retired"? The same thing could be done
for the older SiFive cores.

Regards,
Samuel
Re: [RESEND PATCH 0/7] perf vendor events riscv: Update SiFive CPU PMU events
Posted by Ian Rogers 10 months ago 
On Wed, Feb 19, 2025 at 1:20 PM Namhyung Kim <namhyung@kernel.org> wrote:
>
> Hello,
>
> On Wed, Feb 12, 2025 at 05:21:33PM -0800, Samuel Holland wrote:
> > This series updates the PMU event JSON files to add support for newer
> > SiFive CPUs, including those used in the HiFive Premier P550 board.
> > Since most changes are incremental, symbolic links are used when a set
> > of events is unchanged from the previous CPU series.
> >
> > I originally sent this series about a year ago[1], but received no
> > feedback. The P550 board is now available (and I have tested this series
> > on it), so it would be good to get perf support for it upstream.
> >
> > [1]: https://lore.kernel.org/linux-perf-users/20240509021531.680920-1-samuel.holland@sifive.com/
> >
> >
> > Eric Lin (5):
> >   perf vendor events riscv: Update SiFive Bullet events
> >   perf vendor events riscv: Add SiFive Bullet version 0x07 events
> >   perf vendor events riscv: Add SiFive Bullet version 0x0d events
> >   perf vendor events riscv: Add SiFive P550 events
> >   perf vendor events riscv: Add SiFive P650 events
> >
> > Samuel Holland (2):
> >   perf vendor events riscv: Rename U74 to Bullet
> >   perf vendor events riscv: Remove leading zeroes
>
> It'd be nice if anyone in the RISC-V community can review this.

I can add a:
Tested-by: Ian Rogers <irogers@google.com>
tag, for testing with a build with JEVENTS_ARCH=all on an x86.

The changes use symlinks but generally we've not done this for Intel.
I'm not sure this matters and didn't see mention in the style guide.

The model naming and events are all coming from SiFive so I trust
they're happy with it, I didn't spot anything glaringly wrong.
Reviewed-by: Ian Rogers <irogers@google.com>

Thanks,
Ian


> Thanks,
> Namhyung
>
> >
> >  tools/perf/pmu-events/arch/riscv/mapfile.csv  |  6 +-
> >  .../cycle-and-instruction-count.json          | 12 +++
> >  .../arch/riscv/sifive/bullet-07/firmware.json |  1 +
> >  .../riscv/sifive/bullet-07/instruction.json   |  1 +
> >  .../arch/riscv/sifive/bullet-07/memory.json   |  1 +
> >  .../riscv/sifive/bullet-07/microarch.json     | 62 +++++++++++++
> >  .../riscv/sifive/bullet-07/watchpoint.json    | 42 +++++++++
> >  .../cycle-and-instruction-count.json          |  1 +
> >  .../arch/riscv/sifive/bullet-0d/firmware.json |  1 +
> >  .../riscv/sifive/bullet-0d/instruction.json   |  1 +
> >  .../arch/riscv/sifive/bullet-0d/memory.json   |  1 +
> >  .../riscv/sifive/bullet-0d/microarch.json     | 72 +++++++++++++++
> >  .../riscv/sifive/bullet-0d/watchpoint.json    |  1 +
> >  .../sifive/{u74 => bullet}/firmware.json      |  0
> >  .../arch/riscv/sifive/bullet/instruction.json | 92 +++++++++++++++++++
> >  .../arch/riscv/sifive/bullet/memory.json      | 32 +++++++
> >  .../arch/riscv/sifive/bullet/microarch.json   | 57 ++++++++++++
> >  .../arch/riscv/sifive/p550/firmware.json      |  1 +
> >  .../arch/riscv/sifive/p550/instruction.json   |  1 +
> >  .../arch/riscv/sifive/p550/memory.json        | 47 ++++++++++
> >  .../arch/riscv/sifive/p550/microarch.json     |  1 +
> >  .../p650/cycle-and-instruction-count.json     |  1 +
> >  .../arch/riscv/sifive/p650/firmware.json      |  1 +
> >  .../arch/riscv/sifive/p650/instruction.json   |  1 +
> >  .../arch/riscv/sifive/p650/memory.json        | 57 ++++++++++++
> >  .../arch/riscv/sifive/p650/microarch.json     | 62 +++++++++++++
> >  .../arch/riscv/sifive/p650/watchpoint.json    |  1 +
> >  .../arch/riscv/sifive/u74/instructions.json   | 92 -------------------
> >  .../arch/riscv/sifive/u74/memory.json         | 32 -------
> >  .../arch/riscv/sifive/u74/microarch.json      | 57 ------------
> >  30 files changed, 555 insertions(+), 182 deletions(-)
> >  create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/cycle-and-instruction-count.json
> >  create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/firmware.json
> >  create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/instruction.json
> >  create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/memory.json
> >  create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/microarch.json
> >  create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/watchpoint.json
> >  create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/cycle-and-instruction-count.json
> >  create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/firmware.json
> >  create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/instruction.json
> >  create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/memory.json
> >  create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/microarch.json
> >  create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/watchpoint.json
> >  rename tools/perf/pmu-events/arch/riscv/sifive/{u74 => bullet}/firmware.json (100%)
> >  create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet/instruction.json
> >  create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet/memory.json
> >  create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet/microarch.json
> >  create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p550/firmware.json
> >  create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p550/instruction.json
> >  create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/p550/memory.json
> >  create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p550/microarch.json
> >  create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p650/cycle-and-instruction-count.json
> >  create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p650/firmware.json
> >  create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p650/instruction.json
> >  create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/p650/memory.json
> >  create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/p650/microarch.json
> >  create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p650/watchpoint.json
> >  delete mode 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/instructions.json
> >  delete mode 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/memory.json
> >  delete mode 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/microarch.json
> >
> > --
> > 2.47.0
> >
Re: [RESEND PATCH 0/7] perf vendor events riscv: Update SiFive CPU PMU events
Posted by Namhyung Kim 9 months, 1 week ago 
On Wed, 12 Feb 2025 17:21:33 -0800, Samuel Holland wrote:
> This series updates the PMU event JSON files to add support for newer
> SiFive CPUs, including those used in the HiFive Premier P550 board.
> Since most changes are incremental, symbolic links are used when a set
> of events is unchanged from the previous CPU series.
> 
> I originally sent this series about a year ago[1], but received no
> feedback. The P550 board is now available (and I have tested this series
> on it), so it would be good to get perf support for it upstream.
> 
> [...]
Applied to perf-tools-next, thanks!

Best regards,
Namhyung

Patchew 2.1-devel-b67e4c2

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