The intermediate hash values generated during an update task were
handled incorrectly in the driver. The values have a defined format for
each algorithm. Copying and pasting from the HASH_RESULT register
balantly would not work for all the supported algorithms. This incorrect
handling causes failures when there is a context switch between multiple
operations.
To handle the expected format correctly, add a separate buffer for
storing the intermediate results for each request. Remove the previous
copy/paste functions which read/wrote to the registers directly. Instead
configure the hardware to get the intermediate result copied to the
buffer and use host1x path to restore the intermediate hash results.
Fixes: 0880bb3b00c8 ("crypto: tegra - Add Tegra Security Engine driver")
Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
---
drivers/crypto/tegra/tegra-se-hash.c | 148 +++++++++++++++++----------
drivers/crypto/tegra/tegra-se.h | 1 +
2 files changed, 97 insertions(+), 52 deletions(-)
diff --git a/drivers/crypto/tegra/tegra-se-hash.c b/drivers/crypto/tegra/tegra-se-hash.c
index 6da18f0f7ce9..89c1e1a0016b 100644
--- a/drivers/crypto/tegra/tegra-se-hash.c
+++ b/drivers/crypto/tegra/tegra-se-hash.c
@@ -34,6 +34,7 @@ struct tegra_sha_reqctx {
struct tegra_se_datbuf datbuf;
struct tegra_se_datbuf residue;
struct tegra_se_datbuf digest;
+ struct tegra_se_datbuf intr_res;
unsigned int alg;
unsigned int config;
unsigned int total_len;
@@ -211,9 +212,61 @@ static int tegra_sha_fallback_export(struct ahash_request *req, void *out)
return crypto_ahash_export(&rctx->fallback_req, out);
}
-static int tegra_sha_prep_cmd(struct tegra_se *se, u32 *cpuvaddr,
+static int tegra_se_insert_hash_result(struct tegra_sha_ctx *ctx, u32 *cpuvaddr,
struct tegra_sha_reqctx *rctx)
{
+ u32 *res = (u32 *)rctx->intr_res.buf;
+ int i = 0, j;
+
+ cpuvaddr[i++] = 0;
+ cpuvaddr[i++] = host1x_opcode_setpayload(HASH_RESULT_REG_COUNT);
+ cpuvaddr[i++] = se_host1x_opcode_incr_w(SE_SHA_HASH_RESULT);
+
+ for (j = 0; j < HASH_RESULT_REG_COUNT; j++) {
+ int idx = j;
+
+ /*
+ * The initial, intermediate and final hash value of SHA-384, SHA-512
+ * in SHA_HASH_RESULT registers follow the below layout of bytes.
+ *
+ * +---------------+------------+
+ * | HASH_RESULT_0 | B4...B7 |
+ * +---------------+------------+
+ * | HASH_RESULT_1 | B0...B3 |
+ * +---------------+------------+
+ * | HASH_RESULT_2 | B12...B15 |
+ * +---------------+------------+
+ * | HASH_RESULT_3 | B8...B11 |
+ * +---------------+------------+
+ * | ...... |
+ * +---------------+------------+
+ * | HASH_RESULT_14| B60...B63 |
+ * +---------------+------------+
+ * | HASH_RESULT_15| B56...B59 |
+ * +---------------+------------+
+ *
+ */
+ if (ctx->alg == SE_ALG_SHA384 || ctx->alg == SE_ALG_SHA512)
+ idx = (j % 2) ? j - 1 : j + 1;
+
+ /* For SHA-1, SHA-224, SHA-256, SHA-384, SHA-512 the initial
+ * intermediate and final hash value when stored in
+ * SHA_HASH_RESULT registers, the byte order is NOT in
+ * little-endian.
+ */
+ if (ctx->alg <= SE_ALG_SHA512)
+ cpuvaddr[i++] = be32_to_cpu(res[idx]);
+ else
+ cpuvaddr[i++] = res[idx];
+ }
+
+ return i;
+}
+
+static int tegra_sha_prep_cmd(struct tegra_sha_ctx *ctx, u32 *cpuvaddr,
+ struct tegra_sha_reqctx *rctx)
+{
+ struct tegra_se *se = ctx->se;
u64 msg_len, msg_left;
int i = 0;
@@ -241,7 +294,7 @@ static int tegra_sha_prep_cmd(struct tegra_se *se, u32 *cpuvaddr,
cpuvaddr[i++] = upper_32_bits(msg_left);
cpuvaddr[i++] = 0;
cpuvaddr[i++] = 0;
- cpuvaddr[i++] = host1x_opcode_setpayload(6);
+ cpuvaddr[i++] = host1x_opcode_setpayload(2);
cpuvaddr[i++] = se_host1x_opcode_incr_w(SE_SHA_CFG);
cpuvaddr[i++] = rctx->config;
@@ -249,15 +302,29 @@ static int tegra_sha_prep_cmd(struct tegra_se *se, u32 *cpuvaddr,
cpuvaddr[i++] = SE_SHA_TASK_HASH_INIT;
rctx->task &= ~SHA_FIRST;
} else {
- cpuvaddr[i++] = 0;
+ /*
+ * If it isn't the first task, program the HASH_RESULT register
+ * with the intermediate result from the previous task
+ */
+ i += tegra_se_insert_hash_result(ctx, cpuvaddr + i, rctx);
}
+ cpuvaddr[i++] = host1x_opcode_setpayload(4);
+ cpuvaddr[i++] = se_host1x_opcode_incr_w(SE_SHA_IN_ADDR);
cpuvaddr[i++] = rctx->datbuf.addr;
cpuvaddr[i++] = (u32)(SE_ADDR_HI_MSB(upper_32_bits(rctx->datbuf.addr)) |
SE_ADDR_HI_SZ(rctx->datbuf.size));
- cpuvaddr[i++] = rctx->digest.addr;
- cpuvaddr[i++] = (u32)(SE_ADDR_HI_MSB(upper_32_bits(rctx->digest.addr)) |
- SE_ADDR_HI_SZ(rctx->digest.size));
+
+ if (rctx->task & SHA_UPDATE) {
+ cpuvaddr[i++] = rctx->intr_res.addr;
+ cpuvaddr[i++] = (u32)(SE_ADDR_HI_MSB(upper_32_bits(rctx->intr_res.addr)) |
+ SE_ADDR_HI_SZ(rctx->intr_res.size));
+ } else {
+ cpuvaddr[i++] = rctx->digest.addr;
+ cpuvaddr[i++] = (u32)(SE_ADDR_HI_MSB(upper_32_bits(rctx->digest.addr)) |
+ SE_ADDR_HI_SZ(rctx->digest.size));
+ }
+
if (rctx->key_id) {
cpuvaddr[i++] = host1x_opcode_setpayload(1);
cpuvaddr[i++] = se_host1x_opcode_nonincr_w(SE_SHA_CRYPTO_CFG);
@@ -266,36 +333,18 @@ static int tegra_sha_prep_cmd(struct tegra_se *se, u32 *cpuvaddr,
cpuvaddr[i++] = host1x_opcode_setpayload(1);
cpuvaddr[i++] = se_host1x_opcode_nonincr_w(SE_SHA_OPERATION);
- cpuvaddr[i++] = SE_SHA_OP_WRSTALL |
- SE_SHA_OP_START |
+ cpuvaddr[i++] = SE_SHA_OP_WRSTALL | SE_SHA_OP_START |
SE_SHA_OP_LASTBUF;
cpuvaddr[i++] = se_host1x_opcode_nonincr(host1x_uclass_incr_syncpt_r(), 1);
cpuvaddr[i++] = host1x_uclass_incr_syncpt_cond_f(1) |
host1x_uclass_incr_syncpt_indx_f(se->syncpt_id);
- dev_dbg(se->dev, "msg len %llu msg left %llu cfg %#x",
- msg_len, msg_left, rctx->config);
+ dev_dbg(se->dev, "msg len %llu msg left %llu sz %lu cfg %#x",
+ msg_len, msg_left, rctx->datbuf.size, rctx->config);
return i;
}
-static void tegra_sha_copy_hash_result(struct tegra_se *se, struct tegra_sha_reqctx *rctx)
-{
- int i;
-
- for (i = 0; i < HASH_RESULT_REG_COUNT; i++)
- rctx->result[i] = readl(se->base + se->hw->regs->result + (i * 4));
-}
-
-static void tegra_sha_paste_hash_result(struct tegra_se *se, struct tegra_sha_reqctx *rctx)
-{
- int i;
-
- for (i = 0; i < HASH_RESULT_REG_COUNT; i++)
- writel(rctx->result[i],
- se->base + se->hw->regs->result + (i * 4));
-}
-
static int tegra_sha_do_init(struct ahash_request *req)
{
struct tegra_sha_reqctx *rctx = ahash_request_ctx(req);
@@ -325,8 +374,17 @@ static int tegra_sha_do_init(struct ahash_request *req)
if (!rctx->residue.buf)
goto resbuf_fail;
+ rctx->intr_res.size = HASH_RESULT_REG_COUNT * 4;
+ rctx->intr_res.buf = dma_alloc_coherent(se->dev, rctx->intr_res.size,
+ &rctx->intr_res.addr, GFP_KERNEL);
+ if (!rctx->intr_res.buf)
+ goto intr_res_fail;
+
return 0;
+intr_res_fail:
+ dma_free_coherent(se->dev, rctx->residue.size, rctx->residue.buf,
+ rctx->residue.addr);
resbuf_fail:
dma_free_coherent(se->dev, rctx->digest.size, rctx->digest.buf,
rctx->digest.addr);
@@ -356,7 +414,6 @@ static int tegra_sha_do_update(struct ahash_request *req)
rctx->src_sg = req->src;
rctx->datbuf.size = (req->nbytes + rctx->residue.size) - nresidue;
- rctx->total_len += rctx->datbuf.size;
/*
* If nbytes are less than a block size, copy it residue and
@@ -365,12 +422,12 @@ static int tegra_sha_do_update(struct ahash_request *req)
if (nblks < 1) {
scatterwalk_map_and_copy(rctx->residue.buf + rctx->residue.size,
rctx->src_sg, 0, req->nbytes, 0);
-
rctx->residue.size += req->nbytes;
+
return 0;
}
- rctx->datbuf.buf = dma_alloc_coherent(ctx->se->dev, rctx->datbuf.size,
+ rctx->datbuf.buf = dma_alloc_coherent(se->dev, rctx->datbuf.size,
&rctx->datbuf.addr, GFP_KERNEL);
if (!rctx->datbuf.buf)
return -ENOMEM;
@@ -387,31 +444,15 @@ static int tegra_sha_do_update(struct ahash_request *req)
/* Update residue value with the residue after current block */
rctx->residue.size = nresidue;
+ rctx->total_len += rctx->datbuf.size;
rctx->config = tegra_sha_get_config(rctx->alg) |
- SE_SHA_DST_HASH_REG;
-
- /*
- * If this is not the first 'update' call, paste the previous copied
- * intermediate results to the registers so that it gets picked up.
- * This is to support the import/export functionality.
- */
- if (!(rctx->task & SHA_FIRST))
- tegra_sha_paste_hash_result(se, rctx);
-
- size = tegra_sha_prep_cmd(se, cpuvaddr, rctx);
+ SE_SHA_DST_MEMORY;
+ size = tegra_sha_prep_cmd(ctx, cpuvaddr, rctx);
ret = tegra_se_host1x_submit(se, se->cmdbuf, size);
- /*
- * If this is not the final update, copy the intermediate results
- * from the registers so that it can be used in the next 'update'
- * call. This is to support the import/export functionality.
- */
- if (!(rctx->task & SHA_FINAL))
- tegra_sha_copy_hash_result(se, rctx);
-
- dma_free_coherent(ctx->se->dev, rctx->datbuf.size,
+ dma_free_coherent(se->dev, rctx->datbuf.size,
rctx->datbuf.buf, rctx->datbuf.addr);
return ret;
@@ -443,8 +484,7 @@ static int tegra_sha_do_final(struct ahash_request *req)
rctx->config = tegra_sha_get_config(rctx->alg) |
SE_SHA_DST_MEMORY;
- size = tegra_sha_prep_cmd(se, cpuvaddr, rctx);
-
+ size = tegra_sha_prep_cmd(ctx, cpuvaddr, rctx);
ret = tegra_se_host1x_submit(se, se->cmdbuf, size);
if (ret)
goto out;
@@ -461,6 +501,10 @@ static int tegra_sha_do_final(struct ahash_request *req)
rctx->residue.buf, rctx->residue.addr);
dma_free_coherent(se->dev, rctx->digest.size, rctx->digest.buf,
rctx->digest.addr);
+
+ dma_free_coherent(se->dev, rctx->intr_res.size, rctx->intr_res.buf,
+ rctx->intr_res.addr);
+
return ret;
}
diff --git a/drivers/crypto/tegra/tegra-se.h b/drivers/crypto/tegra/tegra-se.h
index e1ec37bfb80a..0f5bcf27358b 100644
--- a/drivers/crypto/tegra/tegra-se.h
+++ b/drivers/crypto/tegra/tegra-se.h
@@ -24,6 +24,7 @@
#define SE_STREAM_ID 0x90
#define SE_SHA_CFG 0x4004
+#define SE_SHA_IN_ADDR 0x400c
#define SE_SHA_KEY_ADDR 0x4094
#define SE_SHA_KEY_DATA 0x4098
#define SE_SHA_KEYMANIFEST 0x409c
--
2.43.2Hi Akhil,
kernel test robot noticed the following build warnings:
[auto build test WARNING on herbert-crypto-2.6/master]
[also build test WARNING on herbert-cryptodev-2.6/master linus/master v6.14-rc2 next-20250212]
[cannot apply to tegra/for-next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Akhil-R/crypto-tegra-Use-separate-buffer-for-setkey/20250212-012434
base: https://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6.git master
patch link: https://lore.kernel.org/r/20250211171713.65770-7-akhilrajeev%40nvidia.com
patch subject: [PATCH v2 06/10] crypto: tegra: Fix HASH intermediate result handling
config: arm-randconfig-004-20250213 (https://download.01.org/0day-ci/archive/20250213/202502131216.RDQlFu1f-lkp@intel.com/config)
compiler: arm-linux-gnueabi-gcc (GCC) 14.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250213/202502131216.RDQlFu1f-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202502131216.RDQlFu1f-lkp@intel.com/
All warnings (new ones prefixed by >>):
In file included from include/linux/device.h:15,
from include/linux/dma-mapping.h:5,
from drivers/crypto/tegra/tegra-se-hash.c:8:
drivers/crypto/tegra/tegra-se-hash.c: In function 'tegra_sha_prep_cmd':
>> drivers/crypto/tegra/tegra-se-hash.c:342:26: warning: format '%lu' expects argument of type 'long unsigned int', but argument 6 has type 'ssize_t' {aka 'int'} [-Wformat=]
342 | dev_dbg(se->dev, "msg len %llu msg left %llu sz %lu cfg %#x",
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/dev_printk.h:139:49: note: in definition of macro 'dev_no_printk'
139 | _dev_printk(level, dev, fmt, ##__VA_ARGS__); \
| ^~~
include/linux/dev_printk.h:171:40: note: in expansion of macro 'dev_fmt'
171 | dev_no_printk(KERN_DEBUG, dev, dev_fmt(fmt), ##__VA_ARGS__)
| ^~~~~~~
drivers/crypto/tegra/tegra-se-hash.c:342:9: note: in expansion of macro 'dev_dbg'
342 | dev_dbg(se->dev, "msg len %llu msg left %llu sz %lu cfg %#x",
| ^~~~~~~
drivers/crypto/tegra/tegra-se-hash.c:342:59: note: format string is defined here
342 | dev_dbg(se->dev, "msg len %llu msg left %llu sz %lu cfg %#x",
| ~~^
| |
| long unsigned int
| %u
drivers/crypto/tegra/tegra-se-hash.c: In function 'tegra_sha_digest':
drivers/crypto/tegra/tegra-se-hash.c:701:13: warning: unused variable 'ret' [-Wunused-variable]
701 | int ret;
| ^~~
vim +342 drivers/crypto/tegra/tegra-se-hash.c
265
266 static int tegra_sha_prep_cmd(struct tegra_sha_ctx *ctx, u32 *cpuvaddr,
267 struct tegra_sha_reqctx *rctx)
268 {
269 struct tegra_se *se = ctx->se;
270 u64 msg_len, msg_left;
271 int i = 0;
272
273 msg_len = rctx->total_len * 8;
274 msg_left = rctx->datbuf.size * 8;
275
276 /*
277 * If IN_ADDR_HI_0.SZ > SHA_MSG_LEFT_[0-3] to the HASH engine,
278 * HW treats it as the last buffer and process the data.
279 * Therefore, add an extra byte to msg_left if it is not the
280 * last buffer.
281 */
282 if (rctx->task & SHA_UPDATE) {
283 msg_left += 8;
284 msg_len += 8;
285 }
286
287 cpuvaddr[i++] = host1x_opcode_setpayload(8);
288 cpuvaddr[i++] = se_host1x_opcode_incr_w(SE_SHA_MSG_LENGTH);
289 cpuvaddr[i++] = lower_32_bits(msg_len);
290 cpuvaddr[i++] = upper_32_bits(msg_len);
291 cpuvaddr[i++] = 0;
292 cpuvaddr[i++] = 0;
293 cpuvaddr[i++] = lower_32_bits(msg_left);
294 cpuvaddr[i++] = upper_32_bits(msg_left);
295 cpuvaddr[i++] = 0;
296 cpuvaddr[i++] = 0;
297 cpuvaddr[i++] = host1x_opcode_setpayload(2);
298 cpuvaddr[i++] = se_host1x_opcode_incr_w(SE_SHA_CFG);
299 cpuvaddr[i++] = rctx->config;
300
301 if (rctx->task & SHA_FIRST) {
302 cpuvaddr[i++] = SE_SHA_TASK_HASH_INIT;
303 rctx->task &= ~SHA_FIRST;
304 } else {
305 /*
306 * If it isn't the first task, program the HASH_RESULT register
307 * with the intermediate result from the previous task
308 */
309 i += tegra_se_insert_hash_result(ctx, cpuvaddr + i, rctx);
310 }
311
312 cpuvaddr[i++] = host1x_opcode_setpayload(4);
313 cpuvaddr[i++] = se_host1x_opcode_incr_w(SE_SHA_IN_ADDR);
314 cpuvaddr[i++] = rctx->datbuf.addr;
315 cpuvaddr[i++] = (u32)(SE_ADDR_HI_MSB(upper_32_bits(rctx->datbuf.addr)) |
316 SE_ADDR_HI_SZ(rctx->datbuf.size));
317
318 if (rctx->task & SHA_UPDATE) {
319 cpuvaddr[i++] = rctx->intr_res.addr;
320 cpuvaddr[i++] = (u32)(SE_ADDR_HI_MSB(upper_32_bits(rctx->intr_res.addr)) |
321 SE_ADDR_HI_SZ(rctx->intr_res.size));
322 } else {
323 cpuvaddr[i++] = rctx->digest.addr;
324 cpuvaddr[i++] = (u32)(SE_ADDR_HI_MSB(upper_32_bits(rctx->digest.addr)) |
325 SE_ADDR_HI_SZ(rctx->digest.size));
326 }
327
328 if (rctx->key_id) {
329 cpuvaddr[i++] = host1x_opcode_setpayload(1);
330 cpuvaddr[i++] = se_host1x_opcode_nonincr_w(SE_SHA_CRYPTO_CFG);
331 cpuvaddr[i++] = SE_AES_KEY_INDEX(rctx->key_id);
332 }
333
334 cpuvaddr[i++] = host1x_opcode_setpayload(1);
335 cpuvaddr[i++] = se_host1x_opcode_nonincr_w(SE_SHA_OPERATION);
336 cpuvaddr[i++] = SE_SHA_OP_WRSTALL | SE_SHA_OP_START |
337 SE_SHA_OP_LASTBUF;
338 cpuvaddr[i++] = se_host1x_opcode_nonincr(host1x_uclass_incr_syncpt_r(), 1);
339 cpuvaddr[i++] = host1x_uclass_incr_syncpt_cond_f(1) |
340 host1x_uclass_incr_syncpt_indx_f(se->syncpt_id);
341
> 342 dev_dbg(se->dev, "msg len %llu msg left %llu sz %lu cfg %#x",
343 msg_len, msg_left, rctx->datbuf.size, rctx->config);
344
345 return i;
346 }
347
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
Hi Akhil,
kernel test robot noticed the following build warnings:
[auto build test WARNING on herbert-crypto-2.6/master]
[also build test WARNING on herbert-cryptodev-2.6/master linus/master v6.14-rc2 next-20250212]
[cannot apply to tegra/for-next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Akhil-R/crypto-tegra-Use-separate-buffer-for-setkey/20250212-012434
base: https://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6.git master
patch link: https://lore.kernel.org/r/20250211171713.65770-7-akhilrajeev%40nvidia.com
patch subject: [PATCH v2 06/10] crypto: tegra: Fix HASH intermediate result handling
config: nios2-randconfig-r112-20250213 (https://download.01.org/0day-ci/archive/20250213/202502131419.R9s0l3RE-lkp@intel.com/config)
compiler: nios2-linux-gcc (GCC) 14.2.0
reproduce: (https://download.01.org/0day-ci/archive/20250213/202502131419.R9s0l3RE-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202502131419.R9s0l3RE-lkp@intel.com/
sparse warnings: (new ones prefixed by >>)
>> drivers/crypto/tegra/tegra-se-hash.c:258:41: sparse: sparse: cast to restricted __be32
>> drivers/crypto/tegra/tegra-se-hash.c:258:41: sparse: sparse: cast to restricted __be32
>> drivers/crypto/tegra/tegra-se-hash.c:258:41: sparse: sparse: cast to restricted __be32
>> drivers/crypto/tegra/tegra-se-hash.c:258:41: sparse: sparse: cast to restricted __be32
>> drivers/crypto/tegra/tegra-se-hash.c:258:41: sparse: sparse: cast to restricted __be32
>> drivers/crypto/tegra/tegra-se-hash.c:258:41: sparse: sparse: cast to restricted __be32
drivers/crypto/tegra/tegra-se-hash.c: note: in included file (through include/uapi/linux/swab.h, include/linux/swab.h, include/uapi/linux/byteorder/little_endian.h, ...):
arch/nios2/include/uapi/asm/swab.h:31:24: sparse: sparse: too many arguments for function __builtin_custom_ini
vim +258 drivers/crypto/tegra/tegra-se-hash.c
214
215 static int tegra_se_insert_hash_result(struct tegra_sha_ctx *ctx, u32 *cpuvaddr,
216 struct tegra_sha_reqctx *rctx)
217 {
218 u32 *res = (u32 *)rctx->intr_res.buf;
219 int i = 0, j;
220
221 cpuvaddr[i++] = 0;
222 cpuvaddr[i++] = host1x_opcode_setpayload(HASH_RESULT_REG_COUNT);
223 cpuvaddr[i++] = se_host1x_opcode_incr_w(SE_SHA_HASH_RESULT);
224
225 for (j = 0; j < HASH_RESULT_REG_COUNT; j++) {
226 int idx = j;
227
228 /*
229 * The initial, intermediate and final hash value of SHA-384, SHA-512
230 * in SHA_HASH_RESULT registers follow the below layout of bytes.
231 *
232 * +---------------+------------+
233 * | HASH_RESULT_0 | B4...B7 |
234 * +---------------+------------+
235 * | HASH_RESULT_1 | B0...B3 |
236 * +---------------+------------+
237 * | HASH_RESULT_2 | B12...B15 |
238 * +---------------+------------+
239 * | HASH_RESULT_3 | B8...B11 |
240 * +---------------+------------+
241 * | ...... |
242 * +---------------+------------+
243 * | HASH_RESULT_14| B60...B63 |
244 * +---------------+------------+
245 * | HASH_RESULT_15| B56...B59 |
246 * +---------------+------------+
247 *
248 */
249 if (ctx->alg == SE_ALG_SHA384 || ctx->alg == SE_ALG_SHA512)
250 idx = (j % 2) ? j - 1 : j + 1;
251
252 /* For SHA-1, SHA-224, SHA-256, SHA-384, SHA-512 the initial
253 * intermediate and final hash value when stored in
254 * SHA_HASH_RESULT registers, the byte order is NOT in
255 * little-endian.
256 */
257 if (ctx->alg <= SE_ALG_SHA512)
> 258 cpuvaddr[i++] = be32_to_cpu(res[idx]);
259 else
260 cpuvaddr[i++] = res[idx];
261 }
262
263 return i;
264 }
265
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
Hi Akhil,
kernel test robot noticed the following build warnings:
[auto build test WARNING on herbert-crypto-2.6/master]
[also build test WARNING on herbert-cryptodev-2.6/master linus/master v6.14-rc2 next-20250213]
[cannot apply to tegra/for-next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Akhil-R/crypto-tegra-Use-separate-buffer-for-setkey/20250212-012434
base: https://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6.git master
patch link: https://lore.kernel.org/r/20250211171713.65770-7-akhilrajeev%40nvidia.com
patch subject: [PATCH v2 06/10] crypto: tegra: Fix HASH intermediate result handling
config: i386-buildonly-randconfig-002-20250213 (https://download.01.org/0day-ci/archive/20250213/202502131717.CFOwEfqA-lkp@intel.com/config)
compiler: clang version 19.1.3 (https://github.com/llvm/llvm-project ab51eccf88f5321e7c60591c5546b254b6afab99)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250213/202502131717.CFOwEfqA-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202502131717.CFOwEfqA-lkp@intel.com/
All warnings (new ones prefixed by >>):
In file included from drivers/crypto/tegra/tegra-se-hash.c:8:
In file included from include/linux/dma-mapping.h:8:
In file included from include/linux/scatterlist.h:8:
In file included from include/linux/mm.h:2223:
include/linux/vmstat.h:518:36: warning: arithmetic between different enumeration types ('enum node_stat_item' and 'enum lru_list') [-Wenum-enum-conversion]
518 | return node_stat_name(NR_LRU_BASE + lru) + 3; // skip "nr_"
| ~~~~~~~~~~~ ^ ~~~
>> drivers/crypto/tegra/tegra-se-hash.c:343:22: warning: format specifies type 'unsigned long' but the argument has type 'ssize_t' (aka 'int') [-Wformat]
342 | dev_dbg(se->dev, "msg len %llu msg left %llu sz %lu cfg %#x",
| ~~~
| %zd
343 | msg_len, msg_left, rctx->datbuf.size, rctx->config);
| ^~~~~~~~~~~~~~~~~
include/linux/dev_printk.h:165:39: note: expanded from macro 'dev_dbg'
165 | dynamic_dev_dbg(dev, dev_fmt(fmt), ##__VA_ARGS__)
| ~~~ ^~~~~~~~~~~
include/linux/dynamic_debug.h:274:19: note: expanded from macro 'dynamic_dev_dbg'
274 | dev, fmt, ##__VA_ARGS__)
| ~~~ ^~~~~~~~~~~
include/linux/dynamic_debug.h:250:59: note: expanded from macro '_dynamic_func_call'
250 | _dynamic_func_call_cls(_DPRINTK_CLASS_DFLT, fmt, func, ##__VA_ARGS__)
| ^~~~~~~~~~~
include/linux/dynamic_debug.h:248:65: note: expanded from macro '_dynamic_func_call_cls'
248 | __dynamic_func_call_cls(__UNIQUE_ID(ddebug), cls, fmt, func, ##__VA_ARGS__)
| ^~~~~~~~~~~
include/linux/dynamic_debug.h:224:15: note: expanded from macro '__dynamic_func_call_cls'
224 | func(&id, ##__VA_ARGS__); \
| ^~~~~~~~~~~
drivers/crypto/tegra/tegra-se-hash.c:701:6: warning: unused variable 'ret' [-Wunused-variable]
701 | int ret;
| ^~~
3 warnings generated.
vim +343 drivers/crypto/tegra/tegra-se-hash.c
265
266 static int tegra_sha_prep_cmd(struct tegra_sha_ctx *ctx, u32 *cpuvaddr,
267 struct tegra_sha_reqctx *rctx)
268 {
269 struct tegra_se *se = ctx->se;
270 u64 msg_len, msg_left;
271 int i = 0;
272
273 msg_len = rctx->total_len * 8;
274 msg_left = rctx->datbuf.size * 8;
275
276 /*
277 * If IN_ADDR_HI_0.SZ > SHA_MSG_LEFT_[0-3] to the HASH engine,
278 * HW treats it as the last buffer and process the data.
279 * Therefore, add an extra byte to msg_left if it is not the
280 * last buffer.
281 */
282 if (rctx->task & SHA_UPDATE) {
283 msg_left += 8;
284 msg_len += 8;
285 }
286
287 cpuvaddr[i++] = host1x_opcode_setpayload(8);
288 cpuvaddr[i++] = se_host1x_opcode_incr_w(SE_SHA_MSG_LENGTH);
289 cpuvaddr[i++] = lower_32_bits(msg_len);
290 cpuvaddr[i++] = upper_32_bits(msg_len);
291 cpuvaddr[i++] = 0;
292 cpuvaddr[i++] = 0;
293 cpuvaddr[i++] = lower_32_bits(msg_left);
294 cpuvaddr[i++] = upper_32_bits(msg_left);
295 cpuvaddr[i++] = 0;
296 cpuvaddr[i++] = 0;
297 cpuvaddr[i++] = host1x_opcode_setpayload(2);
298 cpuvaddr[i++] = se_host1x_opcode_incr_w(SE_SHA_CFG);
299 cpuvaddr[i++] = rctx->config;
300
301 if (rctx->task & SHA_FIRST) {
302 cpuvaddr[i++] = SE_SHA_TASK_HASH_INIT;
303 rctx->task &= ~SHA_FIRST;
304 } else {
305 /*
306 * If it isn't the first task, program the HASH_RESULT register
307 * with the intermediate result from the previous task
308 */
309 i += tegra_se_insert_hash_result(ctx, cpuvaddr + i, rctx);
310 }
311
312 cpuvaddr[i++] = host1x_opcode_setpayload(4);
313 cpuvaddr[i++] = se_host1x_opcode_incr_w(SE_SHA_IN_ADDR);
314 cpuvaddr[i++] = rctx->datbuf.addr;
315 cpuvaddr[i++] = (u32)(SE_ADDR_HI_MSB(upper_32_bits(rctx->datbuf.addr)) |
316 SE_ADDR_HI_SZ(rctx->datbuf.size));
317
318 if (rctx->task & SHA_UPDATE) {
319 cpuvaddr[i++] = rctx->intr_res.addr;
320 cpuvaddr[i++] = (u32)(SE_ADDR_HI_MSB(upper_32_bits(rctx->intr_res.addr)) |
321 SE_ADDR_HI_SZ(rctx->intr_res.size));
322 } else {
323 cpuvaddr[i++] = rctx->digest.addr;
324 cpuvaddr[i++] = (u32)(SE_ADDR_HI_MSB(upper_32_bits(rctx->digest.addr)) |
325 SE_ADDR_HI_SZ(rctx->digest.size));
326 }
327
328 if (rctx->key_id) {
329 cpuvaddr[i++] = host1x_opcode_setpayload(1);
330 cpuvaddr[i++] = se_host1x_opcode_nonincr_w(SE_SHA_CRYPTO_CFG);
331 cpuvaddr[i++] = SE_AES_KEY_INDEX(rctx->key_id);
332 }
333
334 cpuvaddr[i++] = host1x_opcode_setpayload(1);
335 cpuvaddr[i++] = se_host1x_opcode_nonincr_w(SE_SHA_OPERATION);
336 cpuvaddr[i++] = SE_SHA_OP_WRSTALL | SE_SHA_OP_START |
337 SE_SHA_OP_LASTBUF;
338 cpuvaddr[i++] = se_host1x_opcode_nonincr(host1x_uclass_incr_syncpt_r(), 1);
339 cpuvaddr[i++] = host1x_uclass_incr_syncpt_cond_f(1) |
340 host1x_uclass_incr_syncpt_indx_f(se->syncpt_id);
341
342 dev_dbg(se->dev, "msg len %llu msg left %llu sz %lu cfg %#x",
> 343 msg_len, msg_left, rctx->datbuf.size, rctx->config);
344
345 return i;
346 }
347
--
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