Due to the path mux design of the MT8196, the following components
need to be added to support Picture Quality (PQ) in the main display
path: CCORR0, CCORR1, DITHER0, GAMMA0, MDP_RSZ0, POSTMASK0, TDSHP0.
Signed-off-by: Sunny Shen <sunny.shen@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index b810a197f58b..1c97dc46ae70 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -242,6 +242,13 @@ static const unsigned int mt8196_mtk_ddp_ovl0_main[] = {
static const unsigned int mt8196_mtk_ddp_disp0_main[] = {
DDP_COMPONENT_DLI_ASYNC0,
+ DDP_COMPONENT_MDP_RSZ0,
+ DDP_COMPONENT_TDSHP0,
+ DDP_COMPONENT_CCORR0,
+ DDP_COMPONENT_CCORR1,
+ DDP_COMPONENT_GAMMA0,
+ DDP_COMPONENT_POSTMASK0,
+ DDP_COMPONENT_DITHER0,
DDP_COMPONENT_DLO_ASYNC1,
};
--
2.34.1
On Tue, 2025-02-11 at 10:52 +0800, Sunny Shen wrote:
> Due to the path mux design of the MT8196, the following components
> need to be added to support Picture Quality (PQ) in the main display
> path: CCORR0, CCORR1, DITHER0, GAMMA0, MDP_RSZ0, POSTMASK0, TDSHP0.
Reviewed-by: CK Hu <ck.hu@mediatek.com>
>
> Signed-off-by: Sunny Shen <sunny.shen@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index b810a197f58b..1c97dc46ae70 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -242,6 +242,13 @@ static const unsigned int mt8196_mtk_ddp_ovl0_main[] = {
>
> static const unsigned int mt8196_mtk_ddp_disp0_main[] = {
> DDP_COMPONENT_DLI_ASYNC0,
> + DDP_COMPONENT_MDP_RSZ0,
> + DDP_COMPONENT_TDSHP0,
> + DDP_COMPONENT_CCORR0,
> + DDP_COMPONENT_CCORR1,
> + DDP_COMPONENT_GAMMA0,
> + DDP_COMPONENT_POSTMASK0,
> + DDP_COMPONENT_DITHER0,
> DDP_COMPONENT_DLO_ASYNC1,
> };
>
Il 17/02/25 07:06, CK Hu (胡俊光) ha scritto:
> On Tue, 2025-02-11 at 10:52 +0800, Sunny Shen wrote:
>> Due to the path mux design of the MT8196, the following components
>> need to be added to support Picture Quality (PQ) in the main display
>> path: CCORR0, CCORR1, DITHER0, GAMMA0, MDP_RSZ0, POSTMASK0, TDSHP0.
>
> Reviewed-by: CK Hu <ck.hu@mediatek.com>
>
>>
>> Signed-off-by: Sunny Shen <sunny.shen@mediatek.com>
>> ---
>> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 7 +++++++
>> 1 file changed, 7 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
>> index b810a197f58b..1c97dc46ae70 100644
>> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
>> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
>> @@ -242,6 +242,13 @@ static const unsigned int mt8196_mtk_ddp_ovl0_main[] = {
>>
>> static const unsigned int mt8196_mtk_ddp_disp0_main[] = {
If you build the display controller path with an OF graph, you don't need to
introduce any mt8196_mtk_ddp_disp0_main, at all.
Since all this work was done and upstreamed, and was done because hardcoding
the display pipeline for each board is only bloating the driver (and wrong),
just express the pipeline with a graph in the devicetree.
The driver doesn't need that array, not anymore.
Regards,
Angelo
>> DDP_COMPONENT_DLI_ASYNC0,
>> + DDP_COMPONENT_MDP_RSZ0,
>> + DDP_COMPONENT_TDSHP0,
>> + DDP_COMPONENT_CCORR0,
>> + DDP_COMPONENT_CCORR1,
>> + DDP_COMPONENT_GAMMA0,
>> + DDP_COMPONENT_POSTMASK0,
>> + DDP_COMPONENT_DITHER0,
>> DDP_COMPONENT_DLO_ASYNC1,
>> };
>>
>
On Mon, 2025-02-17 at 15:25 +0100, AngeloGioacchino Del Regno wrote:
>
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
>
>
> Il 17/02/25 07:06, CK Hu (胡俊光) ha scritto:
> > On Tue, 2025-02-11 at 10:52 +0800, Sunny Shen wrote:
> > > Due to the path mux design of the MT8196, the following
> > > components
> > > need to be added to support Picture Quality (PQ) in the main
> > > display
> > > path: CCORR0, CCORR1, DITHER0, GAMMA0, MDP_RSZ0, POSTMASK0,
> > > TDSHP0.
> >
> > Reviewed-by: CK Hu <ck.hu@mediatek.com>
> >
> > >
> > > Signed-off-by: Sunny Shen <sunny.shen@mediatek.com>
> > > ---
> > > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 7 +++++++
> > > 1 file changed, 7 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > > b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > > index b810a197f58b..1c97dc46ae70 100644
> > > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > > @@ -242,6 +242,13 @@ static const unsigned int
> > > mt8196_mtk_ddp_ovl0_main[] = {
> > >
> > > static const unsigned int mt8196_mtk_ddp_disp0_main[] = {
>
> If you build the display controller path with an OF graph, you don't
> need to
> introduce any mt8196_mtk_ddp_disp0_main, at all.
>
> Since all this work was done and upstreamed, and was done because
> hardcoding
> the display pipeline for each board is only bloating the driver (and
> wrong),
> just express the pipeline with a graph in the devicetree.
>
> The driver doesn't need that array, not anymore.
>
> Regards,
> Angelo
Hi Angelo,
Thank you for the review
We are still investigating the method of using OF graph.
I can find a patch of add controllor graph here
(https://patchwork.kernel.org/project/linux-mediatek/patch/20250220110948.45596-2-angelogioacchino.delregno@collabora.com/
)
May I ask that is there any example of driver config display path by OF
graph?
And since the path control is not the main topic of PQ support.
Should we discard the change of this file
and modify the patch added path of mt8196?
(https://patchwork.kernel.org/project/linux-mediatek/patch/20250321093435.94835-16-paul-pl.chen@mediatek.com/
)
Or add a new patch series?
Regards,
Sunny
>
> > > DDP_COMPONENT_DLI_ASYNC0,
> > > + DDP_COMPONENT_MDP_RSZ0,
> > > + DDP_COMPONENT_TDSHP0,
> > > + DDP_COMPONENT_CCORR0,
> > > + DDP_COMPONENT_CCORR1,
> > > + DDP_COMPONENT_GAMMA0,
> > > + DDP_COMPONENT_POSTMASK0,
> > > + DDP_COMPONENT_DITHER0,
> > > DDP_COMPONENT_DLO_ASYNC1,
> > > };
> > >
> >
>
>
>
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