From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Currently, the watchdog driver relies on TF-A/U-Boot to configure the
`CPG_ERRORRST_SEL2` register. This register must be set correctly to
ensure a reset request is issued upon watchdog timer (WDT) underflow.

Now that the driver has access to the `syscon` handle for CPG, configure
`CPG_ERRORRST_SEL2` directly instead of depending on firmware. This
improves robustness by ensuring the required configuration is applied
within the driver itself.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v3->v4
- New patch
---
 drivers/watchdog/rzv2h_wdt.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/drivers/watchdog/rzv2h_wdt.c b/drivers/watchdog/rzv2h_wdt.c
index c9bdaa8f2e3a..04b8ee899353 100644
--- a/drivers/watchdog/rzv2h_wdt.c
+++ b/drivers/watchdog/rzv2h_wdt.c
@@ -43,6 +43,10 @@
 
 #define WDT_DEFAULT_TIMEOUT	60U
 
+#define CPG_ERRORRST_SEL2(x)	((x) - 0x3c)
+#define CPG_ERRRSTSELx(x)	BIT(x)
+#define CPG_ERRRSTSELx_WEN(x)	BIT((x) + 16)
+
 #define CPG_ERROR_RST2(x)	BIT(x)
 #define CPG_ERROR_RST2_WEN(x)	BIT((x) + 16)
 
@@ -246,6 +250,16 @@ static int rzv2h_wdt_probe(struct platform_device *pdev)
 				return ret;
 		}
 		bootstatus = val & CPG_ERROR_RST2(bit) ? WDIOF_CARDRESET : 0;
+
+		/*
+		 * configure CPG_ERRORRST_SEL2 register to issue a reset request
+		 * upon WDT underflow
+		 */
+		ret = regmap_write(syscon, CPG_ERRORRST_SEL2(offset),
+				   CPG_ERRRSTSELx(bit) |
+				   CPG_ERRRSTSELx_WEN(bit));
+		if (ret)
+			return ret;
 	}
 
 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
-- 
2.43.0

Hi Prabhakar,

On Mon, 10 Feb 2025 at 19:49, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Currently, the watchdog driver relies on TF-A/U-Boot to configure the
> `CPG_ERRORRST_SEL2` register. This register must be set correctly to
> ensure a reset request is issued upon watchdog timer (WDT) underflow.
>
> Now that the driver has access to the `syscon` handle for CPG, configure
> `CPG_ERRORRST_SEL2` directly instead of depending on firmware. This
> improves robustness by ensuring the required configuration is applied
> within the driver itself.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Thanks for your patch!

IMHO doing it in the firmware stack is actually a good thing, as the
watchdog policy is system-wide, and thus goes beyond Linux running on
the application cores.

That is also the reason why commit 76b1c5b218f31811 ("[TEST] soc:
renesas: rcar-rst: Enable WDT reset on early R-Car V4M") is only
part of renesas-drivers[1], and not planned for upstream.  The sole
exception on modern R-Car is R-Car V3U, cfr. commit cb9a39aacd3d6387
("soc: renesas: rcar-rst: Allow WDT reset on R-Car V3U")[2].

[1] https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git/commit/?h=renesas-drivers-2025-02-18-v6.14-rc3&id=76b1c5b218f31811a7aaca588d3ec4ba584b7bf2
[2] https://elixir.bootlin.com/linux/v6.13.3/source/drivers/soc/renesas/rcar-rst.c#L76

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds