The CRU block found on the Renesas RZ/G3E ("R9A09G047") SoC has five
interrups:
- image_conv: image_conv irq
- axi_mst_err: AXI master error level irq
- vd_addr_wend: Video data AXI master addr 0 write end irq
- sd_addr_wend: Statistics data AXI master addr 0 write end irq
- vsd_addr_wend: Video statistics data AXI master addr 0 write end irq
This IP has only one input port 'port@1' similar to the RZ/G2UL CRU.
Document the CRU block found on the Renesas RZ/G3E ("R9A09G047") SoC.
Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
---
.../bindings/media/renesas,rzg2l-cru.yaml | 33 ++++++++++++-------
1 file changed, 22 insertions(+), 11 deletions(-)
diff --git a/Documentation/devicetree/bindings/media/renesas,rzg2l-cru.yaml b/Documentation/devicetree/bindings/media/renesas,rzg2l-cru.yaml
index bc1245127025..7e4a7ed56378 100644
--- a/Documentation/devicetree/bindings/media/renesas,rzg2l-cru.yaml
+++ b/Documentation/devicetree/bindings/media/renesas,rzg2l-cru.yaml
@@ -17,24 +17,34 @@ description:
properties:
compatible:
- items:
- - enum:
- - renesas,r9a07g043-cru # RZ/G2UL
- - renesas,r9a07g044-cru # RZ/G2{L,LC}
- - renesas,r9a07g054-cru # RZ/V2L
- - const: renesas,rzg2l-cru
+ oneOf:
+ - items:
+ - enum:
+ - renesas,r9a07g043-cru # RZ/G2UL
+ - renesas,r9a07g044-cru # RZ/G2{L,LC}
+ - renesas,r9a07g054-cru # RZ/V2L
+ - const: renesas,rzg2l-cru
+
+ - const: renesas,r9a09g047-cru # RZ/G3E
reg:
maxItems: 1
interrupts:
- maxItems: 3
+ maxItems: 5
interrupt-names:
- items:
- - const: image_conv
- - const: image_conv_err
- - const: axi_mst_err
+ oneOf:
+ - items:
+ - const: image_conv
+ - const: image_conv_err
+ - const: axi_mst_err
+ - items:
+ - const: image_conv
+ - const: axi_mst_err
+ - const: vd_addr_wend
+ - const: sd_addr_wend
+ - const: vsd_addr_wend
clocks:
items:
@@ -120,6 +130,7 @@ allOf:
contains:
enum:
- renesas,r9a07g043-cru
+ - renesas,r9a09g047-cru
then:
properties:
ports:
--
2.34.1Hi Tommaso,
Thank you for the patch.
On Mon, Feb 10, 2025 at 12:45:36PM +0100, Tommaso Merciai wrote:
> The CRU block found on the Renesas RZ/G3E ("R9A09G047") SoC has five
> interrups:
>
> - image_conv: image_conv irq
> - axi_mst_err: AXI master error level irq
> - vd_addr_wend: Video data AXI master addr 0 write end irq
> - sd_addr_wend: Statistics data AXI master addr 0 write end irq
> - vsd_addr_wend: Video statistics data AXI master addr 0 write end irq
>
> This IP has only one input port 'port@1' similar to the RZ/G2UL CRU.
>
> Document the CRU block found on the Renesas RZ/G3E ("R9A09G047") SoC.
>
> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
> ---
> .../bindings/media/renesas,rzg2l-cru.yaml | 33 ++++++++++++-------
> 1 file changed, 22 insertions(+), 11 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/media/renesas,rzg2l-cru.yaml b/Documentation/devicetree/bindings/media/renesas,rzg2l-cru.yaml
> index bc1245127025..7e4a7ed56378 100644
> --- a/Documentation/devicetree/bindings/media/renesas,rzg2l-cru.yaml
> +++ b/Documentation/devicetree/bindings/media/renesas,rzg2l-cru.yaml
> @@ -17,24 +17,34 @@ description:
>
> properties:
> compatible:
> - items:
> - - enum:
> - - renesas,r9a07g043-cru # RZ/G2UL
> - - renesas,r9a07g044-cru # RZ/G2{L,LC}
> - - renesas,r9a07g054-cru # RZ/V2L
> - - const: renesas,rzg2l-cru
> + oneOf:
> + - items:
> + - enum:
> + - renesas,r9a07g043-cru # RZ/G2UL
> + - renesas,r9a07g044-cru # RZ/G2{L,LC}
> + - renesas,r9a07g054-cru # RZ/V2L
> + - const: renesas,rzg2l-cru
> +
> + - const: renesas,r9a09g047-cru # RZ/G3E
>
> reg:
> maxItems: 1
>
> interrupts:
> - maxItems: 3
> + maxItems: 5
>
> interrupt-names:
> - items:
> - - const: image_conv
> - - const: image_conv_err
> - - const: axi_mst_err
> + oneOf:
> + - items:
> + - const: image_conv
> + - const: image_conv_err
> + - const: axi_mst_err
> + - items:
> + - const: image_conv
> + - const: axi_mst_err
> + - const: vd_addr_wend
> + - const: sd_addr_wend
> + - const: vsd_addr_wend
This should move to a conditional block.
>
> clocks:
> items:
> @@ -120,6 +130,7 @@ allOf:
> contains:
> enum:
> - renesas,r9a07g043-cru
> + - renesas,r9a09g047-cru
> then:
> properties:
> ports:
--
Regards,
Laurent Pinchart
Hi Laurent,
Thanks for your review.
On Fri, Feb 14, 2025 at 02:45:00AM +0200, Laurent Pinchart wrote:
> Hi Tommaso,
>
> Thank you for the patch.
>
> On Mon, Feb 10, 2025 at 12:45:36PM +0100, Tommaso Merciai wrote:
> > The CRU block found on the Renesas RZ/G3E ("R9A09G047") SoC has five
> > interrups:
> >
> > - image_conv: image_conv irq
> > - axi_mst_err: AXI master error level irq
> > - vd_addr_wend: Video data AXI master addr 0 write end irq
> > - sd_addr_wend: Statistics data AXI master addr 0 write end irq
> > - vsd_addr_wend: Video statistics data AXI master addr 0 write end irq
> >
> > This IP has only one input port 'port@1' similar to the RZ/G2UL CRU.
> >
> > Document the CRU block found on the Renesas RZ/G3E ("R9A09G047") SoC.
> >
> > Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
> > ---
> > .../bindings/media/renesas,rzg2l-cru.yaml | 33 ++++++++++++-------
> > 1 file changed, 22 insertions(+), 11 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/media/renesas,rzg2l-cru.yaml b/Documentation/devicetree/bindings/media/renesas,rzg2l-cru.yaml
> > index bc1245127025..7e4a7ed56378 100644
> > --- a/Documentation/devicetree/bindings/media/renesas,rzg2l-cru.yaml
> > +++ b/Documentation/devicetree/bindings/media/renesas,rzg2l-cru.yaml
> > @@ -17,24 +17,34 @@ description:
> >
> > properties:
> > compatible:
> > - items:
> > - - enum:
> > - - renesas,r9a07g043-cru # RZ/G2UL
> > - - renesas,r9a07g044-cru # RZ/G2{L,LC}
> > - - renesas,r9a07g054-cru # RZ/V2L
> > - - const: renesas,rzg2l-cru
> > + oneOf:
> > + - items:
> > + - enum:
> > + - renesas,r9a07g043-cru # RZ/G2UL
> > + - renesas,r9a07g044-cru # RZ/G2{L,LC}
> > + - renesas,r9a07g054-cru # RZ/V2L
> > + - const: renesas,rzg2l-cru
> > +
> > + - const: renesas,r9a09g047-cru # RZ/G3E
> >
> > reg:
> > maxItems: 1
> >
> > interrupts:
> > - maxItems: 3
> > + maxItems: 5
> >
> > interrupt-names:
> > - items:
> > - - const: image_conv
> > - - const: image_conv_err
> > - - const: axi_mst_err
> > + oneOf:
> > + - items:
> > + - const: image_conv
> > + - const: image_conv_err
> > + - const: axi_mst_err
> > + - items:
> > + - const: image_conv
> > + - const: axi_mst_err
> > + - const: vd_addr_wend
> > + - const: sd_addr_wend
> > + - const: vsd_addr_wend
>
> This should move to a conditional block.
I think here we can do similar to patch 2/8.
What about setting here:
interrupts:
minItems: 3
maxItems: 5
interrupt-names:
minItems: 3
maxItems: 5
Then move interrupts and interrupt-names into
the conditional block:
allOf:
- if:
properties:
compatible:
contains:
enum:
- renesas,r9a07g044-cru
- renesas,r9a07g054-cru
then:
properties:
interrupts:
minItems: 3
maxItems: 3
interrupt-names:
items:
- const: image_conv
- const: image_conv_err
- const: axi_mst_err
ports:
required:
- port@0
- port@1
- if:
properties:
compatible:
contains:
enum:
- renesas,r9a07g043-cru
then:
properties:
interrupts:
minItems: 3
maxItems: 3
interrupt-names:
items:
- const: image_conv
- const: image_conv_err
- const: axi_mst_err
ports:
properties:
port@0: false
required:
- port@1
- if:
properties:
compatible:
contains:
const: renesas,r9a09g047-cru
then:
properties:
interrupts:
minItems: 5
maxItems: 5
interrupt-names:
items:
- const: image_conv
- const: axi_mst_err
- const: vd_addr_wend
- const: sd_addr_wend
- const: vsd_addr_wend
ports:
properties:
port@0: false
required:
- port@1
>
> >
> > clocks:
> > items:
> > @@ -120,6 +130,7 @@ allOf:
> > contains:
> > enum:
> > - renesas,r9a07g043-cru
> > + - renesas,r9a09g047-cru
> > then:
> > properties:
> > ports:
>
> --
> Regards,
>
> Laurent Pinchart
Thanks & Regards,
Tommaso
On Mon, 10 Feb 2025 12:45:36 +0100, Tommaso Merciai wrote:
> The CRU block found on the Renesas RZ/G3E ("R9A09G047") SoC has five
> interrups:
>
> - image_conv: image_conv irq
> - axi_mst_err: AXI master error level irq
> - vd_addr_wend: Video data AXI master addr 0 write end irq
> - sd_addr_wend: Statistics data AXI master addr 0 write end irq
> - vsd_addr_wend: Video statistics data AXI master addr 0 write end irq
>
> This IP has only one input port 'port@1' similar to the RZ/G2UL CRU.
>
> Document the CRU block found on the Renesas RZ/G3E ("R9A09G047") SoC.
>
> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
> ---
> .../bindings/media/renesas,rzg2l-cru.yaml | 33 ++++++++++++-------
> 1 file changed, 22 insertions(+), 11 deletions(-)
>
My bot found errors running 'make dt_binding_check' on your patch:
yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/media/renesas,rzg2l-cru.example.dtb: video@10830000: interrupts: [[0, 167, 4], [0, 168, 4], [0, 169, 4]] is too short
from schema $id: http://devicetree.org/schemas/media/renesas,rzg2l-cru.yaml#
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20250210114540.524790-5-tommaso.merciai.xr@bp.renesas.com
The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.
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