For PMUv3, the register MDCR_EL2.HPMN partitiones the PMU counters
into two ranges where counters 0..HPMN-1 are accessible by EL1 and, if
allowed, EL0 while counters HPMN..N are only accessible by EL2.
Introduce a module parameter in the PMUv3 driver to set this
register. The name reserved_host_counters reflects the intent to
reserve some counters for the host so the guest may eventually be
allowed direct access to a subset of PMU functionality for increased
performance.
Track HPMN and whether the pmu is partitioned in struct arm_pmu
because KVM will need to know that to handle guests correctly.
While FEAT_HPMN0 does allow HPMN to be set to 0, this patch
specifically disallows that case because it's not useful given the
intention to allow guests access to their own counters.
Due to the difficulty this feature would create for the driver running
at EL1 on the host, partitioning is only allowed in VHE mode. Working
on nVHE mode would require a hypercall for every register access
because the counters reserved for the host by HPMN are now only
accessible to EL2.
The parameter is only configurable at boot time. Making the parameter
configurable on a running system is dangerous due to the difficulty of
knowing for sure no counters are in use anywhere so it is safe to
reporgram HPMN.
Signed-off-by: Colton Lewis <coltonlewis@google.com>
---
arch/arm/include/asm/arm_pmuv3.h | 13 +++++++++
arch/arm64/include/asm/arm_pmuv3.h | 10 +++++++
drivers/perf/arm_pmuv3.c | 46 ++++++++++++++++++++++++++++--
include/linux/perf/arm_pmu.h | 2 ++
include/linux/perf/arm_pmuv3.h | 7 +++++
5 files changed, 76 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/arm_pmuv3.h b/arch/arm/include/asm/arm_pmuv3.h
index 2ec0e5e83fc9..c5f496450e16 100644
--- a/arch/arm/include/asm/arm_pmuv3.h
+++ b/arch/arm/include/asm/arm_pmuv3.h
@@ -11,6 +11,8 @@
#define PMCCNTR __ACCESS_CP15_64(0, c9)
+#define HDCR __ACCESS_CP15(c1, 4, c1, 1)
+
#define PMCR __ACCESS_CP15(c9, 0, c12, 0)
#define PMCNTENSET __ACCESS_CP15(c9, 0, c12, 1)
#define PMCNTENCLR __ACCESS_CP15(c9, 0, c12, 2)
@@ -214,6 +216,7 @@ static inline void write_pmuserenr(u32 val)
static inline void write_pmuacr(u64 val) {}
+static inline bool has_vhe(void) { return false; }
static inline void kvm_set_pmu_events(u32 set, struct perf_event_attr *attr) {}
static inline void kvm_clr_pmu_events(u32 clr) {}
static inline bool kvm_pmu_counter_deferred(struct perf_event_attr *attr)
@@ -277,4 +280,14 @@ static inline u64 read_pmceid1(void)
return val;
}
+static inline u32 read_mdcr(void)
+{
+ return read_sysreg(HDCR);
+}
+
+static inline void write_mdcr(u32 val)
+{
+ write_sysreg(val, HDCR);
+}
+
#endif
diff --git a/arch/arm64/include/asm/arm_pmuv3.h b/arch/arm64/include/asm/arm_pmuv3.h
index 8a777dec8d88..fc37e7e81e07 100644
--- a/arch/arm64/include/asm/arm_pmuv3.h
+++ b/arch/arm64/include/asm/arm_pmuv3.h
@@ -188,4 +188,14 @@ static inline bool is_pmuv3p9(int pmuver)
return pmuver >= ID_AA64DFR0_EL1_PMUVer_V3P9;
}
+static inline u64 read_mdcr(void)
+{
+ return read_sysreg(mdcr_el2);
+}
+
+static inline void write_mdcr(u64 val)
+{
+ write_sysreg(val, mdcr_el2);
+}
+
#endif
diff --git a/drivers/perf/arm_pmuv3.c b/drivers/perf/arm_pmuv3.c
index 0e360feb3432..39109260b161 100644
--- a/drivers/perf/arm_pmuv3.c
+++ b/drivers/perf/arm_pmuv3.c
@@ -325,6 +325,7 @@ GEN_PMU_FORMAT_ATTR(threshold_compare);
GEN_PMU_FORMAT_ATTR(threshold);
static int sysctl_perf_user_access __read_mostly;
+static u8 reserved_host_counters __read_mostly;
static bool armv8pmu_event_is_64bit(struct perf_event *event)
{
@@ -500,6 +501,29 @@ static void armv8pmu_pmcr_write(u64 val)
write_pmcr(val);
}
+static u64 armv8pmu_mdcr_read(void)
+{
+ return read_mdcr();
+}
+
+static void armv8pmu_mdcr_write(u64 val)
+{
+ write_mdcr(val);
+ isb();
+}
+
+static void armv8pmu_partition(u8 hpmn)
+{
+ u64 mdcr = armv8pmu_mdcr_read();
+
+ mdcr &= ~ARMV8_PMU_MDCR_HPMN;
+ mdcr |= FIELD_PREP(ARMV8_PMU_MDCR_HPMN, hpmn);
+ /* Prevent guest counters counting at EL2 */
+ mdcr |= ARMV8_PMU_MDCR_HPMD;
+
+ armv8pmu_mdcr_write(mdcr);
+}
+
static int armv8pmu_has_overflowed(u64 pmovsr)
{
return !!(pmovsr & ARMV8_PMU_OVERFLOWED_MASK);
@@ -1069,6 +1093,9 @@ static void armv8pmu_reset(void *info)
bitmap_to_arr64(&mask, cpu_pmu->cntr_mask, ARMPMU_MAX_HWEVENTS);
+ if (cpu_pmu->partitioned)
+ armv8pmu_partition(cpu_pmu->hpmn);
+
/* The counter and interrupt enable registers are unknown at reset. */
armv8pmu_disable_counter(mask);
armv8pmu_disable_intens(mask);
@@ -1205,6 +1232,7 @@ static void __armv8pmu_probe_pmu(void *info)
{
struct armv8pmu_probe_info *probe = info;
struct arm_pmu *cpu_pmu = probe->pmu;
+ u8 pmcr_n;
u64 pmceid_raw[2];
u32 pmceid[2];
int pmuver;
@@ -1215,10 +1243,20 @@ static void __armv8pmu_probe_pmu(void *info)
cpu_pmu->pmuver = pmuver;
probe->present = true;
+ pmcr_n = FIELD_GET(ARMV8_PMU_PMCR_N, armv8pmu_pmcr_read());
/* Read the nb of CNTx counters supported from PMNC */
- bitmap_set(cpu_pmu->cntr_mask,
- 0, FIELD_GET(ARMV8_PMU_PMCR_N, armv8pmu_pmcr_read()));
+ bitmap_set(cpu_pmu->cntr_mask, 0, pmcr_n);
+
+ if (has_vhe() &&
+ reserved_host_counters > 0 &&
+ reserved_host_counters < pmcr_n) {
+ cpu_pmu->hpmn = pmcr_n - reserved_host_counters;
+ cpu_pmu->partitioned = true;
+ } else {
+ cpu_pmu->hpmn = pmcr_n;
+ cpu_pmu->partitioned = false;
+ }
/* Add the CPU cycles counter */
set_bit(ARMV8_PMU_CYCLE_IDX, cpu_pmu->cntr_mask);
@@ -1516,3 +1554,7 @@ void arch_perf_update_userpage(struct perf_event *event,
userpg->cap_user_time_zero = 1;
userpg->cap_user_time_short = 1;
}
+
+module_param(reserved_host_counters, byte, 0);
+MODULE_PARM_DESC(reserved_host_counters,
+ "Partition the PMU into host and guest counters");
diff --git a/include/linux/perf/arm_pmu.h b/include/linux/perf/arm_pmu.h
index 4b5b83677e3f..ad97aabed25a 100644
--- a/include/linux/perf/arm_pmu.h
+++ b/include/linux/perf/arm_pmu.h
@@ -101,6 +101,8 @@ struct arm_pmu {
void (*reset)(void *);
int (*map_event)(struct perf_event *event);
DECLARE_BITMAP(cntr_mask, ARMPMU_MAX_HWEVENTS);
+ u8 hpmn; /* MDCR_EL2.HPMN: counter partition pivot */
+ bool partitioned;
bool secure_access; /* 32-bit ARM only */
#define ARMV8_PMUV3_MAX_COMMON_EVENTS 0x40
DECLARE_BITMAP(pmceid_bitmap, ARMV8_PMUV3_MAX_COMMON_EVENTS);
diff --git a/include/linux/perf/arm_pmuv3.h b/include/linux/perf/arm_pmuv3.h
index c2448477c37f..115ee39f693a 100644
--- a/include/linux/perf/arm_pmuv3.h
+++ b/include/linux/perf/arm_pmuv3.h
@@ -223,6 +223,13 @@
ARMV8_PMU_PMCR_X | ARMV8_PMU_PMCR_DP | \
ARMV8_PMU_PMCR_LC | ARMV8_PMU_PMCR_LP)
+/*
+ * Per-CPU MDCR: config reg
+ */
+#define ARMV8_PMU_MDCR_HPMN GENMASK(4, 0)
+#define ARMV8_PMU_MDCR_HPME BIT(7)
+#define ARMV8_PMU_MDCR_HPMD BIT(17)
+
/*
* Counter bitmask layouts for overflow, enable, and interrupts
*/
--
2.48.1.502.g6dc24dfdaf-googHi Colton,
On Sat, Feb 08, 2025 at 02:01:09AM +0000, Colton Lewis wrote:
> For PMUv3, the register MDCR_EL2.HPMN partitiones the PMU counters
> into two ranges where counters 0..HPMN-1 are accessible by EL1 and, if
> allowed, EL0 while counters HPMN..N are only accessible by EL2.
>
> Introduce a module parameter in the PMUv3 driver to set this
> register. The name reserved_host_counters reflects the intent to
> reserve some counters for the host so the guest may eventually be
> allowed direct access to a subset of PMU functionality for increased
> performance.
>
> Track HPMN and whether the pmu is partitioned in struct arm_pmu
> because KVM will need to know that to handle guests correctly.
>
> While FEAT_HPMN0 does allow HPMN to be set to 0, this patch
> specifically disallows that case because it's not useful given the
> intention to allow guests access to their own counters.
Quite the contrary.
FEAT_HPMN0 is useful if userspace wants to provide a vPMU that has a
fixed cycle counter w/o event counters. Certain OSes refuse to boot
without it...
> static inline u32 read_mdcr(void)
> {
> return read_sysreg(HDCR);
> }
>
> static inline void write_mdcr(u32 val)
> {
> write_sysreg(val, HDCR);
> }
>
Hmm... While this fixes the 32bit compilation issues, it opens a new can
of worms.
VHE is a 64bit only feature, so you're *guaranteed* that these accessors
will undef (running at EL1).
> +static void armv8pmu_partition(u8 hpmn)
> +{
> + u64 mdcr = armv8pmu_mdcr_read();
> +
> + mdcr &= ~ARMV8_PMU_MDCR_HPMN;
> + mdcr |= FIELD_PREP(ARMV8_PMU_MDCR_HPMN, hpmn);
> + /* Prevent guest counters counting at EL2 */
> + mdcr |= ARMV8_PMU_MDCR_HPMD;
> +
> + armv8pmu_mdcr_write(mdcr);
> +}
> +
After giving this a read, I don't think the host PMU driver should care
about MDCR_EL2 at all. The only time that 'guest' events are loaded into
the PMU is between vcpu_load() / vcpu_put(), at which point *KVM* has
reconfigured MDCR_EL2.
I'm not sure if there's much involvement with the host PMU driver beyond
it pinky-swearing to only use the specified counters. KVM is what
actually will program HPMN.
That'd alleviate the PMU driver from having VHE awareness or caring
about MDCR_EL2.
--
Thanks,
Oliver
Hi Oliver, thanks for the review.
Oliver Upton <oliver.upton@linux.dev> writes:
> Hi Colton,
> On Sat, Feb 08, 2025 at 02:01:09AM +0000, Colton Lewis wrote:
>> For PMUv3, the register MDCR_EL2.HPMN partitiones the PMU counters
>> into two ranges where counters 0..HPMN-1 are accessible by EL1 and, if
>> allowed, EL0 while counters HPMN..N are only accessible by EL2.
>> Introduce a module parameter in the PMUv3 driver to set this
>> register. The name reserved_host_counters reflects the intent to
>> reserve some counters for the host so the guest may eventually be
>> allowed direct access to a subset of PMU functionality for increased
>> performance.
>> Track HPMN and whether the pmu is partitioned in struct arm_pmu
>> because KVM will need to know that to handle guests correctly.
>> While FEAT_HPMN0 does allow HPMN to be set to 0, this patch
>> specifically disallows that case because it's not useful given the
>> intention to allow guests access to their own counters.
> Quite the contrary.
> FEAT_HPMN0 is useful if userspace wants to provide a vPMU that has a
> fixed cycle counter w/o event counters. Certain OSes refuse to boot
> without it...
Cool. I'll make sure writing 0 is allowed if we have FEAT_HPMN0.
>> static inline u32 read_mdcr(void)
>> {
>> return read_sysreg(HDCR);
>> }
>> static inline void write_mdcr(u32 val)
>> {
>> write_sysreg(val, HDCR);
>> }
> Hmm... While this fixes the 32bit compilation issues, it opens a new can
> of worms.
> VHE is a 64bit only feature, so you're *guaranteed* that these accessors
> will undef (running at EL1).
True. I mentioned in the cover letter they aren't intended to actually
run in the PMU driver because I guard for VHE there.
>> +static void armv8pmu_partition(u8 hpmn)
>> +{
>> + u64 mdcr = armv8pmu_mdcr_read();
>> +
>> + mdcr &= ~ARMV8_PMU_MDCR_HPMN;
>> + mdcr |= FIELD_PREP(ARMV8_PMU_MDCR_HPMN, hpmn);
>> + /* Prevent guest counters counting at EL2 */
>> + mdcr |= ARMV8_PMU_MDCR_HPMD;
>> +
>> + armv8pmu_mdcr_write(mdcr);
>> +}
>> +
> After giving this a read, I don't think the host PMU driver should care
> about MDCR_EL2 at all. The only time that 'guest' events are loaded into
> the PMU is between vcpu_load() / vcpu_put(), at which point *KVM* has
> reconfigured MDCR_EL2.
> I'm not sure if there's much involvement with the host PMU driver beyond
> it pinky-swearing to only use the specified counters. KVM is what
> actually will program HPMN.
> That'd alleviate the PMU driver from having VHE awareness or caring
> about MDCR_EL2.
That does seem like a cleaner solution. I can lift that handling into
KVM code, but I will still need the variables I introduced in struct
arm_pmu to be populated so the driver knows what counters to use.
Without looking, I'm concerned there might be an initilization ordering
issue with that where KVM will get the value for HPMN first because it's
initialized first but then can't store them somewhere accessible to the
driver because the driver hasn't been initialized yet. Then the driver
is initialized and used without knowing HPMN and is now using counters
we wanted the guest to have.
There is probably an easy way around this, but I'll need to do some
digging.
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