arch/arm64/boot/dts/intel/Makefile | 1 + .../dts/intel/socfpga_agilex5_socdk_nand.dts | 89 +++++++++++++++++++ 2 files changed, 90 insertions(+) create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts
From: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
The Agilex5 devkit supports a separate NAND daughter card.
The NAND daughter card replaces the SDMMC slot that is on the default
daughter card thus requires a separate board dts file.
Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
---
changes in v2:
* Use nand flash node name according to dt bindings to fix dt build warnings.
* Arrange node in sequence.
Link to v1:https://lore.kernel.org/all/20250107084831.2750035-2-niravkumar.l.rabara@intel.com/
arch/arm64/boot/dts/intel/Makefile | 1 +
.../dts/intel/socfpga_agilex5_socdk_nand.dts | 89 +++++++++++++++++++
2 files changed, 90 insertions(+)
create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts
diff --git a/arch/arm64/boot/dts/intel/Makefile b/arch/arm64/boot/dts/intel/Makefile
index d39cfb723f5b..33f6d01266b1 100644
--- a/arch/arm64/boot/dts/intel/Makefile
+++ b/arch/arm64/boot/dts/intel/Makefile
@@ -3,5 +3,6 @@ dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_agilex_n6000.dtb \
socfpga_agilex_socdk.dtb \
socfpga_agilex_socdk_nand.dtb \
socfpga_agilex5_socdk.dtb \
+ socfpga_agilex5_socdk_nand.dtb \
socfpga_n5x_socdk.dtb
dtb-$(CONFIG_ARCH_KEEMBAY) += keembay-evm.dtb
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts
new file mode 100644
index 000000000000..ccc9be2cd7c6
--- /dev/null
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts
@@ -0,0 +1,89 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2025, Altera Corporation
+ */
+#include "socfpga_agilex5.dtsi"
+
+/ {
+ model = "SoCFPGA Agilex5 SoCDK";
+ compatible = "intel,socfpga-agilex5-socdk", "intel,socfpga-agilex5";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ led0 {
+ label = "hps_led0";
+ gpios = <&porta 6 GPIO_ACTIVE_HIGH>;
+ };
+
+ led1 {
+ label = "hps_led1";
+ gpios = <&porta 7 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ /* We expect the bootloader to fill in the reg */
+ reg = <0x0 0x80000000 0x0 0x0>;
+ };
+};
+
+&gpio0 {
+ status = "okay";
+};
+
+&gpio1 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&i3c0 {
+ status = "okay";
+};
+
+&i3c1 {
+ status = "okay";
+};
+
+&nand {
+ status = "okay";
+
+ nand@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0>;
+ nand-bus-width = <8>;
+
+ partition@0 {
+ label = "u-boot";
+ reg = <0 0x200000>;
+ };
+ partition@200000 {
+ label = "root";
+ reg = <0x200000 0xffe00000>;
+ };
+ };
+};
+
+&osc1 {
+ clock-frequency = <25000000>;
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&watchdog0 {
+ status = "okay";
+};
--
2.25.1
On 05/02/2025 11:13, niravkumar.l.rabara@intel.com wrote:
> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts
> new file mode 100644
> index 000000000000..ccc9be2cd7c6
> --- /dev/null
> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts
> @@ -0,0 +1,89 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2025, Altera Corporation
> + */
> +#include "socfpga_agilex5.dtsi"
> +
> +/ {
> + model = "SoCFPGA Agilex5 SoCDK";
> + compatible = "intel,socfpga-agilex5-socdk", "intel,socfpga-agilex5";
You cannot use other boards compatibles. Different device, different
compatible.
Best regards,
Krzysztof
Hi Krysztof,
> -----Original Message-----
> From: Krzysztof Kozlowski <krzk@kernel.org>
> Sent: Wednesday, 5 February, 2025 7:31 PM
> To: Rabara, Niravkumar L <niravkumar.l.rabara@intel.com>; Dinh Nguyen
> <dinguyen@kernel.org>; Rob Herring <robh@kernel.org>; Krzysztof Kozlowski
> <krzk+dt@kernel.org>; Conor Dooley <conor+dt@kernel.org>;
> nirav.rabara@altera.com; devicetree@vger.kernel.org; linux-
> kernel@vger.kernel.org
> Subject: Re: [PATCH v2] arm64: dts: socfpga: agilex5: add NAND board file
>
> On 05/02/2025 11:13, niravkumar.l.rabara@intel.com wrote:
> > diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts
> > b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts
> > new file mode 100644
> > index 000000000000..ccc9be2cd7c6
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts
> > @@ -0,0 +1,89 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright (C) 2025, Altera Corporation */ #include
> > +"socfpga_agilex5.dtsi"
> > +
> > +/ {
> > + model = "SoCFPGA Agilex5 SoCDK";
> > + compatible = "intel,socfpga-agilex5-socdk", "intel,socfpga-agilex5";
>
>
> You cannot use other boards compatibles. Different device, different
> compatible.
>
Same Agilex5 development kit board supports a separate NAND
daughter card.
Default daughter card with SDMMC on Agilex5 devkit required to
replaced with this NAND daughter card to use NAND flash with
Agilex5 devkit.
Maybe I should replace the "NAND board" to "NAND daughter board"
for the patch title.
Is this reasonable?
Thanks,
Nirav
On 05/02/2025 14:43, Rabara, Niravkumar L wrote:
> Hi Krysztof,
>
>> -----Original Message-----
>> From: Krzysztof Kozlowski <krzk@kernel.org>
>> Sent: Wednesday, 5 February, 2025 7:31 PM
>> To: Rabara, Niravkumar L <niravkumar.l.rabara@intel.com>; Dinh Nguyen
>> <dinguyen@kernel.org>; Rob Herring <robh@kernel.org>; Krzysztof Kozlowski
>> <krzk+dt@kernel.org>; Conor Dooley <conor+dt@kernel.org>;
>> nirav.rabara@altera.com; devicetree@vger.kernel.org; linux-
>> kernel@vger.kernel.org
>> Subject: Re: [PATCH v2] arm64: dts: socfpga: agilex5: add NAND board file
>>
>> On 05/02/2025 11:13, niravkumar.l.rabara@intel.com wrote:
>>> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts
>>> b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts
>>> new file mode 100644
>>> index 000000000000..ccc9be2cd7c6
>>> --- /dev/null
>>> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts
>>> @@ -0,0 +1,89 @@
>>> +// SPDX-License-Identifier: GPL-2.0
>>> +/*
>>> + * Copyright (C) 2025, Altera Corporation */ #include
>>> +"socfpga_agilex5.dtsi"
>>> +
>>> +/ {
>>> + model = "SoCFPGA Agilex5 SoCDK";
>>> + compatible = "intel,socfpga-agilex5-socdk", "intel,socfpga-agilex5";
>>
>>
>> You cannot use other boards compatibles. Different device, different
>> compatible.
>>
>
> Same Agilex5 development kit board supports a separate NAND
> daughter card.
> Default daughter card with SDMMC on Agilex5 devkit required to
> replaced with this NAND daughter card to use NAND flash with
> Agilex5 devkit.
So different boards?
>
> Maybe I should replace the "NAND board" to "NAND daughter board"
> for the patch title.
>
> Is this reasonable?
Yeah, would be better, but I was not commenting about that. Define what
is the hardware here and use proper compatibles.
Best regards,
Krzysztof
Hi Krysztof, > -----Original Message----- > From: Krzysztof Kozlowski <krzk@kernel.org> > Sent: Thursday, 6 February, 2025 12:36 AM > To: Rabara, Niravkumar L <niravkumar.l.rabara@intel.com>; Dinh Nguyen > <dinguyen@kernel.org>; Rob Herring <robh@kernel.org>; Krzysztof Kozlowski > <krzk+dt@kernel.org>; Conor Dooley <conor+dt@kernel.org>; > nirav.rabara@altera.com; devicetree@vger.kernel.org; linux- > kernel@vger.kernel.org > Subject: Re: [PATCH v2] arm64: dts: socfpga: agilex5: add NAND board file > > >>> + model = "SoCFPGA Agilex5 SoCDK"; > >>> + compatible = "intel,socfpga-agilex5-socdk", > >>> +"intel,socfpga-agilex5"; > >> > >> > >> You cannot use other boards compatibles. Different device, different > >> compatible. > >> > > > > Same Agilex5 development kit board supports a separate NAND daughter > > card. > > Default daughter card with SDMMC on Agilex5 devkit required to > > replaced with this NAND daughter card to use NAND flash with > > Agilex5 devkit. > > > So different boards? > > > > > Maybe I should replace the "NAND board" to "NAND daughter board" > > for the patch title. > > > > Is this reasonable? > > > Yeah, would be better, but I was not commenting about that. Define what is the > hardware here and use proper compatibles. > Got it. I was under the wrong impression that daughter board can use the base board compatibles. I will add the NAND board's compatible to the bindings and use it here in v3. Thanks, Nirav
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