arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+)
From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Add OPP table for the Renesas RZ/G3S SoC.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
This depends on https://lore.kernel.org/all/20250115142059.1833063-1-claudiu.beznea.uj@bp.renesas.com
arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 28 ++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
index a9b98db9ef95..50cdad52ca75 100644
--- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
@@ -28,6 +28,33 @@ audio_clk2: audio2-clk {
clock-frequency = <0>;
};
+ cluster0_opp: opp-table-0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-137500000 {
+ opp-hz = /bits/ 64 <137500000>;
+ opp-microvolt = <940000>;
+ clock-latency-ns = <300000>;
+ };
+ opp-275000000 {
+ opp-hz = /bits/ 64 <275000000>;
+ opp-microvolt = <940000>;
+ clock-latency-ns = <300000>;
+ };
+ opp-550000000 {
+ opp-hz = /bits/ 64 <550000000>;
+ opp-microvolt = <940000>;
+ clock-latency-ns = <300000>;
+ };
+ opp-1100000000 {
+ opp-hz = /bits/ 64 <1100000000>;
+ opp-microvolt = <940000>;
+ clock-latency-ns = <300000>;
+ opp-suspend;
+ };
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -40,6 +67,7 @@ cpu0: cpu@0 {
next-level-cache = <&L3_CA55>;
enable-method = "psci";
clocks = <&cpg CPG_CORE R9A08G045_CLK_I>;
+ operating-points-v2 = <&cluster0_opp>;
};
L3_CA55: cache-controller-0 {
--
2.43.0Hi Claudiu,
CC Energy Model
On Tue, 28 Jan 2025 at 15:56, Claudiu <claudiu.beznea@tuxon.dev> wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>
> Add OPP table for the Renesas RZ/G3S SoC.
>
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Thanks for your patch!
> --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
> @@ -28,6 +28,33 @@ audio_clk2: audio2-clk {
> clock-frequency = <0>;
> };
>
> + cluster0_opp: opp-table-0 {
> + compatible = "operating-points-v2";
> + opp-shared;
> +
> + opp-137500000 {
> + opp-hz = /bits/ 64 <137500000>;
> + opp-microvolt = <940000>;
> + clock-latency-ns = <300000>;
> + };
> + opp-275000000 {
> + opp-hz = /bits/ 64 <275000000>;
> + opp-microvolt = <940000>;
> + clock-latency-ns = <300000>;
> + };
> + opp-550000000 {
> + opp-hz = /bits/ 64 <550000000>;
> + opp-microvolt = <940000>;
> + clock-latency-ns = <300000>;
> + };
> + opp-1100000000 {
> + opp-hz = /bits/ 64 <1100000000>;
> + opp-microvolt = <940000>;
> + clock-latency-ns = <300000>;
> + opp-suspend;
> + };
So all voltages are the same. This means the Energy Model (if enabled)
will always pick the operating point with the highest clock rate, just
like on R-Car E3 and RZ/G2E. Apparently that can be fixed by using
"opp-microwatt" instead, but I am still waiting for feedback about
some practical points[1] (yes, the Ebisu-4D is still on my desk for
this reason, and thus unavailable for remote access).
Thanks!
> + };
> +
> cpus {
> #address-cells = <1>;
> #size-cells = <0>;
> @@ -40,6 +67,7 @@ cpu0: cpu@0 {
> next-level-cache = <&L3_CA55>;
> enable-method = "psci";
> clocks = <&cpg CPG_CORE R9A08G045_CLK_I>;
> + operating-points-v2 = <&cluster0_opp>;
> };
>
> L3_CA55: cache-controller-0 {
[1] https://lore.kernel.org/linux-renesas-soc/cover.1728377971.git.geert+renesas@glider.be
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
On Thu, 6 Feb 2025 at 09:26, Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> CC Energy Model
>
> On Tue, 28 Jan 2025 at 15:56, Claudiu <claudiu.beznea@tuxon.dev> wrote:
> > From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> >
> > Add OPP table for the Renesas RZ/G3S SoC.
> >
> > Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>
> Thanks for your patch!
>
> > --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
> > @@ -28,6 +28,33 @@ audio_clk2: audio2-clk {
> > clock-frequency = <0>;
> > };
> >
> > + cluster0_opp: opp-table-0 {
> > + compatible = "operating-points-v2";
> > + opp-shared;
> > +
> > + opp-137500000 {
> > + opp-hz = /bits/ 64 <137500000>;
> > + opp-microvolt = <940000>;
> > + clock-latency-ns = <300000>;
> > + };
> > + opp-275000000 {
> > + opp-hz = /bits/ 64 <275000000>;
> > + opp-microvolt = <940000>;
> > + clock-latency-ns = <300000>;
> > + };
> > + opp-550000000 {
> > + opp-hz = /bits/ 64 <550000000>;
> > + opp-microvolt = <940000>;
> > + clock-latency-ns = <300000>;
> > + };
> > + opp-1100000000 {
> > + opp-hz = /bits/ 64 <1100000000>;
> > + opp-microvolt = <940000>;
> > + clock-latency-ns = <300000>;
> > + opp-suspend;
> > + };
>
> So all voltages are the same. This means the Energy Model (if enabled)
> will always pick the operating point with the highest clock rate, just
> like on R-Car E3 and RZ/G2E. Apparently that can be fixed by using
> "opp-microwatt" instead, but I am still waiting for feedback about
> some practical points[1] (yes, the Ebisu-4D is still on my desk for
> this reason, and thus unavailable for remote access).
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v6.15.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
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