Enable cpufreq for IPQ5424

[PATCH 1/4] dt-bindings: clock: ipq5424-apss-clk: Add ipq5424 apss clock controller

Posted by Sricharan R 3 days, 9 hours ago

From: Sricharan Ramabadhran <quic_srichara@quicinc.com>

The CPU core in ipq5424 is clocked by a huayra PLL with RCG support.
The RCG and PLL have a separate register space from the GCC.
Also the L3 cache has a separate pll and needs to be scaled along
with the CPU.

Co-developed-by: Md Sadre Alam <quic_mdalam@quicinc.com>
Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
---
 .../bindings/clock/qcom,ipq5424-apss-clk.yaml | 57 +++++++++++++++++++
 include/dt-bindings/clock/qcom,apss-ipq.h     |  6 ++
 2 files changed, 63 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/qcom,ipq5424-apss-clk.yaml

diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq5424-apss-clk.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq5424-apss-clk.yaml
new file mode 100644
index 000000000000..df7cfb82bac3
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,ipq5424-apss-clk.yaml
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,ipq5424-apss-clk.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm APSS IPQ5424 Clock Controller
+
+maintainers:
+  - Sricharan Ramabadhran <quic_srichara@quicinc.com>
+  - Md Sadre Alam <quic_mdalam@quicinc.com>
+
+description: |
+  The CPU core in ipq5424 is clocked by a huayra PLL with RCG support.
+  The RCG and PLL have a separate register space from the GCC.
+
+properties:
+  compatible:
+    enum:
+      - qcom,ipq5424-apss-clk
+  reg:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: Reference to the XO clock.
+      - description: Reference to the GPLL0 clock.
+
+  clock-names:
+    items:
+      - const: xo
+      - const: gpll0
+
+  '#clock-cells':
+    const: 1
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/qcom,ipq5424-gcc.h>
+
+    apss_clk: apss-clock@fa80000 {
+      compatible = "qcom,ipq5424-apss-clk";
+      reg = <0x0fa80000 0x20000>;
+      clocks = <&xo_board>, <&gcc GPLL0>;
+      clock-names = "xo", "gpll0";
+      #clock-cells = <1>;
+    };
+
diff --git a/include/dt-bindings/clock/qcom,apss-ipq.h b/include/dt-bindings/clock/qcom,apss-ipq.h
index 77b6e05492e2..0bb41e5efdef 100644
--- a/include/dt-bindings/clock/qcom,apss-ipq.h
+++ b/include/dt-bindings/clock/qcom,apss-ipq.h
@@ -8,5 +8,11 @@
 
 #define APCS_ALIAS0_CLK_SRC			0
 #define APCS_ALIAS0_CORE_CLK			1
+#define APSS_PLL_EARLY				2
+#define APSS_SILVER_CLK_SRC			3
+#define APSS_SILVER_CORE_CLK			4
+#define L3_PLL					5
+#define L3_CLK_SRC				6
+#define L3_CORE_CLK				7
 
 #endif
-- 
2.34.1

Re: [PATCH 1/4] dt-bindings: clock: ipq5424-apss-clk: Add ipq5424 apss clock controller

Posted by Krzysztof Kozlowski 2 days, 11 hours ago

On 27/01/2025 10:31, Sricharan R wrote:
> From: Sricharan Ramabadhran <quic_srichara@quicinc.com>
> 
> The CPU core in ipq5424 is clocked by a huayra PLL with RCG support.
> The RCG and PLL have a separate register space from the GCC.
> Also the L3 cache has a separate pll and needs to be scaled along
> with the CPU.
> 
> Co-developed-by: Md Sadre Alam <quic_mdalam@quicinc.com>
> Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>

Considering that there were multiple conflicting patches coming from
Qualcomm around IPQ SoCs and that we are in the merge window, I will
skip this patch.

I suspect this duplicates the other chip as well, but that's your task
to sync up internally.

Best regards,
Krzysztof

Re: [PATCH 1/4] dt-bindings: clock: ipq5424-apss-clk: Add ipq5424 apss clock controller

Posted by Sricharan Ramabadhran 2 days, 7 hours ago


On 1/28/2025 1:04 PM, Krzysztof Kozlowski wrote:
> On 27/01/2025 10:31, Sricharan R wrote:
>> From: Sricharan Ramabadhran <quic_srichara@quicinc.com>
>>
>> The CPU core in ipq5424 is clocked by a huayra PLL with RCG support.
>> The RCG and PLL have a separate register space from the GCC.
>> Also the L3 cache has a separate pll and needs to be scaled along
>> with the CPU.
>>
>> Co-developed-by: Md Sadre Alam <quic_mdalam@quicinc.com>
>> Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
>> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
> 
> Considering that there were multiple conflicting patches coming from
> Qualcomm around IPQ SoCs and that we are in the merge window, I will
> skip this patch.
> 
> I suspect this duplicates the other chip as well, but that's your task
> to sync up internally.
> 
ok, but this .yaml is specific to IPQ5424 and would not conflict with
IPQ5332. That said, will post it after merge window as a part of
V3 (for other patch changes) to avoid any confusion.

Regards,
  Sricharan

Re: [PATCH 1/4] dt-bindings: clock: ipq5424-apss-clk: Add ipq5424 apss clock controller

Posted by Krzysztof Kozlowski 2 days, 6 hours ago

On 28/01/2025 12:15, Sricharan Ramabadhran wrote:
> 
> 
> On 1/28/2025 1:04 PM, Krzysztof Kozlowski wrote:
>> On 27/01/2025 10:31, Sricharan R wrote:
>>> From: Sricharan Ramabadhran <quic_srichara@quicinc.com>
>>>
>>> The CPU core in ipq5424 is clocked by a huayra PLL with RCG support.
>>> The RCG and PLL have a separate register space from the GCC.
>>> Also the L3 cache has a separate pll and needs to be scaled along
>>> with the CPU.
>>>
>>> Co-developed-by: Md Sadre Alam <quic_mdalam@quicinc.com>
>>> Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
>>> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
>>
>> Considering that there were multiple conflicting patches coming from
>> Qualcomm around IPQ SoCs and that we are in the merge window, I will
>> skip this patch.
>>
>> I suspect this duplicates the other chip as well, but that's your task
>> to sync up internally.
>>
> ok, but this .yaml is specific to IPQ5424 and would not conflict with
> IPQ5332. That said, will post it after merge window as a part of
> V3 (for other patch changes) to avoid any confusion.


But maybe it is the same on ipq5332? or similar? Other works were
totally de-synced and you ask community to sync them. That's not how it
works.

Best regards,
Krzysztof

Re: [PATCH 1/4] dt-bindings: clock: ipq5424-apss-clk: Add ipq5424 apss clock controller

Posted by Sricharan Ramabadhran 8 hours ago


On 1/28/2025 6:00 PM, Krzysztof Kozlowski wrote:
> On 28/01/2025 12:15, Sricharan Ramabadhran wrote:
>>
>>
>> On 1/28/2025 1:04 PM, Krzysztof Kozlowski wrote:
>>> On 27/01/2025 10:31, Sricharan R wrote:
>>>> From: Sricharan Ramabadhran <quic_srichara@quicinc.com>
>>>>
>>>> The CPU core in ipq5424 is clocked by a huayra PLL with RCG support.
>>>> The RCG and PLL have a separate register space from the GCC.
>>>> Also the L3 cache has a separate pll and needs to be scaled along
>>>> with the CPU.
>>>>
>>>> Co-developed-by: Md Sadre Alam <quic_mdalam@quicinc.com>
>>>> Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
>>>> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
>>>
>>> Considering that there were multiple conflicting patches coming from
>>> Qualcomm around IPQ SoCs and that we are in the merge window, I will
>>> skip this patch.
>>>
>>> I suspect this duplicates the other chip as well, but that's your task
>>> to sync up internally.
>>>
>> ok, but this .yaml is specific to IPQ5424 and would not conflict with
>> IPQ5332. That said, will post it after merge window as a part of
>> V3 (for other patch changes) to avoid any confusion.
> 
> 
> But maybe it is the same on ipq5332? or similar? Other works were
> totally de-synced and you ask community to sync them. That's not how it
> works.

This is different from ipq5332, hence we cannot re-use and would have
no conflicts as well.

Regards,
  Sricharan