Add basic support for the MyIR Remi Pi (based on r9a07g044l2):
- UART
- i2c
- emmc
- USB host
- HDMI output
- Ethernet
Signed-off-by: Julien Massot <julien.massot@collabora.com>
---
arch/arm64/boot/dts/renesas/Makefile | 1 +
.../arm64/boot/dts/renesas/r9a07g044l2-remi-pi.dts | 388 +++++++++++++++++++++
2 files changed, 389 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
index 97228a3cb99c163d299b508ee7653aafea3d1a3a..6824c63a1b154acf13de7e3d44bb10d5754738c4 100644
--- a/arch/arm64/boot/dts/renesas/Makefile
+++ b/arch/arm64/boot/dts/renesas/Makefile
@@ -126,6 +126,7 @@ dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-smarc-cru-csi-ov5645.dtbo
r9a07g044c2-smarc-cru-csi-ov5645-dtbs := r9a07g044c2-smarc.dtb r9a07g044c2-smarc-cru-csi-ov5645.dtbo
dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-smarc-cru-csi-ov5645.dtb
+dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-remi-pi.dtb
dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-smarc.dtb
dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-smarc-cru-csi-ov5645.dtbo
r9a07g044l2-smarc-cru-csi-ov5645-dtbs := r9a07g044l2-smarc.dtb r9a07g044l2-smarc-cru-csi-ov5645.dtbo
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044l2-remi-pi.dts b/arch/arm64/boot/dts/renesas/r9a07g044l2-remi-pi.dts
new file mode 100644
index 0000000000000000000000000000000000000000..57d318ded704a970c09fd8f7205ccf7bc221e318
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r9a07g044l2-remi-pi.dts
@@ -0,0 +1,388 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the MYiR Remi Pi
+ *
+ * Copyright (C) 2022 MYiR Electronics Corp.
+ * Copyright (C) 2025 Collabora Ltd.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
+
+#include "r9a07g044l2.dtsi"
+
+/ {
+ model = "MYIR Tech Limited Remi Pi MYB-YG2LX-REMI";
+ compatible = "myir,remi-pi", "renesas,r9a07g044l2", "renesas,r9a07g044";
+
+ aliases {
+ ethernet0 = ð0;
+ ethernet1 = ð1;
+
+ serial0 = &scif0;
+ serial1 = &scif1;
+ serial2 = &scif2;
+ serial3 = &scif3;
+
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+
+ mmc0 = &sdhi0;
+ mmc1 = &sdhi1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@48000000 {
+ device_type = "memory";
+ /* first 128MB is reserved for secure area. */
+ reg = <0x0 0x48000000 0x0 0x38000000>;
+ };
+
+ reg_5p0v: regulator-5p0v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-5.0V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-3.3V";
+ vin-supply = <®_5p0v>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ reg_1p8v: regulator-1p8v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-1.8V";
+ vin-supply = <®_3p3v>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ reg_1p1v: regulator-vdd-core {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-1.1V";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-always-on;
+ };
+
+ hdmi-out {
+ compatible = "hdmi-connector";
+ type = "a";
+ ddc-i2c-bus = <&i2c1>;
+
+ port {
+ hdmi_con: endpoint {
+ remote-endpoint = <<8912_out>;
+ };
+ };
+ };
+};
+
+ð0 {
+ pinctrl-0 = <ð0_pins>;
+ pinctrl-names = "default";
+ phy-handle = <&phy0>;
+ phy-mode = "rgmii-id";
+ status = "okay";
+
+ phy0: ethernet-phy@4 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <4>;
+ interrupts-extended = <&pinctrl RZG2L_GPIO(44, 2) IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+ð1 {
+ pinctrl-0 = <ð1_pins>;
+ pinctrl-names = "default";
+ phy-handle = <&phy1>;
+ phy-mode = "rgmii-id";
+ status = "okay";
+
+ phy1: ethernet-phy@6 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <6>;
+ interrupts-extended = <&pinctrl RZG2L_GPIO(43, 2) IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+&extal_clk {
+ clock-frequency = <24000000>;
+};
+
+&gpu {
+ mali-supply = <®_1p1v>;
+};
+
+&ostm1 {
+ status = "okay";
+};
+
+&ostm2 {
+ status = "okay";
+};
+
+&pinctrl {
+ i2c0_pins: i2c0 {
+ pins = "RIIC0_SDA", "RIIC0_SCL";
+ input-enable;
+ };
+
+ i2c1_pins: i2c1 {
+ pins = "RIIC1_SDA", "RIIC1_SCL";
+ input-enable;
+ };
+
+ i2c2_pins: i2c2 {
+ pinmux = <RZG2L_PORT_PINMUX(3, 0, 2)>, /* SDA */
+ <RZG2L_PORT_PINMUX(3, 1, 2)>; /* SCL */
+ };
+
+ i2c3_pins: i2c3 {
+ pinmux = <RZG2L_PORT_PINMUX(18, 0, 3)>, /* SDA */
+ <RZG2L_PORT_PINMUX(18, 1, 3)>; /* SCL */
+ };
+
+ spi0_pins: spi0 {
+ pinmux = <RZG2L_PORT_PINMUX(47, 0, 5)>, /* CLK */
+ <RZG2L_PORT_PINMUX(47, 1, 5)>, /* MOSI */
+ <RZG2L_PORT_PINMUX(47, 2, 5)>, /* MISO */
+ <RZG2L_PORT_PINMUX(47, 3, 5)>; /* Chip Enable*/
+ };
+
+ eth0_pins: eth0 {
+ pinmux = <RZG2L_PORT_PINMUX(27, 1, 1)>, /* ET0_MDC */
+ <RZG2L_PORT_PINMUX(28, 0, 1)>, /* ET0_MDIO */
+ <RZG2L_PORT_PINMUX(20, 0, 1)>, /* ET0_TXC */
+ <RZG2L_PORT_PINMUX(20, 1, 1)>, /* ET0_TX_CTL */
+ <RZG2L_PORT_PINMUX(20, 2, 1)>, /* ET0_TXD0 */
+ <RZG2L_PORT_PINMUX(21, 0, 1)>, /* ET0_TXD1 */
+ <RZG2L_PORT_PINMUX(21, 1, 1)>, /* ET0_TXD2 */
+ <RZG2L_PORT_PINMUX(22, 0, 1)>, /* ET0_TXD3 */
+ <RZG2L_PORT_PINMUX(24, 0, 1)>, /* ET0_RXC */
+ <RZG2L_PORT_PINMUX(24, 1, 1)>, /* ET0_RX_CTL */
+ <RZG2L_PORT_PINMUX(25, 0, 1)>, /* ET0_RXD0 */
+ <RZG2L_PORT_PINMUX(25, 1, 1)>, /* ET0_RXD1 */
+ <RZG2L_PORT_PINMUX(26, 0, 1)>, /* ET0_RXD2 */
+ <RZG2L_PORT_PINMUX(26, 1, 1)>; /* ET0_RXD3 */
+ };
+
+ eth1_pins: eth1 {
+ pinmux = <RZG2L_PORT_PINMUX(37, 0, 1)>, /* ET1_MDC */
+ <RZG2L_PORT_PINMUX(37, 1, 1)>, /* ET1_MDIO */
+ <RZG2L_PORT_PINMUX(29, 0, 1)>, /* ET1_TXC */
+ <RZG2L_PORT_PINMUX(29, 1, 1)>, /* ET1_TX_CTL */
+ <RZG2L_PORT_PINMUX(30, 0, 1)>, /* ET1_TXD0 */
+ <RZG2L_PORT_PINMUX(30, 1, 1)>, /* ET1_TXD1 */
+ <RZG2L_PORT_PINMUX(31, 0, 1)>, /* ET1_TXD2 */
+ <RZG2L_PORT_PINMUX(31, 1, 1)>, /* ET1_TXD3 */
+ <RZG2L_PORT_PINMUX(33, 1, 1)>, /* ET1_RXC */
+ <RZG2L_PORT_PINMUX(34, 0, 1)>, /* ET1_RX_CTL */
+ <RZG2L_PORT_PINMUX(34, 1, 1)>, /* ET1_RXD0 */
+ <RZG2L_PORT_PINMUX(35, 0, 1)>, /* ET1_RXD1 */
+ <RZG2L_PORT_PINMUX(35, 1, 1)>, /* ET1_RXD2 */
+ <RZG2L_PORT_PINMUX(36, 0, 1)>; /* ET1_RXD3 */
+ };
+
+ sdhi0_pins: sd0 {
+ sd0_data {
+ pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3",
+ "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7";
+ power-source = <1800>;
+ };
+
+ sd0_ctrl {
+ pins = "SD0_CLK", "SD0_CMD";
+ power-source = <1800>;
+ };
+
+ sd0_rst {
+ pins = "SD0_RST#";
+ power-source = <1800>;
+ };
+ };
+
+ sdhi0_pins_uhs: sd0_uhs {
+ sd0_data_uhs {
+ pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3",
+ "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7";
+ power-source = <1800>;
+ };
+
+ sd0_ctrl_uhs {
+ pins = "SD0_CLK", "SD0_CMD";
+ power-source = <1800>;
+ };
+
+ sd0_rst_uhs {
+ pins = "SD0_RST#";
+ power-source = <1800>;
+ };
+ };
+
+ usb1_pins: usb1 {
+ pinmux = <RZG2L_PORT_PINMUX(42, 0, 1)>, /* VBUS */
+ <RZG2L_PORT_PINMUX(42, 1, 1)>; /* OVC */
+ };
+
+ scif0_pins: scif0 {
+ pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>, /* TxD */
+ <RZG2L_PORT_PINMUX(38, 1, 1)>; /* RxD */
+ };
+
+ scif1_pins: scif1 {
+ pinmux = <RZG2L_PORT_PINMUX(40, 0, 1)>, /* TxD */
+ <RZG2L_PORT_PINMUX(40, 1, 1)>; /* RxD */
+ };
+
+ scif2_pins: scif2 {
+ pinmux = <RZG2L_PORT_PINMUX(48, 0, 1)>, /* TxD */
+ <RZG2L_PORT_PINMUX(48, 1, 1)>; /* RxD */
+ };
+
+ scif3_pins: scif3 {
+ pinmux = <RZG2L_PORT_PINMUX(0, 0, 5)>, /* TxD */
+ <RZG2L_PORT_PINMUX(0, 1, 5)>; /* RxD */
+ };
+};
+
+&sdhi0 {
+ pinctrl-0 = <&sdhi0_pins>;
+ pinctrl-1 = <&sdhi0_pins_uhs>;
+ pinctrl-names = "default", "state_uhs";
+
+ vmmc-supply = <®_3p3v>;
+ vqmmc-supply = <®_1p8v>;
+ bus-width = <8>;
+ mmc-hs200-1_8v;
+ non-removable;
+ fixed-emmc-driver-type = <1>;
+ status = "okay";
+};
+
+&usb2_phy1 {
+ pinctrl-0 = <&usb1_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&dsi {
+ status = "okay";
+ ports {
+ port@1 {
+ dsi_out: endpoint {
+ remote-endpoint = <<8912_in>;
+ data-lanes = <1 2 3 4>;
+ };
+ };
+ };
+};
+
+&du {
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-0 = <&i2c0_pins>;
+ pinctrl-names = "default";
+
+ clock-frequency = <400000>;
+ status = "okay";
+
+ hdmi-bridge@48 {
+ compatible = "lontium,lt8912b";
+ reg = <0x48> ;
+ reset-gpios = <&pinctrl RZG2L_GPIO(42, 2) GPIO_ACTIVE_LOW>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ lt8912_in: endpoint {
+ data-lanes = <1 2 3 4>;
+ remote-endpoint = <&dsi_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ lt8912_out: endpoint {
+ remote-endpoint = <&hdmi_con>;
+ };
+ };
+ };
+ };
+};
+
+&i2c1 {
+ pinctrl-0 = <&i2c1_pins>;
+ pinctrl-names = "default";
+ clock-frequency = <100000>;
+ status = "okay";
+};
+
+&i2c2 {
+ pinctrl-0 = <&i2c2_pins>;
+ pinctrl-names = "default";
+ clock-frequency = <100000>;
+ status = "okay";
+};
+
+&i2c3 {
+ pinctrl-0 = <&i2c3_pins>;
+ pinctrl-names = "default";
+ clock-frequency = <100000>;
+ status = "okay";
+};
+
+&scif0 {
+ pinctrl-0 = <&scif0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&scif2 {
+ pinctrl-0 = <&scif2_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&scif3 {
+ pinctrl-0 = <&scif3_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&phyrst {
+ status = "okay";
+};
+
+&mtu3 {
+ status = "okay";
+};
--
2.47.1Hi Julien,
On Mon, 27 Jan 2025 at 10:39, Julien Massot <julien.massot@collabora.com> wrote:
> Add basic support for the MyIR Remi Pi (based on r9a07g044l2):
> - UART
> - i2c
> - emmc
> - USB host
> - HDMI output
> - Ethernet
>
> Signed-off-by: Julien Massot <julien.massot@collabora.com>
Thanks for your patch!
> --- /dev/null
> +++ b/arch/arm64/boot/dts/renesas/r9a07g044l2-remi-pi.dts
> @@ -0,0 +1,388 @@
> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +/*
> + * Device Tree Source for the MYiR Remi Pi
> + *
> + * Copyright (C) 2022 MYiR Electronics Corp.
> + * Copyright (C) 2025 Collabora Ltd.
> + */
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
> +
> +#include "r9a07g044l2.dtsi"
> +
> +/ {
> + model = "MYIR Tech Limited Remi Pi MYB-YG2LX-REMI";
> + compatible = "myir,remi-pi", "renesas,r9a07g044l2", "renesas,r9a07g044";
> +
> + aliases {
> + ethernet0 = ð0;
> + ethernet1 = ð1;
> +
> + serial0 = &scif0;
So serial0 is the CA55 console, OK.
> + serial1 = &scif1;
Connected to BT/WiFi, but not yet enabled below.
> + serial2 = &scif2;
This is wired to the Raspberri Pi expansion connector.
However, on Raspberri Pi, these pins are GPIOs.
While the Raspberri Pi UART_[TR]X pins are wired to SCIF4 here,
which is not yet enabled...
> + serial3 = &scif3;
Serial3 is the CA33 debug console, OK.
> +
> + i2c0 = &i2c0;
> + i2c1 = &i2c1;
> + i2c2 = &i2c2;
> + i2c3 = &i2c3;
> +
> + mmc0 = &sdhi0;
> + mmc1 = &sdhi1;
sdhi1 is not yet enabled, so please drop it.
> + };
> + reg_5p0v: regulator-5p0v {
> + compatible = "regulator-fixed";
> + regulator-name = "fixed-5.0V";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + };
> +
> + reg_3p3v: regulator-3p3v {
> + compatible = "regulator-fixed";
> + regulator-name = "fixed-3.3V";
> + vin-supply = <®_5p0v>;
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + };
> +
> + reg_1p8v: regulator-1p8v {
> + compatible = "regulator-fixed";
> + regulator-name = "fixed-1.8V";
> + vin-supply = <®_3p3v>;
reg_5p0v, as 1.8V is generated from 5.0V, according to the schematics.
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-always-on;
> + };
> +
> + reg_1p1v: regulator-vdd-core {
> + compatible = "regulator-fixed";
> + regulator-name = "fixed-1.1V";
> + regulator-min-microvolt = <1100000>;
> + regulator-max-microvolt = <1100000>;
> + regulator-always-on;
> + };
> +ð0 {
> + pinctrl-0 = <ð0_pins>;
> + pinctrl-names = "default";
> + phy-handle = <&phy0>;
> + phy-mode = "rgmii-id";
> + status = "okay";
> +
> + phy0: ethernet-phy@4 {
> + compatible = "ethernet-phy-ieee802.3-c22";
> + reg = <4>;
> + interrupts-extended = <&pinctrl RZG2L_GPIO(44, 2) IRQ_TYPE_LEVEL_LOW>;
Missing reset-gpios (P44_3).
> + };
> +};
> +
> +ð1 {
> + pinctrl-0 = <ð1_pins>;
> + pinctrl-names = "default";
> + phy-handle = <&phy1>;
> + phy-mode = "rgmii-id";
> + status = "okay";
> +
> + phy1: ethernet-phy@6 {
> + compatible = "ethernet-phy-ieee802.3-c22";
> + reg = <6>;
> + interrupts-extended = <&pinctrl RZG2L_GPIO(43, 2) IRQ_TYPE_LEVEL_LOW>;
Missing reset-gpios (P43_3).
> + };
> +};
> +&pinctrl {
> + spi0_pins: spi0 {
> + pinmux = <RZG2L_PORT_PINMUX(47, 0, 5)>, /* CLK */
> + <RZG2L_PORT_PINMUX(47, 1, 5)>, /* MOSI */
> + <RZG2L_PORT_PINMUX(47, 2, 5)>, /* MISO */
> + <RZG2L_PORT_PINMUX(47, 3, 5)>; /* Chip Enable*/
> + };
Unused.
> +
> + eth0_pins: eth0 {
Please sort pinctrl subnodes (alphabetically by node name).
> + sdhi0_pins: sd0 {
> + sd0_data {
> + pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3",
> + "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7";
> + power-source = <1800>;
> + };
> +
> + sd0_ctrl {
> + pins = "SD0_CLK", "SD0_CMD";
> + power-source = <1800>;
> + };
> +
> + sd0_rst {
> + pins = "SD0_RST#";
> + power-source = <1800>;
> + };
> + };
> +
> + sdhi0_pins_uhs: sd0_uhs {
> + sd0_data_uhs {
> + pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3",
> + "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7";
> + power-source = <1800>;
> + };
> +
> + sd0_ctrl_uhs {
> + pins = "SD0_CLK", "SD0_CMD";
> + power-source = <1800>;
> + };
> +
> + sd0_rst_uhs {
> + pins = "SD0_RST#";
> + power-source = <1800>;
> + };
> + };
sd0 and sd0_uhs are identical, so you can just always use the former,
and drop the latter.
> +
> + usb1_pins: usb1 {
> + pinmux = <RZG2L_PORT_PINMUX(42, 0, 1)>, /* VBUS */
> + <RZG2L_PORT_PINMUX(42, 1, 1)>; /* OVC */
These two pins don't seem to be exposed on the SoM.
Perhaps this is wired on the SoM?
> + };
> +
> + scif0_pins: scif0 {
> + pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>, /* TxD */
> + <RZG2L_PORT_PINMUX(38, 1, 1)>; /* RxD */
> + };
> +
> + scif1_pins: scif1 {
> + pinmux = <RZG2L_PORT_PINMUX(40, 0, 1)>, /* TxD */
> + <RZG2L_PORT_PINMUX(40, 1, 1)>; /* RxD */
> + };
SCIF1 is connected to BT/WiFi, and the CTS/RTS pins should be included.
However, for now SCIF1 is not yet enabled, so please everything related to it.
> +&usb2_phy1 {
> + pinctrl-0 = <&usb1_pins>;
> + pinctrl-names = "default";
> +
> + status = "okay";
> +};
> +
> +&ehci1 {
Please sort references to nodes (alphabetically). More below...
> +&dsi {
> + status = "okay";
Please insert a blank line.
> + ports {
> +&i2c0 {
> + pinctrl-0 = <&i2c0_pins>;
> + pinctrl-names = "default";
> +
> + clock-frequency = <400000>;
> + status = "okay";
> +
> + hdmi-bridge@48 {
> + compatible = "lontium,lt8912b";
> + reg = <0x48> ;
> + reset-gpios = <&pinctrl RZG2L_GPIO(42, 2) GPIO_ACTIVE_LOW>;
Missing interrupts (P16_1), but that is not yet supported by the
bindings, so I guess it's fine to leave it out for now.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Hi Geert,
Thanks for this great review,
I appreciate the time spent on me!
> Hi Julien,
>
> On Mon, 27 Jan 2025 at 10:39, Julien Massot <julien.massot@collabora.com> wrote:
> > Add basic support for the MyIR Remi Pi (based on r9a07g044l2):
> > - UART
> > - i2c
> > - emmc
> > - USB host
> > - HDMI output
> > - Ethernet
> >
> > Signed-off-by: Julien Massot <julien.massot@collabora.com>
>
> Thanks for your patch!
>
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/renesas/r9a07g044l2-remi-pi.dts
> > @@ -0,0 +1,388 @@
> > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +/*
> > + * Device Tree Source for the MYiR Remi Pi
> > + *
> > + * Copyright (C) 2022 MYiR Electronics Corp.
> > + * Copyright (C) 2025 Collabora Ltd.
> > + */
> > +
> > +/dts-v1/;
> > +
> > +#include <dt-bindings/gpio/gpio.h>
> > +#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
> > +
> > +#include "r9a07g044l2.dtsi"
> > +
> > +/ {
> > + model = "MYIR Tech Limited Remi Pi MYB-YG2LX-REMI";
> > + compatible = "myir,remi-pi", "renesas,r9a07g044l2", "renesas,r9a07g044";
> > +
> > + aliases {
> > + ethernet0 = ð0;
> > + ethernet1 = ð1;
> > +
> > + serial0 = &scif0;
>
> So serial0 is the CA55 console, OK.
>
> > + serial1 = &scif1;
>
> Connected to BT/WiFi, but not yet enabled below.
Will drop, I want to support the BT/WiFi chip, but
not that easy to enable with the muxes on the SDHI1.
Let's keep that for the future.
>
>
> > + serial2 = &scif2;
>
> This is wired to the Raspberri Pi expansion connector.
> However, on Raspberri Pi, these pins are GPIOs.
> While the Raspberri Pi UART_[TR]X pins are wired to SCIF4 here,
> which is not yet enabled...
>
>
> Ok then let be nice and try to be closer to the normal Raspberry Pi header:
I will enable SCIF4, and remove SCIF2.
>
> > + serial3 = &scif3;
>
> Serial3 is the CA33 debug console, OK.
Let disable this one to leave it available for a potential RTOS.
>
> > +
> > + i2c0 = &i2c0;
> > + i2c1 = &i2c1;
> > + i2c2 = &i2c2;
> > + i2c3 = &i2c3;
> > +
> > + mmc0 = &sdhi0;
> > + mmc1 = &sdhi1;
>
> sdhi1 is not yet enabled, so please drop it.
Right
>
> > + };
>
> > + reg_5p0v: regulator-5p0v {
> > + compatible = "regulator-fixed";
> > + regulator-name = "fixed-5.0V";
> > + regulator-min-microvolt = <5000000>;
> > + regulator-max-microvolt = <5000000>;
> > + };
> > +
> > + reg_3p3v: regulator-3p3v {
> > + compatible = "regulator-fixed";
> > + regulator-name = "fixed-3.3V";
> > + vin-supply = <®_5p0v>;
> > + regulator-min-microvolt = <3300000>;
> > + regulator-max-microvolt = <3300000>;
> > + regulator-always-on;
> > + };
> > +
> > + reg_1p8v: regulator-1p8v {
> > + compatible = "regulator-fixed";
> > + regulator-name = "fixed-1.8V";
> > + vin-supply = <®_3p3v>;
>
> reg_5p0v, as 1.8V is generated from 5.0V, according to the schematics.
Nice catch! will change
>
> > + regulator-min-microvolt = <1800000>;
> > + regulator-max-microvolt = <1800000>;
> > + regulator-always-on;
> > + };
> > +
> > + reg_1p1v: regulator-vdd-core {
> > + compatible = "regulator-fixed";
> > + regulator-name = "fixed-1.1V";
> > + regulator-min-microvolt = <1100000>;
> > + regulator-max-microvolt = <1100000>;
> > + regulator-always-on;
> > + };
>
> > +ð0 {
> > + pinctrl-0 = <ð0_pins>;
> > + pinctrl-names = "default";
> > + phy-handle = <&phy0>;
> > + phy-mode = "rgmii-id";
> > + status = "okay";
> > +
> > + phy0: ethernet-phy@4 {
> > + compatible = "ethernet-phy-ieee802.3-c22";
> > + reg = <4>;
> > + interrupts-extended = <&pinctrl RZG2L_GPIO(44, 2) IRQ_TYPE_LEVEL_LOW>;
>
> Missing reset-gpios (P44_3).
ok
>
> > + };
> > +};
> > +
> > +ð1 {
> > + pinctrl-0 = <ð1_pins>;
> > + pinctrl-names = "default";
> > + phy-handle = <&phy1>;
> > + phy-mode = "rgmii-id";
> > + status = "okay";
> > +
> > + phy1: ethernet-phy@6 {
> > + compatible = "ethernet-phy-ieee802.3-c22";
> > + reg = <6>;
> > + interrupts-extended = <&pinctrl RZG2L_GPIO(43, 2) IRQ_TYPE_LEVEL_LOW>;
>
> Missing reset-gpios (P43_3).
ok
>
> > + };
> > +};
>
> > +&pinctrl {
>
> > + spi0_pins: spi0 {
> > + pinmux = <RZG2L_PORT_PINMUX(47, 0, 5)>, /* CLK */
> > + <RZG2L_PORT_PINMUX(47, 1, 5)>, /* MOSI */
> > + <RZG2L_PORT_PINMUX(47, 2, 5)>, /* MISO */
> > + <RZG2L_PORT_PINMUX(47, 3, 5)>; /* Chip Enable*/
> > + };
>
> Unused.
will drop
>
> > +
> > + eth0_pins: eth0 {
>
> Please sort pinctrl subnodes (alphabetically by node name).
ok
>
> > + sdhi0_pins: sd0 {
> > + sd0_data {
> > + pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3",
> > + "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7";
> > + power-source = <1800>;
> > + };
> > +
> > + sd0_ctrl {
> > + pins = "SD0_CLK", "SD0_CMD";
> > + power-source = <1800>;
> > + };
> > +
> > + sd0_rst {
> > + pins = "SD0_RST#";
> > + power-source = <1800>;
> > + };
> > + };
> > +
> > + sdhi0_pins_uhs: sd0_uhs {
> > + sd0_data_uhs {
> > + pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3",
> > + "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7";
> > + power-source = <1800>;
> > + };
> > +
> > + sd0_ctrl_uhs {
> > + pins = "SD0_CLK", "SD0_CMD";
> > + power-source = <1800>;
> > + };
> > +
> > + sd0_rst_uhs {
> > + pins = "SD0_RST#";
> > + power-source = <1800>;
> > + };
> > + };
>
> sd0 and sd0_uhs are identical, so you can just always use the former,
> and drop the latter.
Ok
>
> > +
> > + usb1_pins: usb1 {
> > + pinmux = <RZG2L_PORT_PINMUX(42, 0, 1)>, /* VBUS */
> > + <RZG2L_PORT_PINMUX(42, 1, 1)>; /* OVC */
>
> These two pins don't seem to be exposed on the SoM.
> Perhaps this is wired on the SoM?
Honestly I don't know :), I copy paste them from downstream but I'm not seeing anything in the
schematics regarding these pins. Let drop them.
>
>
> > + };
> > +
> > + scif0_pins: scif0 {
> > + pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>, /* TxD */
> > + <RZG2L_PORT_PINMUX(38, 1, 1)>; /* RxD */
> > + };
> > +
> > + scif1_pins: scif1 {
> > + pinmux = <RZG2L_PORT_PINMUX(40, 0, 1)>, /* TxD */
> > + <RZG2L_PORT_PINMUX(40, 1, 1)>; /* RxD */
> > + };
>
> SCIF1 is connected to BT/WiFi, and the CTS/RTS pins should be included.
> However, for now SCIF1 is not yet enabled, so please everything related to it.
>
> Will drop SCIF1, until I come with an idea to support BT/WIFI chip.
>
>
> > +&usb2_phy1 {
> > + pinctrl-0 = <&usb1_pins>;
> > + pinctrl-names = "default";
> > +
> > + status = "okay";
> > +};
> > +
> > +&ehci1 {
>
> Please sort references to nodes (alphabetically). More below...
ok
>
> > +&dsi {
> > + status = "okay";
>
> Please insert a blank line.
ok
>
> > + ports {
>
> > +&i2c0 {
> > + pinctrl-0 = <&i2c0_pins>;
> > + pinctrl-names = "default";
> > +
> > + clock-frequency = <400000>;
> > + status = "okay";
> > +
> > + hdmi-bridge@48 {
> > + compatible = "lontium,lt8912b";
> > + reg = <0x48> ;
> > + reset-gpios = <&pinctrl RZG2L_GPIO(42, 2) GPIO_ACTIVE_LOW>;
>
> Missing interrupts (P16_1), but that is not yet supported by the
> bindings, so I guess it's fine to leave it out for now.
I will keep it as is.
Regards,
--
Julien
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