1. Patchew
  2. linux
  3. [PATCH 00/20] Arch-PEBS and PMU supports for Clearwater Forest
  4. View patch

[PATCH 02/20] perf/x86/intel: Fix ARCH_PERFMON_NUM_COUNTER_LEAF

Dapeng Mi posted 20 patches 1 year ago
[PATCH 02/20] perf/x86/intel: Fix ARCH_PERFMON_NUM_COUNTER_LEAF
Posted by Dapeng Mi 1 year ago 
From: Kan Liang <kan.liang@linux.intel.com>

The EAX of the CPUID Leaf 023H enumerates the mask of valid sub-leaves.
To tell the availability of the sub-leaf 1 (enumerate the counter mask),
perf should check the bit 1 (0x2) of EAS, rather than bit 0 (0x1).

The error is not user-visible on bare metal. Because the sub-leaf 0 and
the sub-leaf 1 are always available. However, it may bring issues in a
virtualization environment when a VMM only enumerates the sub-leaf 0.

Fixes: eb467aaac21e ("perf/x86/intel: Support Architectural PerfMon Extension leaf")
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Cc: stable@vger.kernel.org
---
 arch/x86/events/intel/core.c      | 4 ++--
 arch/x86/include/asm/perf_event.h | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 5e8521a54474..12eb96219740 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -4966,8 +4966,8 @@ static void update_pmu_cap(struct x86_hybrid_pmu *pmu)
 	if (ebx & ARCH_PERFMON_EXT_EQ)
 		pmu->config_mask |= ARCH_PERFMON_EVENTSEL_EQ;
 
-	if (sub_bitmaps & ARCH_PERFMON_NUM_COUNTER_LEAF_BIT) {
-		cpuid_count(ARCH_PERFMON_EXT_LEAF, ARCH_PERFMON_NUM_COUNTER_LEAF,
+	if (sub_bitmaps & ARCH_PERFMON_NUM_COUNTER_LEAF) {
+		cpuid_count(ARCH_PERFMON_EXT_LEAF, ARCH_PERFMON_NUM_COUNTER_LEAF_BIT,
 			    &eax, &ebx, &ecx, &edx);
 		pmu->cntr_mask64 = eax;
 		pmu->fixed_cntr_mask64 = ebx;
diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h
index adaeb8ca3a8a..71e2ae021374 100644
--- a/arch/x86/include/asm/perf_event.h
+++ b/arch/x86/include/asm/perf_event.h
@@ -197,7 +197,7 @@ union cpuid10_edx {
 #define ARCH_PERFMON_EXT_UMASK2			0x1
 #define ARCH_PERFMON_EXT_EQ			0x2
 #define ARCH_PERFMON_NUM_COUNTER_LEAF_BIT	0x1
-#define ARCH_PERFMON_NUM_COUNTER_LEAF		0x1
+#define ARCH_PERFMON_NUM_COUNTER_LEAF		BIT(ARCH_PERFMON_NUM_COUNTER_LEAF_BIT)
 
 /*
  * Intel Architectural LBR CPUID detection/enumeration details:
-- 
2.40.1
Re: [PATCH 02/20] perf/x86/intel: Fix ARCH_PERFMON_NUM_COUNTER_LEAF
Posted by Peter Zijlstra 1 year ago 
On Thu, Jan 23, 2025 at 02:07:03PM +0000, Dapeng Mi wrote:
> From: Kan Liang <kan.liang@linux.intel.com>
> 
> The EAX of the CPUID Leaf 023H enumerates the mask of valid sub-leaves.
> To tell the availability of the sub-leaf 1 (enumerate the counter mask),
> perf should check the bit 1 (0x2) of EAS, rather than bit 0 (0x1).
> 
> The error is not user-visible on bare metal. Because the sub-leaf 0 and
> the sub-leaf 1 are always available. However, it may bring issues in a
> virtualization environment when a VMM only enumerates the sub-leaf 0.
> 
> Fixes: eb467aaac21e ("perf/x86/intel: Support Architectural PerfMon Extension leaf")
> Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
> Cc: stable@vger.kernel.org
> ---
>  arch/x86/events/intel/core.c      | 4 ++--
>  arch/x86/include/asm/perf_event.h | 2 +-
>  2 files changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
> index 5e8521a54474..12eb96219740 100644
> --- a/arch/x86/events/intel/core.c
> +++ b/arch/x86/events/intel/core.c
> @@ -4966,8 +4966,8 @@ static void update_pmu_cap(struct x86_hybrid_pmu *pmu)
>  	if (ebx & ARCH_PERFMON_EXT_EQ)
>  		pmu->config_mask |= ARCH_PERFMON_EVENTSEL_EQ;
>  
> -	if (sub_bitmaps & ARCH_PERFMON_NUM_COUNTER_LEAF_BIT) {
> -		cpuid_count(ARCH_PERFMON_EXT_LEAF, ARCH_PERFMON_NUM_COUNTER_LEAF,
> +	if (sub_bitmaps & ARCH_PERFMON_NUM_COUNTER_LEAF) {
> +		cpuid_count(ARCH_PERFMON_EXT_LEAF, ARCH_PERFMON_NUM_COUNTER_LEAF_BIT,
>  			    &eax, &ebx, &ecx, &edx);
>  		pmu->cntr_mask64 = eax;
>  		pmu->fixed_cntr_mask64 = ebx;
> diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h
> index adaeb8ca3a8a..71e2ae021374 100644
> --- a/arch/x86/include/asm/perf_event.h
> +++ b/arch/x86/include/asm/perf_event.h
> @@ -197,7 +197,7 @@ union cpuid10_edx {
>  #define ARCH_PERFMON_EXT_UMASK2			0x1
>  #define ARCH_PERFMON_EXT_EQ			0x2
>  #define ARCH_PERFMON_NUM_COUNTER_LEAF_BIT	0x1
> -#define ARCH_PERFMON_NUM_COUNTER_LEAF		0x1
> +#define ARCH_PERFMON_NUM_COUNTER_LEAF		BIT(ARCH_PERFMON_NUM_COUNTER_LEAF_BIT)

if you'll look around, you'll note this file uses BIT_ULL(), please stay
consistent.
Re: [PATCH 02/20] perf/x86/intel: Fix ARCH_PERFMON_NUM_COUNTER_LEAF
Posted by Liang, Kan 1 year ago 

On 2025-01-27 11:29 a.m., Peter Zijlstra wrote:
> On Thu, Jan 23, 2025 at 02:07:03PM +0000, Dapeng Mi wrote:
>> From: Kan Liang <kan.liang@linux.intel.com>
>>
>> The EAX of the CPUID Leaf 023H enumerates the mask of valid sub-leaves.
>> To tell the availability of the sub-leaf 1 (enumerate the counter mask),
>> perf should check the bit 1 (0x2) of EAS, rather than bit 0 (0x1).
>>
>> The error is not user-visible on bare metal. Because the sub-leaf 0 and
>> the sub-leaf 1 are always available. However, it may bring issues in a
>> virtualization environment when a VMM only enumerates the sub-leaf 0.
>>
>> Fixes: eb467aaac21e ("perf/x86/intel: Support Architectural PerfMon Extension leaf")
>> Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
>> Cc: stable@vger.kernel.org
>> ---
>>  arch/x86/events/intel/core.c      | 4 ++--
>>  arch/x86/include/asm/perf_event.h | 2 +-
>>  2 files changed, 3 insertions(+), 3 deletions(-)
>>
>> diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
>> index 5e8521a54474..12eb96219740 100644
>> --- a/arch/x86/events/intel/core.c
>> +++ b/arch/x86/events/intel/core.c
>> @@ -4966,8 +4966,8 @@ static void update_pmu_cap(struct x86_hybrid_pmu *pmu)
>>  	if (ebx & ARCH_PERFMON_EXT_EQ)
>>  		pmu->config_mask |= ARCH_PERFMON_EVENTSEL_EQ;
>>  
>> -	if (sub_bitmaps & ARCH_PERFMON_NUM_COUNTER_LEAF_BIT) {
>> -		cpuid_count(ARCH_PERFMON_EXT_LEAF, ARCH_PERFMON_NUM_COUNTER_LEAF,
>> +	if (sub_bitmaps & ARCH_PERFMON_NUM_COUNTER_LEAF) {
>> +		cpuid_count(ARCH_PERFMON_EXT_LEAF, ARCH_PERFMON_NUM_COUNTER_LEAF_BIT,
>>  			    &eax, &ebx, &ecx, &edx);
>>  		pmu->cntr_mask64 = eax;
>>  		pmu->fixed_cntr_mask64 = ebx;
>> diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h
>> index adaeb8ca3a8a..71e2ae021374 100644
>> --- a/arch/x86/include/asm/perf_event.h
>> +++ b/arch/x86/include/asm/perf_event.h
>> @@ -197,7 +197,7 @@ union cpuid10_edx {
>>  #define ARCH_PERFMON_EXT_UMASK2			0x1
>>  #define ARCH_PERFMON_EXT_EQ			0x2
>>  #define ARCH_PERFMON_NUM_COUNTER_LEAF_BIT	0x1
>> -#define ARCH_PERFMON_NUM_COUNTER_LEAF		0x1
>> +#define ARCH_PERFMON_NUM_COUNTER_LEAF		BIT(ARCH_PERFMON_NUM_COUNTER_LEAF_BIT)
> 
> if you'll look around, you'll note this file uses BIT_ULL(), please stay
> consistent.

But they are used for a 64-bit register.
The ARCH_PERFMON_NUM_COUNTER_LEAF is for the CPUID enumeration, which is
a u32.

Thanks,
Kan
Re: [PATCH 02/20] perf/x86/intel: Fix ARCH_PERFMON_NUM_COUNTER_LEAF
Posted by Peter Zijlstra 1 year ago 
On Mon, Jan 27, 2025 at 11:43:53AM -0500, Liang, Kan wrote:

> But they are used for a 64-bit register.
> The ARCH_PERFMON_NUM_COUNTER_LEAF is for the CPUID enumeration, which is
> a u32.

A well, but CPUID should be using unions, no?

we have cpuid10_e[abd]x cpuid28_e[abc]x, so wheres cpuid23_e?x at?
Re: [PATCH 02/20] perf/x86/intel: Fix ARCH_PERFMON_NUM_COUNTER_LEAF
Posted by Liang, Kan 1 year ago 

On 2025-01-27 4:29 p.m., Peter Zijlstra wrote:
> On Mon, Jan 27, 2025 at 11:43:53AM -0500, Liang, Kan wrote:
> 
>> But they are used for a 64-bit register.
>> The ARCH_PERFMON_NUM_COUNTER_LEAF is for the CPUID enumeration, which is
>> a u32.
> 
> A well, but CPUID should be using unions, no?
> 
> we have cpuid10_e[abd]x cpuid28_e[abc]x, so wheres cpuid23_e?x at?
> 

Sure, I will add a cpuid23_e?x to make them consistent.

Thanks,
Kan

Patchew 2.1-devel-b67e4c2

© 2016 - 2026 Red Hat, Inc.