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[PATCH] mailbox: tegra-hsp: Define dimensioning masks in soc data

Kartik Rajput posted 1 patch 1 year ago 
drivers/mailbox/tegra-hsp.c | 72 ++++++++++++++++++++++++++++++-------
1 file changed, 60 insertions(+), 12 deletions(-)
[PATCH] mailbox: tegra-hsp: Define dimensioning masks in soc data
Posted by Kartik Rajput 1 year ago 
Tegra264 has updated HSP_INT_DIMENSIONING register as follows:
	* nSI is now BIT17:BIT21.
	* nDB is now BIT12:BIT16.

Currently, we are using a static macro HSP_nINT_MASK to get the values
from HSP_INT_DIMENSIONING register. This results in wrong values for nSI
for HSP instances that supports 16 shared interrupts.

Define dimensioning masks in soc data and use them to parse nSI, nDB,
nAS, nSS & nSM values.

Fixes: 602dbbacc3ef ("mailbox: tegra: add support for Tegra264")
Cc: stable@vger.kernel.org

Signed-off-by: Kartik Rajput <kkartik@nvidia.com>
---
 drivers/mailbox/tegra-hsp.c | 72 ++++++++++++++++++++++++++++++-------
 1 file changed, 60 insertions(+), 12 deletions(-)

diff --git a/drivers/mailbox/tegra-hsp.c b/drivers/mailbox/tegra-hsp.c
index 8d5e2d7dc03b..038d4a4080e7 100644
--- a/drivers/mailbox/tegra-hsp.c
+++ b/drivers/mailbox/tegra-hsp.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (c) 2016-2023, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2025, NVIDIA CORPORATION.  All rights reserved.
  */
 
 #include <linux/delay.h>
@@ -28,12 +28,6 @@
 #define HSP_INT_FULL_MASK	0xff
 
 #define HSP_INT_DIMENSIONING	0x380
-#define HSP_nSM_SHIFT		0
-#define HSP_nSS_SHIFT		4
-#define HSP_nAS_SHIFT		8
-#define HSP_nDB_SHIFT		12
-#define HSP_nSI_SHIFT		16
-#define HSP_nINT_MASK		0xf
 
 #define HSP_DB_TRIGGER	0x0
 #define HSP_DB_ENABLE	0x4
@@ -97,6 +91,20 @@ struct tegra_hsp_soc {
 	bool has_per_mb_ie;
 	bool has_128_bit_mb;
 	unsigned int reg_stride;
+
+	/* Shifts for dimensioning register. */
+	unsigned int si_shift;
+	unsigned int db_shift;
+	unsigned int as_shift;
+	unsigned int ss_shift;
+	unsigned int sm_shift;
+
+	/* Masks for dimensioning register. */
+	unsigned int si_mask;
+	unsigned int db_mask;
+	unsigned int as_mask;
+	unsigned int ss_mask;
+	unsigned int sm_mask;
 };
 
 struct tegra_hsp {
@@ -745,11 +753,11 @@ static int tegra_hsp_probe(struct platform_device *pdev)
 		return PTR_ERR(hsp->regs);
 
 	value = tegra_hsp_readl(hsp, HSP_INT_DIMENSIONING);
-	hsp->num_sm = (value >> HSP_nSM_SHIFT) & HSP_nINT_MASK;
-	hsp->num_ss = (value >> HSP_nSS_SHIFT) & HSP_nINT_MASK;
-	hsp->num_as = (value >> HSP_nAS_SHIFT) & HSP_nINT_MASK;
-	hsp->num_db = (value >> HSP_nDB_SHIFT) & HSP_nINT_MASK;
-	hsp->num_si = (value >> HSP_nSI_SHIFT) & HSP_nINT_MASK;
+	hsp->num_sm = (value >> hsp->soc->sm_shift) & hsp->soc->sm_mask;
+	hsp->num_ss = (value >> hsp->soc->ss_shift) & hsp->soc->ss_mask;
+	hsp->num_as = (value >> hsp->soc->as_shift) & hsp->soc->as_mask;
+	hsp->num_db = (value >> hsp->soc->db_shift) & hsp->soc->db_mask;
+	hsp->num_si = (value >> hsp->soc->si_shift) & hsp->soc->si_mask;
 
 	err = platform_get_irq_byname_optional(pdev, "doorbell");
 	if (err >= 0)
@@ -913,6 +921,16 @@ static const struct tegra_hsp_soc tegra186_hsp_soc = {
 	.has_per_mb_ie = false,
 	.has_128_bit_mb = false,
 	.reg_stride = 0x100,
+	.si_shift = 16,
+	.db_shift = 12,
+	.as_shift = 8,
+	.ss_shift = 4,
+	.sm_shift = 0,
+	.si_mask = 0xf,
+	.db_mask = 0xf,
+	.as_mask = 0xf,
+	.ss_mask = 0xf,
+	.sm_mask = 0xf,
 };
 
 static const struct tegra_hsp_soc tegra194_hsp_soc = {
@@ -920,6 +938,16 @@ static const struct tegra_hsp_soc tegra194_hsp_soc = {
 	.has_per_mb_ie = true,
 	.has_128_bit_mb = false,
 	.reg_stride = 0x100,
+	.si_shift = 16,
+	.db_shift = 12,
+	.as_shift = 8,
+	.ss_shift = 4,
+	.sm_shift = 0,
+	.si_mask = 0xf,
+	.db_mask = 0xf,
+	.as_mask = 0xf,
+	.ss_mask = 0xf,
+	.sm_mask = 0xf,
 };
 
 static const struct tegra_hsp_soc tegra234_hsp_soc = {
@@ -927,6 +955,16 @@ static const struct tegra_hsp_soc tegra234_hsp_soc = {
 	.has_per_mb_ie = false,
 	.has_128_bit_mb = true,
 	.reg_stride = 0x100,
+	.si_shift = 16,
+	.db_shift = 12,
+	.as_shift = 8,
+	.ss_shift = 4,
+	.sm_shift = 0,
+	.si_mask = 0xf,
+	.db_mask = 0xf,
+	.as_mask = 0xf,
+	.ss_mask = 0xf,
+	.sm_mask = 0xf,
 };
 
 static const struct tegra_hsp_soc tegra264_hsp_soc = {
@@ -934,6 +972,16 @@ static const struct tegra_hsp_soc tegra264_hsp_soc = {
 	.has_per_mb_ie = false,
 	.has_128_bit_mb = true,
 	.reg_stride = 0x1000,
+	.si_shift = 17,
+	.db_shift = 12,
+	.as_shift = 8,
+	.ss_shift = 4,
+	.sm_shift = 0,
+	.si_mask = 0x1f,
+	.db_mask = 0x1f,
+	.as_mask = 0xf,
+	.ss_mask = 0xf,
+	.sm_mask = 0xf,
 };
 
 static const struct of_device_id tegra_hsp_match[] = {
-- 
2.43.0
Re: [PATCH] mailbox: tegra-hsp: Define dimensioning masks in soc data
Posted by Thierry Reding 11 months, 2 weeks ago 
On Thu, Jan 23, 2025 at 06:16:32PM +0530, Kartik Rajput wrote:
> Tegra264 has updated HSP_INT_DIMENSIONING register as follows:
> 	* nSI is now BIT17:BIT21.
> 	* nDB is now BIT12:BIT16.
> 
> Currently, we are using a static macro HSP_nINT_MASK to get the values
> from HSP_INT_DIMENSIONING register. This results in wrong values for nSI
> for HSP instances that supports 16 shared interrupts.
> 
> Define dimensioning masks in soc data and use them to parse nSI, nDB,
> nAS, nSS & nSM values.
> 
> Fixes: 602dbbacc3ef ("mailbox: tegra: add support for Tegra264")
> Cc: stable@vger.kernel.org
> 
> Signed-off-by: Kartik Rajput <kkartik@nvidia.com>

Maybe remove the blank line between the Cc: and S-o-b: tags. Also, "soc"
-> "SoC" in the subject and commit message. With that:

Acked-by: Thierry Reding <treding@nvidia.com>
Re: [PATCH] mailbox: tegra-hsp: Define dimensioning masks in soc data
Posted by Jassi Brar 11 months, 2 weeks ago 
On Thu, Feb 27, 2025 at 4:35 AM Thierry Reding <thierry.reding@gmail.com> wrote:
>
> On Thu, Jan 23, 2025 at 06:16:32PM +0530, Kartik Rajput wrote:
> > Tegra264 has updated HSP_INT_DIMENSIONING register as follows:
> >       * nSI is now BIT17:BIT21.
> >       * nDB is now BIT12:BIT16.
> >
> > Currently, we are using a static macro HSP_nINT_MASK to get the values
> > from HSP_INT_DIMENSIONING register. This results in wrong values for nSI
> > for HSP instances that supports 16 shared interrupts.
> >
> > Define dimensioning masks in soc data and use them to parse nSI, nDB,
> > nAS, nSS & nSM values.
> >
> > Fixes: 602dbbacc3ef ("mailbox: tegra: add support for Tegra264")
> > Cc: stable@vger.kernel.org
> >
> > Signed-off-by: Kartik Rajput <kkartik@nvidia.com>
>
> Maybe remove the blank line between the Cc: and S-o-b: tags. Also, "soc"
> -> "SoC" in the subject and commit message. With that:
>
> Acked-by: Thierry Reding <treding@nvidia.com>

Fixed myself and picked with the acks.
thanks
Re: [PATCH] mailbox: tegra-hsp: Define dimensioning masks in soc data
Posted by Thierry Reding 11 months, 2 weeks ago 
On Sat, Mar 01, 2025 at 10:42:21AM -0600, Jassi Brar wrote:
> On Thu, Feb 27, 2025 at 4:35 AM Thierry Reding <thierry.reding@gmail.com> wrote:
> >
> > On Thu, Jan 23, 2025 at 06:16:32PM +0530, Kartik Rajput wrote:
> > > Tegra264 has updated HSP_INT_DIMENSIONING register as follows:
> > >       * nSI is now BIT17:BIT21.
> > >       * nDB is now BIT12:BIT16.
> > >
> > > Currently, we are using a static macro HSP_nINT_MASK to get the values
> > > from HSP_INT_DIMENSIONING register. This results in wrong values for nSI
> > > for HSP instances that supports 16 shared interrupts.
> > >
> > > Define dimensioning masks in soc data and use them to parse nSI, nDB,
> > > nAS, nSS & nSM values.
> > >
> > > Fixes: 602dbbacc3ef ("mailbox: tegra: add support for Tegra264")
> > > Cc: stable@vger.kernel.org
> > >
> > > Signed-off-by: Kartik Rajput <kkartik@nvidia.com>
> >
> > Maybe remove the blank line between the Cc: and S-o-b: tags. Also, "soc"
> > -> "SoC" in the subject and commit message. With that:
> >
> > Acked-by: Thierry Reding <treding@nvidia.com>
> 
> Fixed myself and picked with the acks.
> thanks

Thanks!

Thierry
Re: [PATCH] mailbox: tegra-hsp: Define dimensioning masks in soc data
Posted by Jon Hunter 11 months, 2 weeks ago 
On 27/02/2025 10:35, Thierry Reding wrote:
> On Thu, Jan 23, 2025 at 06:16:32PM +0530, Kartik Rajput wrote:
>> Tegra264 has updated HSP_INT_DIMENSIONING register as follows:
>> 	* nSI is now BIT17:BIT21.
>> 	* nDB is now BIT12:BIT16.
>>
>> Currently, we are using a static macro HSP_nINT_MASK to get the values
>> from HSP_INT_DIMENSIONING register. This results in wrong values for nSI
>> for HSP instances that supports 16 shared interrupts.
>>
>> Define dimensioning masks in soc data and use them to parse nSI, nDB,
>> nAS, nSS & nSM values.
>>
>> Fixes: 602dbbacc3ef ("mailbox: tegra: add support for Tegra264")
>> Cc: stable@vger.kernel.org
>>
>> Signed-off-by: Kartik Rajput <kkartik@nvidia.com>
> 
> Maybe remove the blank line between the Cc: and S-o-b: tags. Also, "soc"
> -> "SoC" in the subject and commit message. With that:
> 
> Acked-by: Thierry Reding <treding@nvidia.com>


FWIW ...

Acked-by: Jon Hunter <jonathanh@nvidia.com>

Thanks!
Jon

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