Expose Zicbom through hwprobe and also provide a key to extract its
respective block size.
Signed-off-by: Yunhui Cui <cuiyunhui@bytedance.com>
---
Documentation/arch/riscv/hwprobe.rst | 6 ++++++
arch/riscv/include/asm/hwprobe.h | 2 +-
arch/riscv/include/uapi/asm/hwprobe.h | 2 ++
arch/riscv/kernel/sys_hwprobe.c | 6 ++++++
4 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst
index 955fbcd19ce9..21323811a206 100644
--- a/Documentation/arch/riscv/hwprobe.rst
+++ b/Documentation/arch/riscv/hwprobe.rst
@@ -242,6 +242,9 @@ The following keys are defined:
* :c:macro:`RISCV_HWPROBE_EXT_SUPM`: The Supm extension is supported as
defined in version 1.0 of the RISC-V Pointer Masking extensions.
+ * :c:macro:`RISCV_HWPROBE_EXT_ZICBOM`: The Zicbom extension is supported, as
+ ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.
+
* :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: Deprecated. Returns similar values to
:c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF`, but the key was
mistakenly classified as a bitmask rather than a value.
@@ -293,3 +296,6 @@ The following keys are defined:
* :c:macro:`RISCV_HWPROBE_MISALIGNED_VECTOR_UNSUPPORTED`: Misaligned vector accesses are
not supported at all and will generate a misaligned address fault.
+
+* :c:macro:`RISCV_HWPROBE_KEY_ZICBOM_BLOCK_SIZE`: An unsigned int which
+ represents the size of the Zicbom block in bytes.
diff --git a/arch/riscv/include/asm/hwprobe.h b/arch/riscv/include/asm/hwprobe.h
index 1ce1df6d0ff3..89379f9a2e6e 100644
--- a/arch/riscv/include/asm/hwprobe.h
+++ b/arch/riscv/include/asm/hwprobe.h
@@ -8,7 +8,7 @@
#include <uapi/asm/hwprobe.h>
-#define RISCV_HWPROBE_MAX_KEY 10
+#define RISCV_HWPROBE_MAX_KEY 11
static inline bool riscv_hwprobe_key_is_valid(__s64 key)
{
diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
index 3af142b99f77..b15c0bd83ef2 100644
--- a/arch/riscv/include/uapi/asm/hwprobe.h
+++ b/arch/riscv/include/uapi/asm/hwprobe.h
@@ -73,6 +73,7 @@ struct riscv_hwprobe {
#define RISCV_HWPROBE_EXT_ZCMOP (1ULL << 47)
#define RISCV_HWPROBE_EXT_ZAWRS (1ULL << 48)
#define RISCV_HWPROBE_EXT_SUPM (1ULL << 49)
+#define RISCV_HWPROBE_EXT_ZICBOM (1ULL << 50)
#define RISCV_HWPROBE_KEY_CPUPERF_0 5
#define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0)
#define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0)
@@ -94,6 +95,7 @@ struct riscv_hwprobe {
#define RISCV_HWPROBE_MISALIGNED_VECTOR_SLOW 2
#define RISCV_HWPROBE_MISALIGNED_VECTOR_FAST 3
#define RISCV_HWPROBE_MISALIGNED_VECTOR_UNSUPPORTED 4
+#define RISCV_HWPROBE_KEY_ZICBOM_BLOCK_SIZE 11
/* Increase RISCV_HWPROBE_MAX_KEY when adding items. */
/* Flags */
diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c
index cb93adfffc48..04150e62f998 100644
--- a/arch/riscv/kernel/sys_hwprobe.c
+++ b/arch/riscv/kernel/sys_hwprobe.c
@@ -106,6 +106,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
EXT_KEY(ZCA);
EXT_KEY(ZCB);
EXT_KEY(ZCMOP);
+ EXT_KEY(ZICBOM);
EXT_KEY(ZICBOZ);
EXT_KEY(ZICOND);
EXT_KEY(ZIHINTNTL);
@@ -278,6 +279,11 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pair,
if (hwprobe_ext0_has(cpus, RISCV_HWPROBE_EXT_ZICBOZ))
pair->value = riscv_cboz_block_size;
break;
+ case RISCV_HWPROBE_KEY_ZICBOM_BLOCK_SIZE:
+ pair->value = 0;
+ if (hwprobe_ext0_has(cpus, RISCV_HWPROBE_EXT_ZICBOM))
+ pair->value = riscv_cbom_block_size;
+ break;
case RISCV_HWPROBE_KEY_HIGHEST_VIRT_ADDRESS:
pair->value = user_max_virt_addr();
break;
--
2.39.2On Wed, Jan 15, 2025 at 10:40:23AM +0800, Yunhui Cui wrote:
> Expose Zicbom through hwprobe and also provide a key to extract its
> respective block size.
>
> Signed-off-by: Yunhui Cui <cuiyunhui@bytedance.com>
> ---
> Documentation/arch/riscv/hwprobe.rst | 6 ++++++
> arch/riscv/include/asm/hwprobe.h | 2 +-
> arch/riscv/include/uapi/asm/hwprobe.h | 2 ++
> arch/riscv/kernel/sys_hwprobe.c | 6 ++++++
> 4 files changed, 15 insertions(+), 1 deletion(-)
>
As the bot points out, we need to add the following to this patch.
Thanks,
drew
diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c
index cb93adfffc48..6b5b24b399c3 100644
--- a/arch/riscv/kernel/sys_hwprobe.c
+++ b/arch/riscv/kernel/sys_hwprobe.c
@@ -160,7 +160,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
pair->value &= ~missing;
}
-static bool hwprobe_ext0_has(const struct cpumask *cpus, unsigned long ext)
+static bool hwprobe_ext0_has(const struct cpumask *cpus, u64 ext)
{
struct riscv_hwprobe pair;
Hi drew,
On Tue, Jan 21, 2025 at 11:29 PM Andrew Jones <ajones@ventanamicro.com> wrote:
>
> On Wed, Jan 15, 2025 at 10:40:23AM +0800, Yunhui Cui wrote:
> > Expose Zicbom through hwprobe and also provide a key to extract its
> > respective block size.
> >
> > Signed-off-by: Yunhui Cui <cuiyunhui@bytedance.com>
> > ---
> > Documentation/arch/riscv/hwprobe.rst | 6 ++++++
> > arch/riscv/include/asm/hwprobe.h | 2 +-
> > arch/riscv/include/uapi/asm/hwprobe.h | 2 ++
> > arch/riscv/kernel/sys_hwprobe.c | 6 ++++++
> > 4 files changed, 15 insertions(+), 1 deletion(-)
> >
>
> As the bot points out, we need to add the following to this patch.
OK, I'll update a version and change hwprobe_ext0_has's second param to u64.
>
> Thanks,
> drew
>
> diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c
> index cb93adfffc48..6b5b24b399c3 100644
> --- a/arch/riscv/kernel/sys_hwprobe.c
> +++ b/arch/riscv/kernel/sys_hwprobe.c
> @@ -160,7 +160,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
> pair->value &= ~missing;
> }
>
> -static bool hwprobe_ext0_has(const struct cpumask *cpus, unsigned long ext)
> +static bool hwprobe_ext0_has(const struct cpumask *cpus, u64 ext)
> {
> struct riscv_hwprobe pair;
>
Thanks,
Yunhui
Hi Yunhui,
kernel test robot noticed the following build warnings:
[auto build test WARNING on shuah-kselftest/next]
[also build test WARNING on shuah-kselftest/fixes linus/master v6.13 next-20250121]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Yunhui-Cui/RISC-V-Enable-cbo-clean-flush-in-usermode/20250115-104456
base: https://git.kernel.org/pub/scm/linux/kernel/git/shuah/linux-kselftest.git next
patch link: https://lore.kernel.org/r/20250115024024.84365-3-cuiyunhui%40bytedance.com
patch subject: [PATCH v5 2/3] RISC-V: hwprobe: Expose Zicbom extension and its block size
config: riscv-randconfig-r133-20250121 (https://download.01.org/0day-ci/archive/20250121/202501212220.5GHTtuF7-lkp@intel.com/config)
compiler: clang version 20.0.0git (https://github.com/llvm/llvm-project c23f2417dc5f6dc371afb07af5627ec2a9d373a0)
reproduce: (https://download.01.org/0day-ci/archive/20250121/202501212220.5GHTtuF7-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202501212220.5GHTtuF7-lkp@intel.com/
All warnings (new ones prefixed by >>):
>> arch/riscv/kernel/sys_hwprobe.c:284:30: warning: implicit conversion from 'unsigned long long' to 'unsigned long' changes value from 1125899906842624 to 0 [-Wconstant-conversion]
284 | if (hwprobe_ext0_has(cpus, RISCV_HWPROBE_EXT_ZICBOM))
| ~~~~~~~~~~~~~~~~ ^~~~~~~~~~~~~~~~~~~~~~~~
arch/riscv/include/uapi/asm/hwprobe.h:76:41: note: expanded from macro 'RISCV_HWPROBE_EXT_ZICBOM'
76 | #define RISCV_HWPROBE_EXT_ZICBOM (1ULL << 50)
| ~~~~~^~~~~
1 warning generated.
vim +284 arch/riscv/kernel/sys_hwprobe.c
244
245 static void hwprobe_one_pair(struct riscv_hwprobe *pair,
246 const struct cpumask *cpus)
247 {
248 switch (pair->key) {
249 case RISCV_HWPROBE_KEY_MVENDORID:
250 case RISCV_HWPROBE_KEY_MARCHID:
251 case RISCV_HWPROBE_KEY_MIMPID:
252 hwprobe_arch_id(pair, cpus);
253 break;
254 /*
255 * The kernel already assumes that the base single-letter ISA
256 * extensions are supported on all harts, and only supports the
257 * IMA base, so just cheat a bit here and tell that to
258 * userspace.
259 */
260 case RISCV_HWPROBE_KEY_BASE_BEHAVIOR:
261 pair->value = RISCV_HWPROBE_BASE_BEHAVIOR_IMA;
262 break;
263
264 case RISCV_HWPROBE_KEY_IMA_EXT_0:
265 hwprobe_isa_ext0(pair, cpus);
266 break;
267
268 case RISCV_HWPROBE_KEY_CPUPERF_0:
269 case RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF:
270 pair->value = hwprobe_misaligned(cpus);
271 break;
272
273 case RISCV_HWPROBE_KEY_MISALIGNED_VECTOR_PERF:
274 pair->value = hwprobe_vec_misaligned(cpus);
275 break;
276
277 case RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE:
278 pair->value = 0;
279 if (hwprobe_ext0_has(cpus, RISCV_HWPROBE_EXT_ZICBOZ))
280 pair->value = riscv_cboz_block_size;
281 break;
282 case RISCV_HWPROBE_KEY_ZICBOM_BLOCK_SIZE:
283 pair->value = 0;
> 284 if (hwprobe_ext0_has(cpus, RISCV_HWPROBE_EXT_ZICBOM))
285 pair->value = riscv_cbom_block_size;
286 break;
287 case RISCV_HWPROBE_KEY_HIGHEST_VIRT_ADDRESS:
288 pair->value = user_max_virt_addr();
289 break;
290
291 case RISCV_HWPROBE_KEY_TIME_CSR_FREQ:
292 pair->value = riscv_timebase;
293 break;
294
295 /*
296 * For forward compatibility, unknown keys don't fail the whole
297 * call, but get their element key set to -1 and value set to 0
298 * indicating they're unrecognized.
299 */
300 default:
301 pair->key = -1;
302 pair->value = 0;
303 break;
304 }
305 }
306
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
On 2025-01-14 8:40 PM, Yunhui Cui wrote: > Expose Zicbom through hwprobe and also provide a key to extract its > respective block size. > > Signed-off-by: Yunhui Cui <cuiyunhui@bytedance.com> > --- > Documentation/arch/riscv/hwprobe.rst | 6 ++++++ > arch/riscv/include/asm/hwprobe.h | 2 +- > arch/riscv/include/uapi/asm/hwprobe.h | 2 ++ > arch/riscv/kernel/sys_hwprobe.c | 6 ++++++ > 4 files changed, 15 insertions(+), 1 deletion(-) Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
On Wed, Jan 15, 2025 at 10:40:23AM +0800, Yunhui Cui wrote: > Expose Zicbom through hwprobe and also provide a key to extract its > respective block size. > > Signed-off-by: Yunhui Cui <cuiyunhui@bytedance.com> > --- > Documentation/arch/riscv/hwprobe.rst | 6 ++++++ > arch/riscv/include/asm/hwprobe.h | 2 +- > arch/riscv/include/uapi/asm/hwprobe.h | 2 ++ > arch/riscv/kernel/sys_hwprobe.c | 6 ++++++ > 4 files changed, 15 insertions(+), 1 deletion(-) > Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
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