Documentation/arch/riscv/hwprobe.rst | 6 ++ arch/riscv/include/asm/hwprobe.h | 2 +- arch/riscv/include/uapi/asm/hwprobe.h | 2 + arch/riscv/kernel/cpufeature.c | 8 +++ arch/riscv/kernel/sys_hwprobe.c | 6 ++ tools/testing/selftests/riscv/hwprobe/cbo.c | 66 +++++++++++++++++---- 6 files changed, 78 insertions(+), 12 deletions(-)
v1/v2: There is only the first patch: RISC-V: Enable cbo.clean/flush in usermode, which mainly removes the enabling of cbo.inval in user mode. v3: Add the functionality of Expose Zicbom and selftests for Zicbom. v4: Modify the order of macros, The test_no_cbo_inval function is added separately. v5: 1. Modify the order of RISCV_HWPROBE_KEY_ZICBOM_BLOCK_SIZE in hwprobe.rst 2. "TEST_NO_ZICBOINVAL" -> "TEST_NO_CBO_INVAL" Yunhui Cui (3): RISC-V: Enable cbo.clean/flush in usermode RISC-V: hwprobe: Expose Zicbom extension and its block size RISC-V: selftests: Add TEST_ZICBOM into CBO tests Documentation/arch/riscv/hwprobe.rst | 6 ++ arch/riscv/include/asm/hwprobe.h | 2 +- arch/riscv/include/uapi/asm/hwprobe.h | 2 + arch/riscv/kernel/cpufeature.c | 8 +++ arch/riscv/kernel/sys_hwprobe.c | 6 ++ tools/testing/selftests/riscv/hwprobe/cbo.c | 66 +++++++++++++++++---- 6 files changed, 78 insertions(+), 12 deletions(-) -- 2.39.2
Hi Yunhui, On Wed, Jan 15, 2025 at 3:40 AM Yunhui Cui <cuiyunhui@bytedance.com> wrote: > > v1/v2: > There is only the first patch: RISC-V: Enable cbo.clean/flush in usermode, > which mainly removes the enabling of cbo.inval in user mode. > > v3: > Add the functionality of Expose Zicbom and selftests for Zicbom. > > v4: > Modify the order of macros, The test_no_cbo_inval function is added > separately. > > v5: > 1. Modify the order of RISCV_HWPROBE_KEY_ZICBOM_BLOCK_SIZE in hwprobe.rst > 2. "TEST_NO_ZICBOINVAL" -> "TEST_NO_CBO_INVAL" > > Yunhui Cui (3): > RISC-V: Enable cbo.clean/flush in usermode > RISC-V: hwprobe: Expose Zicbom extension and its block size > RISC-V: selftests: Add TEST_ZICBOM into CBO tests > > Documentation/arch/riscv/hwprobe.rst | 6 ++ > arch/riscv/include/asm/hwprobe.h | 2 +- > arch/riscv/include/uapi/asm/hwprobe.h | 2 + > arch/riscv/kernel/cpufeature.c | 8 +++ > arch/riscv/kernel/sys_hwprobe.c | 6 ++ > tools/testing/selftests/riscv/hwprobe/cbo.c | 66 +++++++++++++++++---- > 6 files changed, 78 insertions(+), 12 deletions(-) > > -- > 2.39.2 > So a v6 needs to be sent with: - the fix for hwprobe_ext0_has() reported by kernel test robot - a rebase on top of 6.14 since patch 2 will conflict with RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0 Do you think you can do that soon so that it gets merged in 6.15? The patchset received a lot of RB so it would be too bad to miss this release. Thanks, Alex
Hi Alex, On Tue, Feb 25, 2025 at 9:21 PM Alexandre Ghiti <alexghiti@rivosinc.com> wrote: > > Hi Yunhui, > > On Wed, Jan 15, 2025 at 3:40 AM Yunhui Cui <cuiyunhui@bytedance.com> wrote: > > > > v1/v2: > > There is only the first patch: RISC-V: Enable cbo.clean/flush in usermode, > > which mainly removes the enabling of cbo.inval in user mode. > > > > v3: > > Add the functionality of Expose Zicbom and selftests for Zicbom. > > > > v4: > > Modify the order of macros, The test_no_cbo_inval function is added > > separately. > > > > v5: > > 1. Modify the order of RISCV_HWPROBE_KEY_ZICBOM_BLOCK_SIZE in hwprobe.rst > > 2. "TEST_NO_ZICBOINVAL" -> "TEST_NO_CBO_INVAL" > > > > Yunhui Cui (3): > > RISC-V: Enable cbo.clean/flush in usermode > > RISC-V: hwprobe: Expose Zicbom extension and its block size > > RISC-V: selftests: Add TEST_ZICBOM into CBO tests > > > > Documentation/arch/riscv/hwprobe.rst | 6 ++ > > arch/riscv/include/asm/hwprobe.h | 2 +- > > arch/riscv/include/uapi/asm/hwprobe.h | 2 + > > arch/riscv/kernel/cpufeature.c | 8 +++ > > arch/riscv/kernel/sys_hwprobe.c | 6 ++ > > tools/testing/selftests/riscv/hwprobe/cbo.c | 66 +++++++++++++++++---- > > 6 files changed, 78 insertions(+), 12 deletions(-) > > > > -- > > 2.39.2 > > > > So a v6 needs to be sent with: > > - the fix for hwprobe_ext0_has() reported by kernel test robot > - a rebase on top of 6.14 since patch 2 will conflict with > RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0 Thank you for the reminder. In fact, version 6 was sent out almost a month ago. Reference: https://lore.kernel.org/lkml/20250124035959.45499-1-cuiyunhui@bytedance.com/ > > Do you think you can do that soon so that it gets merged in 6.15? The > patchset received a lot of RB so it would be too bad to miss this > release. > > Thanks, > > Alex Thanks, Yunhui
On Tue, Feb 25, 2025 at 2:27 PM yunhui cui <cuiyunhui@bytedance.com> wrote: > > Hi Alex, > > On Tue, Feb 25, 2025 at 9:21 PM Alexandre Ghiti <alexghiti@rivosinc.com> wrote: > > > > Hi Yunhui, > > > > On Wed, Jan 15, 2025 at 3:40 AM Yunhui Cui <cuiyunhui@bytedance.com> wrote: > > > > > > v1/v2: > > > There is only the first patch: RISC-V: Enable cbo.clean/flush in usermode, > > > which mainly removes the enabling of cbo.inval in user mode. > > > > > > v3: > > > Add the functionality of Expose Zicbom and selftests for Zicbom. > > > > > > v4: > > > Modify the order of macros, The test_no_cbo_inval function is added > > > separately. > > > > > > v5: > > > 1. Modify the order of RISCV_HWPROBE_KEY_ZICBOM_BLOCK_SIZE in hwprobe.rst > > > 2. "TEST_NO_ZICBOINVAL" -> "TEST_NO_CBO_INVAL" > > > > > > Yunhui Cui (3): > > > RISC-V: Enable cbo.clean/flush in usermode > > > RISC-V: hwprobe: Expose Zicbom extension and its block size > > > RISC-V: selftests: Add TEST_ZICBOM into CBO tests > > > > > > Documentation/arch/riscv/hwprobe.rst | 6 ++ > > > arch/riscv/include/asm/hwprobe.h | 2 +- > > > arch/riscv/include/uapi/asm/hwprobe.h | 2 + > > > arch/riscv/kernel/cpufeature.c | 8 +++ > > > arch/riscv/kernel/sys_hwprobe.c | 6 ++ > > > tools/testing/selftests/riscv/hwprobe/cbo.c | 66 +++++++++++++++++---- > > > 6 files changed, 78 insertions(+), 12 deletions(-) > > > > > > -- > > > 2.39.2 > > > > > > > So a v6 needs to be sent with: > > > > - the fix for hwprobe_ext0_has() reported by kernel test robot > > - a rebase on top of 6.14 since patch 2 will conflict with > > RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0 > > Thank you for the reminder. In fact, version 6 was sent out almost a > month ago. Reference: > https://lore.kernel.org/lkml/20250124035959.45499-1-cuiyunhui@bytedance.com/ Oh sorry, I missed it somehow! I think we can fix RISCV_HWPROBE_MAX_KEY when merging the patch. Sorry again and thanks! Alex > > > > > Do you think you can do that soon so that it gets merged in 6.15? The > > patchset received a lot of RB so it would be too bad to miss this > > release. > > > > Thanks, > > > > Alex > > Thanks, > Yunhui
Hi Alex, On Tue, Feb 25, 2025 at 10:07 PM Alexandre Ghiti <alexghiti@rivosinc.com> wrote: > > On Tue, Feb 25, 2025 at 2:27 PM yunhui cui <cuiyunhui@bytedance.com> wrote: > > > > Hi Alex, > > > > On Tue, Feb 25, 2025 at 9:21 PM Alexandre Ghiti <alexghiti@rivosinc.com> wrote: > > > > > > Hi Yunhui, > > > > > > On Wed, Jan 15, 2025 at 3:40 AM Yunhui Cui <cuiyunhui@bytedance.com> wrote: > > > > > > > > v1/v2: > > > > There is only the first patch: RISC-V: Enable cbo.clean/flush in usermode, > > > > which mainly removes the enabling of cbo.inval in user mode. > > > > > > > > v3: > > > > Add the functionality of Expose Zicbom and selftests for Zicbom. > > > > > > > > v4: > > > > Modify the order of macros, The test_no_cbo_inval function is added > > > > separately. > > > > > > > > v5: > > > > 1. Modify the order of RISCV_HWPROBE_KEY_ZICBOM_BLOCK_SIZE in hwprobe.rst > > > > 2. "TEST_NO_ZICBOINVAL" -> "TEST_NO_CBO_INVAL" > > > > > > > > Yunhui Cui (3): > > > > RISC-V: Enable cbo.clean/flush in usermode > > > > RISC-V: hwprobe: Expose Zicbom extension and its block size > > > > RISC-V: selftests: Add TEST_ZICBOM into CBO tests > > > > > > > > Documentation/arch/riscv/hwprobe.rst | 6 ++ > > > > arch/riscv/include/asm/hwprobe.h | 2 +- > > > > arch/riscv/include/uapi/asm/hwprobe.h | 2 + > > > > arch/riscv/kernel/cpufeature.c | 8 +++ > > > > arch/riscv/kernel/sys_hwprobe.c | 6 ++ > > > > tools/testing/selftests/riscv/hwprobe/cbo.c | 66 +++++++++++++++++---- > > > > 6 files changed, 78 insertions(+), 12 deletions(-) > > > > > > > > -- > > > > 2.39.2 > > > > > > > > > > So a v6 needs to be sent with: > > > > > > - the fix for hwprobe_ext0_has() reported by kernel test robot > > > - a rebase on top of 6.14 since patch 2 will conflict with > > > RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0 > > > > Thank you for the reminder. In fact, version 6 was sent out almost a > > month ago. Reference: > > https://lore.kernel.org/lkml/20250124035959.45499-1-cuiyunhui@bytedance.com/ > > Oh sorry, I missed it somehow! > > I think we can fix RISCV_HWPROBE_MAX_KEY when merging the patch. > > Sorry again and thanks! It's all good. I've rebased a version: https://lore.kernel.org/all/20250226063206.71216-1-cuiyunhui@bytedance.com/. Could you help to merge it? Thanks. > > Alex > > > > > > > > > Do you think you can do that soon so that it gets merged in 6.15? The > > > patchset received a lot of RB so it would be too bad to miss this > > > release. > > > > > > Thanks, > > > > > > Alex > > > > Thanks, > > Yunhui Thanks, Yunhui
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