This is my newly reworked phy driver for the rk3328 usb3 phy. It is
based loosely on my original version, but as of now almost nothing of
the original driver remains. The main fix here is the discovery of
BIT(6) in the interrupt enable grf register fixes the usb3 disconnection
detection (mostly). On occasion an unpopulated usb3 hub will take
several seconds to disconnect. However this means all of the hack around
work to reset the usb core manually is no longer required.

I did my best to document all registers I could find. A lot was taken
from emails between myself and Rockchip's engineers, much thanks to
William Wu <wulf@rock-chips.com> for their assistance here. The rest of
the config bits were taken from the rk3328 and rk3228h TRMs and the
downstream driver. Everything that I couldn't find a definition for is
prefixed UNK_ or UNKNOWN_. There's a lot of obviously used configuration
registers with the pipe interface that are also undocumented.

The only major bug I have so far is my AX88179 usb3 gigabit ethernet
adapter (Pluggable brand) crashes out when large amounts of data are
transmitted. I suspect this is related to the RX and TX tuning, as
leaving it at defaults makes things worse. As I am not a USB3 engineer
and I do not have the specialized knowledge and hardware to determine
what is going wrong, I am hoping the mailing list will have an answer
here.

Please test and review.

Very Respectfully,
Peter Geis



Peter Geis (6):
  clk: rockchip: fix wrong clk_ref_usb3otg parent for rk3328
  dt-bindings: phy: rockchip: add rk3328 usb3 phy
  phy: rockchip: add driver for rk3328 usb3 phy
  arm64: dts: rockchip: add rk3328 usb3 phy node
  arm64: dts: rockchip: enable the usb3 phy on rk3328-roc boards
  arm64: dts: rockchip: enable the usb3 phy on remaining rk3328 boards

 .../bindings/phy/rockchip,inno-usb3phy.yaml   | 166 ++++
 .../boot/dts/rockchip/rk3328-nanopi-r2.dtsi   |  12 +
 .../dts/rockchip/rk3328-orangepi-r1-plus.dtsi |  12 +
 arch/arm64/boot/dts/rockchip/rk3328-roc.dtsi  |  12 +
 .../boot/dts/rockchip/rk3328-rock-pi-e.dts    |  12 +
 .../arm64/boot/dts/rockchip/rk3328-rock64.dts |  12 +
 arch/arm64/boot/dts/rockchip/rk3328.dtsi      |  39 +
 drivers/clk/rockchip/clk-rk3328.c             |   2 +-
 drivers/phy/rockchip/Kconfig                  |  10 +
 drivers/phy/rockchip/Makefile                 |   1 +
 drivers/phy/rockchip/phy-rockchip-inno-usb3.c | 869 ++++++++++++++++++
 11 files changed, 1146 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/phy/rockchip,inno-usb3phy.yaml
 create mode 100644 drivers/phy/rockchip/phy-rockchip-inno-usb3.c

-- 
2.39.5

On 15/01/2025 02:26, Peter Geis wrote:
> 
> This is my newly reworked phy driver for the rk3328 usb3 phy. It is
> based loosely on my original version, but as of now almost nothing of
> the original driver remains. The main fix here is the discovery of
> BIT(6) in the interrupt enable grf register fixes the usb3 disconnection
> detection (mostly). On occasion an unpopulated usb3 hub will take
> several seconds to disconnect. However this means all of the hack around
> work to reset the usb core manually is no longer required.
> 
BTW, RFC for some maintainers means "do not review, work-in-progress".
For some means "review, but low priority" or "review, but for sure I
have bugs here". I usually review and then someone responds: "it is not
for review, it is just RFC", so to avoid my wasted time please always
mention in cover letter why this is RFC. What do you expect here or why
this is not ready for review as normal patch.

Best regards,
Krzysztof

On Sat, Jan 18, 2025 at 4:08 AM Krzysztof Kozlowski <krzk@kernel.org> wrote:
>
> On 15/01/2025 02:26, Peter Geis wrote:
> >
> > This is my newly reworked phy driver for the rk3328 usb3 phy. It is
> > based loosely on my original version, but as of now almost nothing of
> > the original driver remains. The main fix here is the discovery of
> > BIT(6) in the interrupt enable grf register fixes the usb3 disconnection
> > detection (mostly). On occasion an unpopulated usb3 hub will take
> > several seconds to disconnect. However this means all of the hack around
> > work to reset the usb core manually is no longer required.
> >
> BTW, RFC for some maintainers means "do not review, work-in-progress".
> For some means "review, but low priority" or "review, but for sure I
> have bugs here". I usually review and then someone responds: "it is not
> for review, it is just RFC", so to avoid my wasted time please always
> mention in cover letter why this is RFC. What do you expect here or why
> this is not ready for review as normal patch.

Thank you, that makes sense. I marked it as RFC as I'm aware it isn't
a perfect solution and there's a lot of undefined values. What I was
looking for here was:
- Review for code quality, so if I'm completely off track I can get to
work fixing it. (Thank you so far)
- Sanity testing from others struggling with the issues it fixes.
- Feedback from USB engineers about the issues remaining.
- Hopefully someone with access to the IP can provide insight into the
magic registers.

>
> Best regards,
> Krzysztof

> Wiadomość napisana przez Peter Geis <pgwipeout@gmail.com> w dniu 15 sty 2025, o godz. 02:26:
> 
> 
> This is my newly reworked phy driver for the rk3328 usb3 phy. It is
> based loosely on my original version, but as of now almost nothing of
> the original driver remains. The main fix here is the discovery of
> BIT(6) in the interrupt enable grf register fixes the usb3 disconnection
> detection (mostly). On occasion an unpopulated usb3 hub will take
> several seconds to disconnect. However this means all of the hack around
> work to reset the usb core manually is no longer required.
> 
> I did my best to document all registers I could find. A lot was taken
> from emails between myself and Rockchip's engineers, much thanks to
> William Wu <wulf@rock-chips.com> for their assistance here. The rest of
> the config bits were taken from the rk3328 and rk3228h TRMs and the
> downstream driver. Everything that I couldn't find a definition for is
> prefixed UNK_ or UNKNOWN_. There's a lot of obviously used configuration
> registers with the pipe interface that are also undocumented.
> 
> The only major bug I have so far is my AX88179 usb3 gigabit ethernet
> adapter (Pluggable brand) crashes out when large amounts of data are
> transmitted. I suspect this is related to the RX and TX tuning, as
> leaving it at defaults makes things worse. As I am not a USB3 engineer
> and I do not have the specialized knowledge and hardware to determine
> what is going wrong, I am hoping the mailing list will have an answer
> here.
> 
> Please test and review.
> 
> Very Respectfully,
> Peter Geis
> 
> 
> 
> Peter Geis (6):
>  clk: rockchip: fix wrong clk_ref_usb3otg parent for rk3328
>  dt-bindings: phy: rockchip: add rk3328 usb3 phy
>  phy: rockchip: add driver for rk3328 usb3 phy
>  arm64: dts: rockchip: add rk3328 usb3 phy node
>  arm64: dts: rockchip: enable the usb3 phy on rk3328-roc boards
>  arm64: dts: rockchip: enable the usb3 phy on remaining rk3328 boards
> 
> .../bindings/phy/rockchip,inno-usb3phy.yaml   | 166 ++++
> .../boot/dts/rockchip/rk3328-nanopi-r2.dtsi   |  12 +
> .../dts/rockchip/rk3328-orangepi-r1-plus.dtsi |  12 +
> arch/arm64/boot/dts/rockchip/rk3328-roc.dtsi  |  12 +
> .../boot/dts/rockchip/rk3328-rock-pi-e.dts    |  12 +
> .../arm64/boot/dts/rockchip/rk3328-rock64.dts |  12 +
> arch/arm64/boot/dts/rockchip/rk3328.dtsi      |  39 +
> drivers/clk/rockchip/clk-rk3328.c             |   2 +-
> drivers/phy/rockchip/Kconfig                  |  10 +
> drivers/phy/rockchip/Makefile                 |   1 +
> drivers/phy/rockchip/phy-rockchip-inno-usb3.c | 869 ++++++++++++++++++
> 11 files changed, 1146 insertions(+), 1 deletion(-)
> create mode 100644 Documentation/devicetree/bindings/phy/rockchip,inno-usb3phy.yaml
> create mode 100644 drivers/phy/rockchip/phy-rockchip-inno-usb3.c
> 
> -- 
> 2.39.5
> 
> 

Peter,
I applied this as test run on 6.12.9 and dmesg says:

[   16.368514] rockchip-usb3-phy ff460000.usb3-phy: could not get usb3phy ref clock
[   16.368534] rockchip-usb3-phy ff460000.usb3-phy: parse dt failed -2
[   16.368543] rockchip-usb3-phy ff460000.usb3-phy: probe with driver rockchip-usb3-phy failed with error -2

This is on beelink a1 tvbox.

Do I miss something?

On Wed, Jan 15, 2025 at 6:22 AM Piotr Oniszczuk
<piotr.oniszczuk@gmail.com> wrote:
>
>
>
> > Wiadomość napisana przez Peter Geis <pgwipeout@gmail.com> w dniu 15 sty 2025, o godz. 02:26:
> >
> >
> > This is my newly reworked phy driver for the rk3328 usb3 phy. It is
> > based loosely on my original version, but as of now almost nothing of
> > the original driver remains. The main fix here is the discovery of
> > BIT(6) in the interrupt enable grf register fixes the usb3 disconnection
> > detection (mostly). On occasion an unpopulated usb3 hub will take
> > several seconds to disconnect. However this means all of the hack around
> > work to reset the usb core manually is no longer required.
> >
> > I did my best to document all registers I could find. A lot was taken
> > from emails between myself and Rockchip's engineers, much thanks to
> > William Wu <wulf@rock-chips.com> for their assistance here. The rest of
> > the config bits were taken from the rk3328 and rk3228h TRMs and the
> > downstream driver. Everything that I couldn't find a definition for is
> > prefixed UNK_ or UNKNOWN_. There's a lot of obviously used configuration
> > registers with the pipe interface that are also undocumented.
> >
> > The only major bug I have so far is my AX88179 usb3 gigabit ethernet
> > adapter (Pluggable brand) crashes out when large amounts of data are
> > transmitted. I suspect this is related to the RX and TX tuning, as
> > leaving it at defaults makes things worse. As I am not a USB3 engineer
> > and I do not have the specialized knowledge and hardware to determine
> > what is going wrong, I am hoping the mailing list will have an answer
> > here.
> >
> > Please test and review.
> >
> > Very Respectfully,
> > Peter Geis
> >
> >
> >
> > Peter Geis (6):
> >  clk: rockchip: fix wrong clk_ref_usb3otg parent for rk3328
> >  dt-bindings: phy: rockchip: add rk3328 usb3 phy
> >  phy: rockchip: add driver for rk3328 usb3 phy
> >  arm64: dts: rockchip: add rk3328 usb3 phy node
> >  arm64: dts: rockchip: enable the usb3 phy on rk3328-roc boards
> >  arm64: dts: rockchip: enable the usb3 phy on remaining rk3328 boards
> >
> > .../bindings/phy/rockchip,inno-usb3phy.yaml   | 166 ++++
> > .../boot/dts/rockchip/rk3328-nanopi-r2.dtsi   |  12 +
> > .../dts/rockchip/rk3328-orangepi-r1-plus.dtsi |  12 +
> > arch/arm64/boot/dts/rockchip/rk3328-roc.dtsi  |  12 +
> > .../boot/dts/rockchip/rk3328-rock-pi-e.dts    |  12 +
> > .../arm64/boot/dts/rockchip/rk3328-rock64.dts |  12 +
> > arch/arm64/boot/dts/rockchip/rk3328.dtsi      |  39 +
> > drivers/clk/rockchip/clk-rk3328.c             |   2 +-
> > drivers/phy/rockchip/Kconfig                  |  10 +
> > drivers/phy/rockchip/Makefile                 |   1 +
> > drivers/phy/rockchip/phy-rockchip-inno-usb3.c | 869 ++++++++++++++++++
> > 11 files changed, 1146 insertions(+), 1 deletion(-)
> > create mode 100644 Documentation/devicetree/bindings/phy/rockchip,inno-usb3phy.yaml
> > create mode 100644 drivers/phy/rockchip/phy-rockchip-inno-usb3.c
> >
> > --
> > 2.39.5
> >
> >
>
> Peter,
> I applied this as test run on 6.12.9 and dmesg says:
>
> [   16.368514] rockchip-usb3-phy ff460000.usb3-phy: could not get usb3phy ref clock
> [   16.368534] rockchip-usb3-phy ff460000.usb3-phy: parse dt failed -2
> [   16.368543] rockchip-usb3-phy ff460000.usb3-phy: probe with driver rockchip-usb3-phy failed with error -2
>
> This is on beelink a1 tvbox.
>
> Do I miss something?
>

Good Morning,

That is an interesting failure. The simplest answer is the
`clock-names = "refclk-usb3otg", "usb3phy-otg", "usb3phy-pipe";` line
was corrupted. Please check that when applied it matches the patch
exactly. If you are still having problems, you can send me the
compiled DTB and I'll take a look.

Very Respectfully,
Peter Geis

>

> Wiadomość napisana przez Peter Geis <pgwipeout@gmail.com> w dniu 15 sty 2025, o godz. 13:25:
> 
>> 
>> 
>> Do I miss something?
>> 
> 
> Good Morning,
> 
> That is an interesting failure. The simplest answer is the
> `clock-names = "refclk-usb3otg", "usb3phy-otg", "usb3phy-pipe";` line
> was corrupted. Please check that when applied it matches the patch
> exactly. If you are still having problems, you can send me the
> compiled DTB and I'll take a look.
> 

oh - this check i done as first thing to look on :-)

pls find:

dtsi: https://gist.github.com/warpme/6af9e2778fb06bfb47b64f98fe79d678
and dt: https://gist.github.com/warpme/79340c54c87b2b1e52f2a146461d8c9f


and compiled .dtb

�
���8�d(�,
azw,beelink-a1rockchip,rk3328
+7Beelink A1
aliases=/pinctrl/gpio@ff210000C/pinctrl/gpio@ff220000I/pinctrl/gpio@ff230000O/pinctrl/gpio@ff240000U/serial@ff110000]/serial@ff120000e/serial@ff130000m/i2c@ff150000r/i2c@ff160000w/i2c@ff170000|/i2c@ff180000�/ethernet@ff540000�/mmc@ff500000�/mmc@ff520000
cpus+
cpu@0�cpuarm,cortex-a53�����x�psci�
�
@
&

3�
@@
R�
_
p
{	
cpu@1�cpuarm,cortex-a53�
����x�psci�
�
@
&

3�
@@
R�
_
p
{

cpu@2�cpuarm,cortex-a53�����x�psci�
�
@
&

3�
@@
R�
_
p
{
cpu@3�cpuarm,cortex-a53�����x�psci�
�
@
&

3�
@@
R�
_
p
{
idle-states
�psci
cpu-sleeparm,idle-state
�
�

�x
��
��
{
l2-cachecache
�
�
	
@
(

{
opp-table-0operating-points-v2
{
opp-408000000Q�~�$�@5
opp-600000000#�F~�$�@
opp-8160000000�,B@$�@
opp-1008000000<���$�@
opp-1200000000G���($�@
opp-1296000000M?d� $�@
opp-1392000000R�<� $�@
opp-1416000000Tfr�p$�@
analog-soundsimple-audio-cardAi2sZ
tAnalog A/V�okay
simple-audio-card,cpu�
simple-audio-card,codec�
arm-pmuarm,cortex-a53-pmu0�defg�	

display-subsystemrockchip,display-subsystem�

hdmi-soundsimple-audio-cardAi2sZ�tHDMI�okay
simple-audio-card,cpu�
simple-audio-card,codec�
psciarm,psci-1.0arm,psci-0.2�smc
timerarm,armv8-timer0�






xin24mfixed-clock��
n6�xin24m
{I
i2s@ff000000(rockchip,rk3328-i2srockchip,rk3066-i2s����)
7�i2s_clki2s_hclk�
txrx�okay
{
i2s@ff010000(rockchip,rk3328-i2srockchip,rk3066-i2s��
��*
8�i2s_clki2s_hclk�
txrx�okay
{
i2s@ff020000(rockchip,rk3328-i2srockchip,rk3066-i2s����+
9�i2s_clki2s_hclk�

txrx	�disabled
spdif@ff030000rockchip,rk3328-spdif����.
:
�mclkhclk�

txdefault*�okay
{s
pdm@ff040000
rockchip,pdm���=
R�pdm_clkpdm_hclk�
rxdefaultsleep*4	�disabled
syscon@ff100000&rockchip,rk3328-grfsysconsimple-mfd��
{:
io-domains"rockchip,rk3328-io-voltage-domain�okay>LZhv��
gpiorockchip,rk3328-grf-gpio��
{H
power-controller!rockchip,rk3328-power-controller�

+
{<
power-domain@1�
���
power-domain@6��
power-domain@5� ��
BAB�
power-domain@8���
F�
reboot-modesyscon-reboot-mode���RB��RB��RB�	RB�

serial@ff110000&rockchip,rk3328-uartsnps,dw-apb-uart��
�7�&��baudclkapb_pclk�
txrxdefault* !	�disabled
serial@ff120000&rockchip,rk3328-uartsnps,dw-apb-uart��
�8�'��baudclkapb_pclk�
txrxdefault*"#$	�disabled
serial@ff130000&rockchip,rk3328-uartsnps,dw-apb-uart��
�9�(��baudclkapb_pclk�
txrxdefault*%�okay
i2c@ff150000(rockchip,rk3328-i2crockchip,rk3399-i2c���$
+�7�	�i2cpclkdefault*&	�disabled
i2c@ff160000(rockchip,rk3328-i2crockchip,rk3399-i2c���%
+�8�	�i2cpclkdefault*'�okay�B@#;S
pmic@18rockchip,rk805�(�default*)Rs��*�*�*�*��
regulators
DCDC_REG1
�vdd_logic�
�`��p
regulator-state-mem.FB@
DCDC_REG2�vdd_arm�
�`��p
{
regulator-state-mem.F~�
DCDC_REG3�vcc_ddr
regulator-state-mem.
DCDC_REG4�vcc_io�2Z��2Z�
{
regulator-state-mem.F2Z�
LDO_REG1�vdd_18�w@�w@
{
regulator-state-mem.Fw@
LDO_REG2�vcc_18emmc�w@�w@
{
regulator-state-mem.Fw@
LDO_REG3�vdd_11������
regulator-state-mem.F��
i2c@ff170000(rockchip,rk3328-i2crockchip,rk3399-i2c���&
+�9�	�i2cpclkdefault*+	�disabled
i2c@ff180000(rockchip,rk3328-i2crockchip,rk3399-i2c���'
+�:�	�i2cpclkdefault*,	�disabled
spi@ff190000(rockchip,rk3328-spirockchip,rk3066-spi���1
+� ��spiclkapb_pclk�	
txrxdefault*-./0	�disabled
watchdog@ff1a0000 rockchip,rk3328-wdtsnps,dw-wdt��
�(��
pwm@ff1b0000rockchip,rk3328-pwm���<�	�pwmpclkdefault*1b	�disabled
pwm@ff1b0010rockchip,rk3328-pwm���<�	�pwmpclkdefault*2b	�disabled
pwm@ff1b0020rockchip,rk3328-pwm�� �<�	�pwmpclkdefault*3b	�disabled
pwm@ff1b0030rockchip,rk3328-pwm��0�<�	�pwmpclkdefault*4b	�disabled
dma-controller@ff1f0000arm,pl330arm,primecell��@�
m��	�apb_pclk�

{
thermal-zones
soc-thermal������5
trips
trip-point0�
p���passive
trip-point1�
L���passive
{6
soc-crit�
s��	�critical
cooling-maps
map0�60�	��������
������������������������
map1�6�7��������
tsadc@ff250000rockchip,rk3328-tsadc��%
�:
$�P�$��tsadcapb_pclkinitdefaultsleep*84928<B
Ctsadc-apbO:\
��s
�okay��
{5
efuse@ff260000rockchip,rk3328-efuse��&P
+
�>�pclk_efuse� 
id@7�
cpu-leakage@17�

logic-leakage@19�

cpu-version@1a�
�
{J
adc@ff280000.rockchip,rk3328-saradcrockchip,rk3399-saradc��(
�P�
�%��saradcapb_pclk<VCsaradc-apb	�disabled
gpu@ff300000"rockchip,rk3328-maliarm,mali-450��0T�ZW]XY[\"�gpgpmmupppp0ppmmu0pp1ppmmu1���	�buscore�;�<
<f�=�okay
{7
gpu-opp-tableoperating-points-v2
{;
opp-200000000���0
opp-300000000��0
opp-400000000ׄ�0
opp-500000000�e�0
iommu@ff330200rockchip,iommu��3
�`����aclkiface	�disabled
iommu@ff340800rockchip,iommu��4@�b��
F�aclkiface	�disabled
video-codec@ff350000rockchip,rk3328-vpu��5�	�vdpu��
F
�aclkhclk>�<
iommu@ff350800rockchip,iommu��5@���
F�aclkiface�<
{>
video-codec@ff360000*rockchip,rk3328-vdecrockchip,rk3399-vdec��6�� ��
BAB�axiahbcabaccore
�ABׄׄ�0<������3Cvideo_hvideo_avideo_corevideo_cabacniu_aniu_h?�<
iommu@ff360480rockchip,iommu ��6�@�6�@�J��
B�aclkiface�<
{?
vop@ff370000rockchip,rk3328-vop��7>�� ��x
;�aclk_vopdclk_vophclk_vop<���
Caxiahbdclk@�okay
port
+
{

endpoint@0�$A
{G
iommu@ff373f00rockchip,iommu��7?
� ��
;�aclkiface�okay
{@
iep@ff3a0000(rockchip,rk3328-ieprockchip,rk3228-iep��:��iep��
S�axiahb�<B
iommu@ff3a0800rockchip,iommu��:@��iep_mmu��
S�aclkiface�<
{B
hdmi@ff3c0000rockchip,rk3328-dw-hdmi��<�#��F�iahbisfrcec4C9hdmidefault*DEFO:�okay
{
ports
+
port@0�
endpoint$G
{A
port@1�

codec@ff410000rockchip,rk3328-codec��A��*
�pclkmclkO:�okayCH

{
phy@ff430000rockchip,rk3328-hdmi-phy��C
�S��Iy�sysclkrefoclkrefpclk	�hdmi_phy�NJZcpu-versionk�okay
{C
clock-controller@ff440000(rockchip,rk3328-crurockchip,crusyscon��DO:�
v
�
x=&'(��������ABDC"\5�
H��
4�$�z
III|��
n6
n6
n6���������ׄ�����������������������
n6#�FLG���рxh�xh��рxh�xh��
{
syscon@ff450000.rockchip,rk3328-usb2phy-grfsysconsimple-mfd��E

+

usb2phy@100rockchip,rk3328-usb2phy�
�I�phyclk�usb480m_phy�
{�K�okay
{K
otg-portk$�;<=�otg-bvalidotg-idlinestate�okay
{Y
host-portk�>
�linestate�okay
{Z
usb3-phy@ff460000rockchip,rk3328-usb3phy��F
�_��(�refclk-usb3otgusb3phy-otgusb3phy-pipe0�KLMN�bvalididlinestaterxdet0<}~|��bCusb3phy-u2-porusb3phy-u3-porusb3phy-pipe-macusb3phy-utmi-macusb3phy-utmi-apbusb3phy-pipe-apb+��okay
utmi-port@ff470000rockchip,rk3328-usb3phy-utmi��G�k�okay
{a
pipe-port@ff478000rockchip,rk3328-usb3phy-pipe��G��k�okay
{b
mmc@ff5000000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshc��P@� �
=!JN�biuciuciu-driveciu-sample�
��<mCreset�okay����default*LMNO��
mmc@ff5100000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshc��Q@�
 �
>"KO�biuciuciu-driveciu-sample�
��р<nCreset	�disabled
mmc@ff5200000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshc��R@� �
?#LP�biuciuciu-driveciu-sample�
��р<oCreset�okay��&default*PQR��
ethernet@ff540000rockchip,rk3328-gmac��T
��macirq8�dWXZY��M�stmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_mac<c
CstmmacethO:4BP�okay
df�SS[inputhTsrgmii|default*U���&�
mdiosnps,dwmac-mdio
+
ethernet-phy@0��'�u0�(

{T
ethernet@ff550000rockchip,rk3328-gmac��U
O:��macirq8�TSSU��VI�stmmacethmac_clk_rxmac_clk_txclk_mac_refaclk_macpclk_macclk_macphy<b
CstmmacethsrmiihV4BP[output	�disabled
mdiosnps,dwmac-mdio
+
ethernet-phy@04ethernet-phy-id1234.d400ethernet-phy-ieee802.3-c22��V<ddefault*WX�
{V
usb@ff5800002rockchip,rk3328-usbrockchip,rk3066-usbsnps,dwc2��X��
M�otg�host�	
	
��@ 4Y	9usb2-phy�okay
usb@ff5c0000
generic-ehci��\
��
NK4Z9usb�okaydefault*[\]^_`
usb@ff5d0000
generic-ohci��]
��
NK4Z9usb	�disabled
mmc@ff5f00000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshc��_@� �
@MQ�biuciuciu-driveciu-sample�
��р<hCreset	�disabled
usb@ff600000rockchip,rk3328-dwc3snps,dwc3��`�C�`a��ref_clksuspend_clkbus_clk�host4ab9usb2-phyusb3-phy
	#utmi_wide	,	M	e	�	�	��okay
interrupt-controller@ff811000arm,gic-400	�	�@�����  ��@ ��` �
	
{

crypto@ff060000rockchip,rk3328-crypto��@��
P
Q;�hclk_masterhclk_slavesclk<DCcrypto-rst
pinctrlrockchip,rk3328-pinctrlO:+�
gpio@ff210000rockchip,gpio-bank��!
�3����	�	�
{p
gpio@ff220000rockchip,gpio-bank��"
�4����	�	�
gpio@ff230000rockchip,gpio-bank��#
�5����	�	�
{(
gpio@ff240000rockchip,gpio-bank��$
�6����	�	�
pcfg-pull-up

{e
pcfg-pull-down


{m
pcfg-pull-none

{c
pcfg-pull-none-2ma

)
{l
pcfg-pull-up-2ma

)
pcfg-pull-up-4ma

)
{f
pcfg-pull-none-4ma

)
{i
pcfg-pull-down-4ma


)
pcfg-pull-none-8ma

)
{g
pcfg-pull-up-8ma

)
{h
pcfg-pull-none-12ma

)
{j
pcfg-pull-up-12ma

)
{k
pcfg-output-high
8
{o
pcfg-output-low
D
{n
pcfg-input-high

O
{d
pcfg-input
O
i2c0
i2c0-xfer 
\
c
c
{&
i2c1
i2c1-xfer 
\cc
{'
i2c2
i2c2-xfer 
\

c
c
{+
i2c3
i2c3-xfer 
\cc
{,
i2c3-pins 
\cc
hdmi_i2c
hdmii2c-xfer 
\
c
c
{E
pdm-0
pdmm0-clk
\c
{
pdmm0-fsync
\c
pdmm0-sdi0
\c
{
pdmm0-sdi1
\c
{
pdmm0-sdi2
\c
{
pdmm0-sdi3
\c
{
pdmm0-clk-sleep
\d
{
pdmm0-sdi0-sleep
\d
{
pdmm0-sdi1-sleep
\d
{
pdmm0-sdi2-sleep
\d
{
pdmm0-sdi3-sleep
\d
{
pdmm0-fsync-sleep
\d
tsadc
otp-pin
\
c
{8
otp-out
\

c
{9
uart0
uart0-xfer 
\
	
c

e
{
uart0-cts
\

c
{ 
uart0-rts
\


c
{!
uart0-rts-pin
\

c
uart1
uart1-xfer 
\ce
{"
uart1-cts
\c
{#
uart1-rts
\c
{$
uart1-rts-pin
\c
uart2-0
uart2m0-xfer 
\
c

e
uart2-1
uart2m1-xfer 
\
c

e
{%
spi0-0
spi0m0-clk
\
e
spi0m0-cs0
\
e
spi0m0-tx
\	
e
spi0m0-rx
\

e
spi0m0-cs1
\
e
spi0-1
spi0m1-clk
\e
spi0m1-cs0
\e
spi0m1-tx
\e
spi0m1-rx
\e
spi0m1-cs1
\e
spi0-2
spi0m2-clk
\e
{-
spi0m2-cs0
\e
{0
spi0m2-tx
\
e
{.
spi0m2-rx
\e
{/
i2s1
i2s1-mclk
\
c
i2s1-sclk
\
c
i2s1-lrckrx
\
c
i2s1-lrcktx
\
c
i2s1-sdi
\
c
i2s1-sdo
\
c
i2s1-sdio1
\
c
i2s1-sdio2
\
c
i2s1-sdio3
\
c
i2s1-sleep�
\ddddddddd
i2s2-0
i2s2m0-mclk
\

c
i2s2m0-sclk
\

c
i2s2m0-lrckrx
\

c
i2s2m0-lrcktx
\

c
i2s2m0-sdi
\

c
i2s2m0-sdo
\

c
i2s2m0-sleep`
\
d
d
d
d
d
d
i2s2-1
i2s2m1-mclk
\

c
i2s2m1-sclk
\c
i2sm1-lrckrx
\c
i2s2m1-lrcktx
\c
i2s2m1-sdi
\c
i2s2m1-sdo
\
c
i2s2m1-sleepP
\
dddd
d
spdif-0
spdifm0-tx
\
c
{
spdif-1
spdifm1-tx
\c
spdif-2
spdifm2-tx
\c
sdmmc0-0
sdmmc0m0-pwren
\
f
sdmmc0m0-pin
\f
sdmmc0-1
sdmmc0m1-pwren
\f
sdmmc0m1-pin
\f
sdmmc0
sdmmc0-clk
\

g
{L
sdmmc0-cmd
\

h
{M
sdmmc0-dectn
\

f
{N
sdmmc0-wrprt
\

f
sdmmc0-bus1
\

h
sdmmc0-bus4@
\

h


h

h

h
{O
sdmmc0-pins�
\
f
f
f
f
f
f

f
f
sdmmc0ext
sdmmc0ext-clk
\i
sdmmc0ext-cmd
\f
sdmmc0ext-wrprt
\f
sdmmc0ext-dectn
\
f
sdmmc0ext-bus1
\f
sdmmc0ext-bus4@
\ffff
sdmmc0ext-pins�
\f
fffffff
sdmmc1
sdmmc1-clk
\

g
sdmmc1-cmd
\


h
sdmmc1-pwren
\

h
sdmmc1-wrprt
\

h
sdmmc1-dectn
\

h
sdmmc1-bus1
\

h
sdmmc1-bus4@
\

h

h

h

h
sdmmc1-pins�
\
f

f
f
f
f
f
f
f
f
emmc
emmc-clk
\j
{P
emmc-cmd
\k
{Q
emmc-pwren
\c
emmc-rstnout
\c
emmc-bus1
\k
emmc-bus4@
\kkkk
emmc-bus8�
\kkkkkkkk
{R
pwm0
pwm0-pin
\
c
{1
pwm1
pwm1-pin
\
c
{2
pwm2
pwm2-pin
\
c
{3
pwmir
pwmir-pin
\
c
{4
gmac-1
rgmiim1-pins
`
\
g

i
i
g
i
i
i

i
i
g
	g
i
i
g
g
g
g
i
g
g
g
g
{U
rmiim1-pins

\
l
j
l
l
l
l

l
l
j
	j
c
c
c
c
c
c
gmac2phy
fephyled-speed10
\
c
fephyled-duplex
\c
fephyled-rxm1
\c
{W
fephyled-txm1
\c
fephyled-linkm1
\c
{X
tsadc_pin
tsadc-int
\
c
tsadc-pin
\
c
hdmi_pin
hdmi-cec
\
c
{D
hdmi-hpd
\
m
{F
cif-0
dvp-d2d9-m0�
\ccccc	c
cc
cccc
cif-1
dvp-d2d9-m1�
\cccccccc
cccc
pmic
pmic-int-l
\e
{)
usb3
usb30-host-drv
\c
{q
usb2
usb20-host-drv
\
c
{r
wifi
bt-dis
\n
{[
bt-wake-host
\e
{\
chip-en
\n
{]
host-wake-bt
\o
{^
wl-dis
\n
{_
wl-wake-host
\
e
{`
chosen
jserial2:1500000n8
external-gmac-clockfixed-clock�sY@�gmac_clkin�
{S
usb3-current-switchregulator-fixed
v
�pdefault*q�vcc_host_5v
�*
vcc-host1-5v-regulatorregulator-fixed
v
�pdefault*r
�vcc_host1_5v
�*
vcc-sysregulator-fixed�vcc_sys�LK@�LK@
{*
vdd-gpuregulator-fixed�vdd_gpu��0��0
{=
ir-receivergpio-ir-receiverH(

�rc-beelink-gs1
spdif-soundsimple-audio-cardtSPDIF
simple-audio-card,cpu�s
simple-audio-card,codec�t
spdif-ditlinux,spdif-dit
{t
openvfd	open,vfd
�openvfd
�(
�(
�(

�

�
	�okay	compatibleinterrupt-parent#address-cells#size-cellsmodelgpio0gpio1gpio2gpio3serial0serial1serial2i2c0i2c1i2c2i2c3ethernet0mmc0mmc1device_typeregclocks#cooling-cellscpu-idle-statesdynamic-power-coefficientenable-methodoperating-points-v2i-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachecpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendsimple-audio-card,formatsimple-audio-card,mclk-fssimple-audio-card,namestatussound-daiinterruptsinterrupt-affinityports#clock-cellsclock-frequencyclock-output-namesclock-namesdmasdma-names#sound-dai-cellspinctrl-namespinctrl-0pinctrl-1vccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplypmuio-supplygpio-controller#gpio-cells#power-domain-cellsoffsetmode-normalmode-recoverymode-bootloadermode-loaderreg-io-widthreg-shifti2c-scl-falling-time-nsi2c-scl-rising-time-nsrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onregulator-boot-onregulator-on-in-suspendregulator-suspend-microvolt#pwm-cellsarm,pl330-periph-burst#dma-cellspolling-delay-passivepolling-delaysustainable-powerthermal-sensorstemperaturehysteresistripcooling-devicecontributionassigned-clocksassigned-clock-ratespinctrl-2resetsreset-namesrockchip,grfrockchip,hw-tshut-temp#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarityrockchip,efuse-sizebits#io-channel-cellsinterrupt-namespower-domainsmali-supply#iommu-cellsiommusremote-endpointphysphy-namesmute-gpiosnvmem-cellsnvmem-cell-names#phy-cells#reset-cellsassigned-clock-parentsrangesfifo-depthmax-frequencybus-widthcap-mmc-highspeedcap-sd-highspeeddisable-wpvmmc-supplyvqmmc-supplymmc-ddr-1_8vno-sdno-sdionon-removabletx-fifo-depthrx-fifo-depthsnps,txpblclock_in_outphy-handlephy-modephy-supplysnps,aalsnps,pbltx_delayrx_delayreset-assert-usreset-deassert-usreset-gpiosphy-is-integrateddr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephy_typesnps,dis-del-phy-power-chg-quirksnps,dis_enblslpm_quirksnps,dis-tx-ipgap-linecheck-quirksnps,dis-u2-freeclk-exists-quirksnps,dis_u2_susphy_quirksnps,dis_u3_susphy_quirk#interrupt-cellsinterrupt-controllerbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highoutput-lowinput-enablerockchip,pinsstdout-pathenable-active-highgpiovin-supplylinux,rc-map-namedev_nameopenvfd_gpio_datopenvfd_gpio_clkopenvfd_gpio_stbopenvfd_charsopenvfd_dot_bitsopenvfd_display_type

On Wed, Jan 15, 2025 at 7:35 AM Piotr Oniszczuk
<piotr.oniszczuk@gmail.com> wrote:
>
>
>
> > Wiadomość napisana przez Peter Geis <pgwipeout@gmail.com> w dniu 15 sty 2025, o godz. 13:25:
> >
> >>
> >>
> >> Do I miss something?
> >>
> >
> > Good Morning,
> >
> > That is an interesting failure. The simplest answer is the
> > `clock-names = "refclk-usb3otg", "usb3phy-otg", "usb3phy-pipe";` line
> > was corrupted. Please check that when applied it matches the patch
> > exactly. If you are still having problems, you can send me the
> > compiled DTB and I'll take a look.
> >
>
> oh - this check i done as first thing to look on :-)
>
> pls find:
>
> dtsi: https://gist.github.com/warpme/6af9e2778fb06bfb47b64f98fe79d678
> and dt: https://gist.github.com/warpme/79340c54c87b2b1e52f2a146461d8c9f
>
>
> and compiled .dtb

It all looks good.
Do you have any CRU errors in the boot log?
Can you check for the presence of clk_ref_usb3otg in
/sys/kernel/debug/clk/clk_summary?

>

> Wiadomość napisana przez Peter Geis <pgwipeout@gmail.com> w dniu 15 sty 2025, o godz. 14:15:
> 
>> 
>> 
>> pls find:
>> 
>> dtsi: https://gist.github.com/warpme/6af9e2778fb06bfb47b64f98fe79d678
>> and dt: https://gist.github.com/warpme/79340c54c87b2b1e52f2a146461d8c9f
>> 
>> 
>> and compiled .dtb
> 
> It all looks good.
> Do you have any CRU errors in the boot log?
> Can you check for the presence of clk_ref_usb3otg in
> /sys/kernel/debug/clk/clk_summary?
> 
>> 

cru errors in dmesg - seems no any.
here is my dmesg: https://gist.github.com/warpme/ecf38482cc88fb68471355d011ecf974

For clk_ref_usb3otg i’m getting following:

root@myth-frontend-e67a8de4c815:~ # cat /sys/kernel/debug/clk/clk_summary | grep usb3
    clk_usb3otg_suspend              0       0        0        30770       0          0     50000      N      deviceless                      no_connection_id
    clk_usb3otg_ref                  0       0        0        24000000    0          0     50000      N      deviceless                      no_connection_id
    clk_ref_usb3otg                  0       0        0        24000000    0          0     50000      Y      deviceless                      no_connection_id
                   pclk_usb3_grf     0       0        0        75000000    0          0     50000      Y                     deviceless                      no_connection_id
                   pclk_usb3phy_pipe 0       0        0        75000000    0          0     50000      N                     deviceless                      no_connection_id
                   pclk_usb3phy_otg  0       0        0        75000000    0          0     50000      N                     deviceless                      no_connection_id
          clk_ref_usb3otg_src        0       0        0        37500000    0          0     50000      N            deviceless                      no_connection_id
                   aclk_usb3otg      0       0        0        150000000   0          0     50000      N                     deviceless                      no_connection_id

On Wed, Jan 15, 2025 at 8:25 AM Piotr Oniszczuk
<piotr.oniszczuk@gmail.com> wrote:
>
>
>
> > Wiadomość napisana przez Peter Geis <pgwipeout@gmail.com> w dniu 15 sty 2025, o godz. 14:15:
> >
> >>
> >>
> >> pls find:
> >>
> >> dtsi: https://gist.github.com/warpme/6af9e2778fb06bfb47b64f98fe79d678
> >> and dt: https://gist.github.com/warpme/79340c54c87b2b1e52f2a146461d8c9f
> >>
> >>
> >> and compiled .dtb
> >
> > It all looks good.
> > Do you have any CRU errors in the boot log?
> > Can you check for the presence of clk_ref_usb3otg in
> > /sys/kernel/debug/clk/clk_summary?
> >
> >>
>
> cru errors in dmesg - seems no any.
> here is my dmesg: https://gist.github.com/warpme/ecf38482cc88fb68471355d011ecf974
>
> For clk_ref_usb3otg i’m getting following:
>
> root@myth-frontend-e67a8de4c815:~ # cat /sys/kernel/debug/clk/clk_summary | grep usb3
>     clk_usb3otg_suspend              0       0        0        30770       0          0     50000      N      deviceless                      no_connection_id
>     clk_usb3otg_ref                  0       0        0        24000000    0          0     50000      N      deviceless                      no_connection_id
>     clk_ref_usb3otg                  0       0        0        24000000    0          0     50000      Y      deviceless                      no_connection_id
>                    pclk_usb3_grf     0       0        0        75000000    0          0     50000      Y                     deviceless                      no_connection_id
>                    pclk_usb3phy_pipe 0       0        0        75000000    0          0     50000      N                     deviceless                      no_connection_id
>                    pclk_usb3phy_otg  0       0        0        75000000    0          0     50000      N                     deviceless                      no_connection_id
>           clk_ref_usb3otg_src        0       0        0        37500000    0          0     50000      N            deviceless                      no_connection_id
>                    aclk_usb3otg      0       0        0        150000000   0          0     50000      N                     deviceless                      no_connection_id
>

I'm at a loss here, I applied the patches to a clean 6.9 tree and even
built it as a module (thank you for the sentinel). I have no issues.
I'm wondering if it's your .config or something about your bootloader.

>

> Wiadomość napisana przez Peter Geis <pgwipeout@gmail.com> w dniu 16 sty 2025, o godz. 15:02:
> 
>> 
> 
> I'm at a loss here, I applied the patches to a clean 6.9 tree and even
>> 

oh maybe issue is in kernel age?
6.9 seems a bit quite old.
i’m on 6.12.9….

On Thu, Jan 16, 2025 at 9:35 AM Piotr Oniszczuk
<piotr.oniszczuk@gmail.com> wrote:
>
>
>
> > Wiadomość napisana przez Peter Geis <pgwipeout@gmail.com> w dniu 16 sty 2025, o godz. 15:02:
> >
> >>
> >
> > I'm at a loss here, I applied the patches to a clean 6.9 tree and even
> >>
>
> oh maybe issue is in kernel age?
> 6.9 seems a bit quite old.
> i’m on 6.12.9….

The patches were prepared and tested against 6.13-rc1, but nothing has
changed significantly in the kernel in regards to rk3328 clock
handling in several years. I jumped back to 6.9 due to dyslexia.

On Wed, 15 Jan 2025 01:26:21 +0000, Peter Geis wrote:
> This is my newly reworked phy driver for the rk3328 usb3 phy. It is
> based loosely on my original version, but as of now almost nothing of
> the original driver remains. The main fix here is the discovery of
> BIT(6) in the interrupt enable grf register fixes the usb3 disconnection
> detection (mostly). On occasion an unpopulated usb3 hub will take
> several seconds to disconnect. However this means all of the hack around
> work to reset the usb core manually is no longer required.
> 
> [...]

Applied, thanks!

[1/6] clk: rockchip: fix wrong clk_ref_usb3otg parent for rk3328
      commit: a9e60f1ffe1ca57d6af6a2573e2f950e76efbf5b

Best regards,
-- 
Heiko Stuebner <heiko@sntech.de>