From: Xianwei Zhao <xianwei.zhao@amlogic.com>
Add the dt-bindings for Amlogic pin controller, and add a new
dt-binding header file which document the GPIO bank names of
all Amlogic subsequent SoCs.
Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
---
.../bindings/pinctrl/amlogic,pinctrl-a4.yaml | 132 +++++++++++++++++++++
include/dt-bindings/pinctrl/amlogic,pinctrl.h | 46 +++++++
2 files changed, 178 insertions(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/amlogic,pinctrl-a4.yaml b/Documentation/devicetree/bindings/pinctrl/amlogic,pinctrl-a4.yaml
new file mode 100644
index 000000000000..bc2764549471
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/amlogic,pinctrl-a4.yaml
@@ -0,0 +1,132 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/amlogic,pinctrl-a4.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Amlogic pinmux controller
+
+maintainers:
+ - Xianwei Zhao <xianwei.zhao@amlogic.com>
+
+allOf:
+ - $ref: pinctrl.yaml#
+
+properties:
+ compatible:
+ const: amlogic,pinctrl-a4
+
+ "#address-cells":
+ const: 2
+
+ "#size-cells":
+ const: 2
+
+ ranges: true
+
+required:
+ - compatible
+ - "#address-cells"
+ - "#size-cells"
+
+patternProperties:
+ "^gpio@[0-9a-f]+$":
+ type: object
+
+ properties:
+ reg:
+ minItems: 1
+ items:
+ - description: pin config register
+ - description: pin mux setting register (some special pin fixed function)
+ - description: pin drive strength register (optionanl)
+
+ reg-names:
+ minItems: 1
+ items:
+ - const: gpio
+ - const: mux
+ - const: ds
+
+ gpio-controller: true
+
+ "#gpio-cells":
+ const: 2
+
+ gpio-ranges:
+ maxItems: 1
+
+ bank-number:
+ description: |
+ bank-number are provided by the pin controller header file at:
+ <include/dt-bindings/pinctrl/amlogic,pinctrl.h>
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ required:
+ - reg
+ - reg-names
+ - gpio-controller
+ - "#gpio-cells"
+ - gpio-ranges
+ - bank-number
+
+ additionalProperties: false
+
+ "^func-[0-9a-z-]+$":
+ type: object
+ patternProperties:
+ "^group-[0-9a-z-]+$":
+ type: object
+ allOf:
+ - $ref: /schemas/pinctrl/pincfg-node.yaml
+ - $ref: /schemas/pinctrl/pinmux-node.yaml
+ additionalProperties: false
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/pinctrl/amlogic,pinctrl.h>
+ apb {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ periphs_pinctrl: pinctrl {
+ compatible = "amlogic,pinctrl-a4";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gpio@14 {
+ reg = <0 0x14 0 0x10>,
+ <0 0x14 0 0x10>;
+ reg-names = "gpio", "mux";
+ gpio-controller;
+ #gpio-cells = <2>;
+ bank-number = <AMLOGIC_GPIO_B>;
+ gpio-ranges = <&periphs_pinctrl 0 8 10>;
+ };
+
+ func-uart-b {
+ group-default {
+ pinmux = <AML_PINMUX(AMLOGIC_GPIO_B, 1, 4)>;
+ bias-pull-up;
+ drive-strength-microamp = <4000>;
+ };
+
+ group-pins1 {
+ pinmux = <AML_PINMUX(AMLOGIC_GPIO_B, 5, 2)>;
+ bias-pull-up;
+ drive-strength-microamp = <4000>;
+ };
+ };
+
+ func-uart-c {
+ group-default {
+ pinmux = <AML_PINMUX(AMLOGIC_GPIO_B, 3, 1)>,
+ <AML_PINMUX(AMLOGIC_GPIO_B, 2, 1)>;
+ bias-pull-up;
+ drive-strength-microamp = <4000>;
+ };
+ };
+ };
+ };
diff --git a/include/dt-bindings/pinctrl/amlogic,pinctrl.h b/include/dt-bindings/pinctrl/amlogic,pinctrl.h
new file mode 100644
index 000000000000..7d40aecc7147
--- /dev/null
+++ b/include/dt-bindings/pinctrl/amlogic,pinctrl.h
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright (c) 2024 Amlogic, Inc. All rights reserved.
+ * Author: Xianwei Zhao <xianwei.zhao@amlogic.com>
+ */
+
+#ifndef _DT_BINDINGS_AMLOGIC_PINCTRL_H
+#define _DT_BINDINGS_AMLOGIC_PINCTRL_H
+/* Normal PIN bank */
+#define AMLOGIC_GPIO_A 0
+#define AMLOGIC_GPIO_B 1
+#define AMLOGIC_GPIO_C 2
+#define AMLOGIC_GPIO_D 3
+#define AMLOGIC_GPIO_E 4
+#define AMLOGIC_GPIO_F 5
+#define AMLOGIC_GPIO_G 6
+#define AMLOGIC_GPIO_H 7
+#define AMLOGIC_GPIO_I 8
+#define AMLOGIC_GPIO_J 9
+#define AMLOGIC_GPIO_K 10
+#define AMLOGIC_GPIO_L 11
+#define AMLOGIC_GPIO_M 12
+#define AMLOGIC_GPIO_N 13
+#define AMLOGIC_GPIO_O 14
+#define AMLOGIC_GPIO_P 15
+#define AMLOGIC_GPIO_Q 16
+#define AMLOGIC_GPIO_R 17
+#define AMLOGIC_GPIO_S 18
+#define AMLOGIC_GPIO_T 19
+#define AMLOGIC_GPIO_U 20
+#define AMLOGIC_GPIO_V 21
+#define AMLOGIC_GPIO_W 22
+#define AMLOGIC_GPIO_X 23
+#define AMLOGIC_GPIO_Y 24
+#define AMLOGIC_GPIO_Z 25
+
+/* Special PIN bank */
+#define AMLOGIC_GPIO_DV 26
+#define AMLOGIC_GPIO_AO 27
+#define AMLOGIC_GPIO_CC 28
+#define AMLOGIC_GPIO_TEST_N 29
+#define AMLOGIC_GPIO_ANALOG 30
+
+#define AML_PINMUX(bank, offset, mode) (((((bank) << 8) + (offset)) << 8) | (mode))
+
+#endif /* _DT_BINDINGS_AMLOGIC_PINCTRL_H */
--
2.37.1On Wed, Jan 15, 2025 at 02:41:59PM +0800, Xianwei Zhao wrote:
> +properties:
> + compatible:
> + const: amlogic,pinctrl-a4
> +
> + "#address-cells":
> + const: 2
> +
> + "#size-cells":
> + const: 2
Why this moved to '2'? 32-bit was not enough?
> +
> + ranges: true
> +
> +required:
> + - compatible
> + - "#address-cells"
> + - "#size-cells"
Keep required after patternProperties
> +
> +patternProperties:
> + "^gpio@[0-9a-f]+$":
> + type: object
> +
> + properties:
> + reg:
> + minItems: 1
> + items:
> + - description: pin config register
> + - description: pin mux setting register (some special pin fixed function)
> + - description: pin drive strength register (optionanl)
typo: optional
> +
> + reg-names:
> + minItems: 1
> + items:
> + - const: gpio
> + - const: mux
> + - const: ds
> +
> + gpio-controller: true
> +
> + "#gpio-cells":
> + const: 2
> +
> + gpio-ranges:
> + maxItems: 1
> +
> + bank-number:
> + description: |
> + bank-number are provided by the pin controller header file at:
> + <include/dt-bindings/pinctrl/amlogic,pinctrl.h>
> + $ref: /schemas/types.yaml#/definitions/uint32
gpio-ranges tell you that, don't they?
Anyway, you would need here minimum and maximum.
> +
> + required:
> + - reg
> + - reg-names
> + - gpio-controller
> + - "#gpio-cells"
> + - gpio-ranges
> + - bank-number
> +
> + additionalProperties: false
> +
> + "^func-[0-9a-z-]+$":
> + type: object
> + patternProperties:
> + "^group-[0-9a-z-]+$":
> + type: object
> + allOf:
> + - $ref: /schemas/pinctrl/pincfg-node.yaml
> + - $ref: /schemas/pinctrl/pinmux-node.yaml
Missing required pinmux and maybe other properties.
> + additionalProperties: false
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/pinctrl/amlogic,pinctrl.h>
> + apb {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + periphs_pinctrl: pinctrl {
> + compatible = "amlogic,pinctrl-a4";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + gpio@14 {
> + reg = <0 0x14 0 0x10>,
> + <0 0x14 0 0x10>;
One line.
> + reg-names = "gpio", "mux";
> + gpio-controller;
> + #gpio-cells = <2>;
> + bank-number = <AMLOGIC_GPIO_B>;
> + gpio-ranges = <&periphs_pinctrl 0 8 10>;
> + };
Best regards,
Krzysztof
Hi Krzysztof,
Thanks for reply.
On 2025/1/17 16:48, Krzysztof Kozlowski wrote:
> [ EXTERNAL EMAIL ]
>
> On Wed, Jan 15, 2025 at 02:41:59PM +0800, Xianwei Zhao wrote:
>> +properties:
>> + compatible:
>> + const: amlogic,pinctrl-a4
>> +
>> + "#address-cells":
>> + const: 2
>> +
>> + "#size-cells":
>> + const: 2
>
> Why this moved to '2'? 32-bit was not enough?
>
Previously only represented a register address offset value, now
directly represents a register, through 'ranges" which to represent.
32-bit is enough, but since APB bus is defined as 64-bit, here is
following. I increase support for 32-bit. Like the following values:
"#address-cells":
enum: [1, 2]
"#size-cells":
enum: [1, 2]
>> +
>> + ranges: true
>> +
>> +required:
>> + - compatible
>> + - "#address-cells"
>> + - "#size-cells"
>
> Keep required after patternProperties
>
Will do.
>> +
>> +patternProperties:
>> + "^gpio@[0-9a-f]+$":
>> + type: object
>> +
>> + properties:
>> + reg:
>> + minItems: 1
>> + items:
>> + - description: pin config register
>> + - description: pin mux setting register (some special pin fixed function)
>> + - description: pin drive strength register (optionanl)
>
> typo: optional
>
Will fix.
>> +
>> + reg-names:
>> + minItems: 1
>> + items:
>> + - const: gpio
>> + - const: mux
>> + - const: ds
>> +
>> + gpio-controller: true
>> +
>> + "#gpio-cells":
>> + const: 2
>> +
>> + gpio-ranges:
>> + maxItems: 1
>> +
>> + bank-number:
>> + description: |
>> + bank-number are provided by the pin controller header file at:
>> + <include/dt-bindings/pinctrl/amlogic,pinctrl.h>
>> + $ref: /schemas/types.yaml#/definitions/uint32
>
> gpio-ranges tell you that, don't they?
>
Yes. Get it from gpio-ranges.
> Anyway, you would need here minimum and maximum.
>
Will drop bank-number property.
>> +
>> + required:
>> + - reg
>> + - reg-names
>> + - gpio-controller
>> + - "#gpio-cells"
>> + - gpio-ranges
>> + - bank-number
>> +
>> + additionalProperties: false
>> +
>> + "^func-[0-9a-z-]+$":
>> + type: object
>> + patternProperties:
>> + "^group-[0-9a-z-]+$":
>> + type: object
>> + allOf:
>> + - $ref: /schemas/pinctrl/pincfg-node.yaml
>> + - $ref: /schemas/pinctrl/pinmux-node.yaml
>
> Missing required pinmux and maybe other properties.
>
Will add required.
>> + additionalProperties: false
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> + - |
>> + #include <dt-bindings/pinctrl/amlogic,pinctrl.h>
>> + apb {
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + periphs_pinctrl: pinctrl {
>> + compatible = "amlogic,pinctrl-a4";
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges;
>> +
>> + gpio@14 {
>> + reg = <0 0x14 0 0x10>,
>> + <0 0x14 0 0x10>;
>
> One line.
>
Will do.
>> + reg-names = "gpio", "mux";
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> + bank-number = <AMLOGIC_GPIO_B>;
>> + gpio-ranges = <&periphs_pinctrl 0 8 10>;
>> + };
>
> Best regards,
> Krzysztof
>
On 20/01/2025 06:57, Xianwei Zhao wrote: > Hi Krzysztof, > Thanks for reply. > > On 2025/1/17 16:48, Krzysztof Kozlowski wrote: >> [ EXTERNAL EMAIL ] >> >> On Wed, Jan 15, 2025 at 02:41:59PM +0800, Xianwei Zhao wrote: >>> +properties: >>> + compatible: >>> + const: amlogic,pinctrl-a4 >>> + >>> + "#address-cells": >>> + const: 2 >>> + >>> + "#size-cells": >>> + const: 2 >> >> Why this moved to '2'? 32-bit was not enough? >> > Previously only represented a register address offset value, now > directly represents a register, through 'ranges" which to represent. > 32-bit is enough, but since APB bus is defined as 64-bit, here is Changelog was silent on this. > following. I increase support for 32-bit. Like the following values: No, just keep one of these. Best regards, Krzysztof
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