Add support for LLCC V6. V6 adds several additional usecase IDs,
rearrages several registers and offsets, and supports slice IDs
over 31, so add a new function for programming LLCC V6.
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
---
drivers/soc/qcom/llcc-qcom.c | 212 ++++++++++++++++++++++++++++++++++++-
include/linux/soc/qcom/llcc-qcom.h | 8 ++
2 files changed, 216 insertions(+), 4 deletions(-)
diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c
index 56823b6a2facc4345265e29b60da24a391e3707d..4379b5baa011aa850a2b65ec20b32519d9331be4 100644
--- a/drivers/soc/qcom/llcc-qcom.c
+++ b/drivers/soc/qcom/llcc-qcom.c
@@ -35,6 +35,9 @@
#define ATTR0_RES_WAYS_MASK GENMASK(15, 0)
#define ATTR0_BONUS_WAYS_MASK GENMASK(31, 16)
#define ATTR0_BONUS_WAYS_SHIFT 16
+#define ATTR2_PROBE_TARGET_WAYS_SHIFT 4
+#define ATTR2_FIXED_SIZE_SHIFT 8
+#define ATTR2_PRIORITY_SHIFT 12
#define LLCC_STATUS_READ_DELAY 100
#define CACHE_LINE_SIZE_SHIFT 6
@@ -49,6 +52,10 @@
#define LLCC_TRP_ATTR0_CFGn(n) (0x21000 + SZ_8 * n)
#define LLCC_TRP_ATTR1_CFGn(n) (0x21004 + SZ_8 * n)
#define LLCC_TRP_ATTR2_CFGn(n) (0x21100 + SZ_4 * n)
+#define LLCC_V6_TRP_ATTR0_CFGn(n) (0x41000 + SZ_64 * n)
+#define LLCC_V6_TRP_ATTR1_CFGn(n) (0x41008 + SZ_64 * n)
+#define LLCC_V6_TRP_ATTR2_CFGn(n) (0x41010 + SZ_64 * n)
+#define LLCC_V6_TRP_ATTR3_CFGn(n) (0x41014 + SZ_64 * n)
#define LLCC_TRP_SCID_DIS_CAP_ALLOC 0x21f00
#define LLCC_TRP_PCB_ACT 0x21f04
@@ -62,10 +69,22 @@
#define LLCC_TRP_ALGO_CFG7 0x21f28
#define LLCC_TRP_WRSC_CACHEABLE_EN 0x21f2c
#define LLCC_TRP_ALGO_CFG8 0x21f30
+#define LLCC_V6_TRP_SCID_DIS_CAP_ALLOC 0x42000
+#define LLCC_V6_TRP_ALGO_CFG1 0x42008
+#define LLCC_V6_TRP_ALGO_CFG2 0x42010
+#define LLCC_V6_TRP_ALGO_CFG3 0x42018
+#define LLCC_V6_TRP_ALGO_CFG4 0x42020
+#define LLCC_V6_TRP_ALGO_CFG5 0x42028
+#define LLCC_V6_TRP_ALGO_CFG6 0x42030
+#define LLCC_V6_TRP_ALGO_CFG7 0x42038
+#define LLCC_V6_TRP_ALGO_CFG8 0x42040
+#define LLCC_V6_TRP_WRSC_EN 0x42080
+#define LLCC_V6_TRP_WRSC_CACHEABLE_EN 0x42088
#define LLCC_VERSION_2_0_0_0 0x02000000
#define LLCC_VERSION_2_1_0_0 0x02010000
#define LLCC_VERSION_4_1_0_0 0x04010000
+#define LLCC_VERSION_6_0_0_0 0X06000000
/**
* struct llcc_slice_config - Data associated with the llcc slice
@@ -3161,6 +3180,33 @@ static const struct llcc_edac_reg_offset llcc_v2_1_edac_reg_offset = {
.drp_ecc_db_err_syn0 = 0x52120,
};
+static const struct llcc_edac_reg_offset llcc_v6_edac_reg_offset = {
+ .trp_ecc_error_status0 = 0x47448,
+ .trp_ecc_error_status1 = 0x47450,
+ .trp_ecc_sb_err_syn0 = 0x47490,
+ .trp_ecc_db_err_syn0 = 0x474d0,
+ .trp_ecc_error_cntr_clear = 0x47444,
+ .trp_interrupt_0_status = 0x47600,
+ .trp_interrupt_0_clear = 0x47604,
+ .trp_interrupt_0_enable = 0x47608,
+
+ /* LLCC Common registers */
+ .cmn_status0 = 0x6400c,
+ .cmn_interrupt_0_enable = 0x6401c,
+ .cmn_interrupt_2_enable = 0x6403c,
+
+ /* LLCC DRP registers */
+ .drp_ecc_error_cfg = 0x80000,
+ .drp_ecc_error_cntr_clear = 0x80004,
+ .drp_interrupt_status = 0x80020,
+ .drp_interrupt_clear = 0x80028,
+ .drp_interrupt_enable = 0x8002c,
+ .drp_ecc_error_status0 = 0x820f4,
+ .drp_ecc_error_status1 = 0x820f8,
+ .drp_ecc_sb_err_syn0 = 0x820fc,
+ .drp_ecc_db_err_syn0 = 0x82120,
+};
+
/* LLCC register offset starting from v1.0.0 */
static const u32 llcc_v1_reg_offset[] = {
[LLCC_COMMON_HW_INFO] = 0x00030000,
@@ -3173,6 +3219,13 @@ static const u32 llcc_v2_1_reg_offset[] = {
[LLCC_COMMON_STATUS0] = 0x0003400c,
};
+/* LLCC register offset starting from v6.0.0 */
+static const u32 llcc_v6_reg_offset[] = {
+ [LLCC_COMMON_HW_INFO] = 0x00064000,
+ [LLCC_COMMON_STATUS0] = 0x0006400c,
+
+};
+
static const struct qcom_llcc_config qcs615_cfg[] = {
{
.sct_data = qcs615_data,
@@ -3869,6 +3922,149 @@ static int _qcom_llcc_cfg_program(const struct llcc_slice_config *config,
return ret;
}
+static int _qcom_llcc_cfg_program_v6(const struct llcc_slice_config *config,
+ const struct qcom_llcc_config *cfg)
+{
+ int ret;
+ u32 attr0_cfg, attr1_cfg, attr2_cfg, attr3_cfg;
+ u32 attr0_val, attr1_val, attr2_val, attr3_val;
+ u32 disable_cap_alloc, wren, wr_cache_en;
+ u32 stale_en, stale_cap_en, mru_uncap_en, mru_rollover;
+ u32 alloc_oneway_en, ovcap_en, ovcap_prio, vict_prio;
+ u32 slice_offset, reg_offset;
+ struct llcc_slice_desc *desc;
+ const struct llcc_slice_config *slice_cfg;
+ u32 sz = 0;
+
+ slice_cfg = cfg->sct_data;
+ sz = cfg->size;
+
+ attr0_cfg = LLCC_V6_TRP_ATTR0_CFGn(config->slice_id);
+ attr1_cfg = LLCC_V6_TRP_ATTR1_CFGn(config->slice_id);
+ attr2_cfg = LLCC_V6_TRP_ATTR2_CFGn(config->slice_id);
+ attr3_cfg = LLCC_V6_TRP_ATTR3_CFGn(config->slice_id);
+
+ attr0_val = config->res_ways;
+ attr1_val = config->bonus_ways;
+ attr2_val = config->cache_mode;
+ attr2_val |= config->probe_target_ways << ATTR2_PROBE_TARGET_WAYS_SHIFT;
+ attr2_val |= config->fixed_size << ATTR2_FIXED_SIZE_SHIFT;
+ attr2_val |= config->priority << ATTR2_PRIORITY_SHIFT;
+
+ attr3_val = MAX_CAP_TO_BYTES(config->max_cap);
+ attr3_val /= drv_data->num_banks;
+ attr3_val >>= CACHE_LINE_SIZE_SHIFT;
+
+ ret = regmap_write(drv_data->bcast_regmap, attr0_cfg, attr0_val);
+ if (ret)
+ return ret;
+
+ ret = regmap_write(drv_data->bcast_regmap, attr1_cfg, attr1_val);
+ if (ret)
+ return ret;
+
+ ret = regmap_write(drv_data->bcast_regmap, attr2_cfg, attr2_val);
+ if (ret)
+ return ret;
+
+ ret = regmap_write(drv_data->bcast_regmap, attr3_cfg, attr3_val);
+ if (ret)
+ return ret;
+
+ slice_offset = config->slice_id % 32;
+ reg_offset = (config->slice_id / 32) * 4;
+
+ if (!cfg->skip_llcc_cfg) {
+ disable_cap_alloc = config->dis_cap_alloc << slice_offset;
+ ret = regmap_write(drv_data->bcast_regmap,
+ LLCC_V6_TRP_SCID_DIS_CAP_ALLOC + reg_offset,
+ disable_cap_alloc);
+
+ if (ret)
+ return ret;
+ }
+
+ wren = config->write_scid_en << slice_offset;
+ ret = regmap_update_bits(drv_data->bcast_regmap,
+ LLCC_V6_TRP_WRSC_EN + reg_offset,
+ BIT(slice_offset), wren);
+ if (ret)
+ return ret;
+
+ wr_cache_en = config->write_scid_cacheable_en << slice_offset;
+ ret = regmap_update_bits(drv_data->bcast_regmap,
+ LLCC_V6_TRP_WRSC_CACHEABLE_EN + reg_offset,
+ BIT(slice_offset), wr_cache_en);
+ if (ret)
+ return ret;
+
+ stale_en = config->stale_en << slice_offset;
+ ret = regmap_update_bits(drv_data->bcast_regmap,
+ LLCC_V6_TRP_ALGO_CFG1 + reg_offset,
+ BIT(slice_offset), stale_en);
+ if (ret)
+ return ret;
+
+ stale_cap_en = config->stale_cap_en << slice_offset;
+ ret = regmap_update_bits(drv_data->bcast_regmap,
+ LLCC_V6_TRP_ALGO_CFG2 + reg_offset,
+ BIT(slice_offset), stale_cap_en);
+ if (ret)
+ return ret;
+
+ mru_uncap_en = config->mru_uncap_en << slice_offset;
+ ret = regmap_update_bits(drv_data->bcast_regmap,
+ LLCC_V6_TRP_ALGO_CFG3 + reg_offset,
+ BIT(slice_offset), mru_uncap_en);
+ if (ret)
+ return ret;
+
+ mru_rollover = config->mru_rollover << slice_offset;
+ ret = regmap_update_bits(drv_data->bcast_regmap,
+ LLCC_V6_TRP_ALGO_CFG4 + reg_offset,
+ BIT(slice_offset), mru_rollover);
+ if (ret)
+ return ret;
+
+ alloc_oneway_en = config->alloc_oneway_en << slice_offset;
+ ret = regmap_update_bits(drv_data->bcast_regmap,
+ LLCC_V6_TRP_ALGO_CFG5 + reg_offset,
+ BIT(slice_offset), alloc_oneway_en);
+ if (ret)
+ return ret;
+
+ ovcap_en = config->ovcap_en << slice_offset;
+ ret = regmap_update_bits(drv_data->bcast_regmap,
+ LLCC_V6_TRP_ALGO_CFG6 + reg_offset,
+ BIT(slice_offset), ovcap_en);
+ if (ret)
+ return ret;
+
+ ovcap_prio = config->ovcap_prio << slice_offset;
+ ret = regmap_update_bits(drv_data->bcast_regmap,
+ LLCC_V6_TRP_ALGO_CFG7 + reg_offset,
+ BIT(slice_offset), ovcap_prio);
+ if (ret)
+ return ret;
+
+ vict_prio = config->vict_prio << slice_offset;
+ ret = regmap_update_bits(drv_data->bcast_regmap,
+ LLCC_V6_TRP_ALGO_CFG8 + reg_offset,
+ BIT(slice_offset), vict_prio);
+ if (ret)
+ return ret;
+
+ if (config->activate_on_init) {
+ desc = llcc_slice_getd(config->usecase_id);
+ if (PTR_ERR_OR_ZERO(desc))
+ return -EINVAL;
+
+ ret = llcc_slice_activate(desc);
+ }
+
+ return ret;
+}
+
static int qcom_llcc_cfg_program(struct platform_device *pdev,
const struct qcom_llcc_config *cfg)
{
@@ -3880,10 +4076,18 @@ static int qcom_llcc_cfg_program(struct platform_device *pdev,
sz = drv_data->cfg_size;
llcc_table = drv_data->cfg;
- for (i = 0; i < sz; i++) {
- ret = _qcom_llcc_cfg_program(&llcc_table[i], cfg);
- if (ret)
- return ret;
+ if (drv_data->version >= LLCC_VERSION_6_0_0_0) {
+ for (i = 0; i < sz; i++) {
+ ret = _qcom_llcc_cfg_program_v6(&llcc_table[i], cfg);
+ if (ret)
+ return ret;
+ }
+ } else {
+ for (i = 0; i < sz; i++) {
+ ret = _qcom_llcc_cfg_program(&llcc_table[i], cfg);
+ if (ret)
+ return ret;
+ }
}
return ret;
diff --git a/include/linux/soc/qcom/llcc-qcom.h b/include/linux/soc/qcom/llcc-qcom.h
index 8e5d78fb4847a232ab17a66c2775552dcb287752..7a69210a250c4646b7fd6cf400995e35d3f00493 100644
--- a/include/linux/soc/qcom/llcc-qcom.h
+++ b/include/linux/soc/qcom/llcc-qcom.h
@@ -24,6 +24,7 @@
#define LLCC_CMPTDMA 15
#define LLCC_DISP 16
#define LLCC_VIDFW 17
+#define LLCC_CAMFW 18
#define LLCC_MDMHPFX 20
#define LLCC_MDMPNG 21
#define LLCC_AUDHW 22
@@ -67,6 +68,13 @@
#define LLCC_EVCS_LEFT 67
#define LLCC_EVCS_RIGHT 68
#define LLCC_SPAD 69
+#define LLCC_VIDDEC 70
+#define LLCC_CAMOFE 71
+#define LLCC_CAMRTIP 72
+#define LLCC_CAMSRTIP 73
+#define LLCC_CAMRTRF 74
+#define LLCC_CAMSRTRF 75
+#define LLCC_CPUSSMPAM 89
/**
* struct llcc_slice_desc - Cache slice descriptor
--
2.46.1On 13.01.2025 10:26 PM, Melody Olvera wrote:
> Add support for LLCC V6. V6 adds several additional usecase IDs,
> rearrages several registers and offsets, and supports slice IDs
> over 31, so add a new function for programming LLCC V6.
>
> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
> ---
> drivers/soc/qcom/llcc-qcom.c | 212 ++++++++++++++++++++++++++++++++++++-
> include/linux/soc/qcom/llcc-qcom.h | 8 ++
> 2 files changed, 216 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c
> index 56823b6a2facc4345265e29b60da24a391e3707d..4379b5baa011aa850a2b65ec20b32519d9331be4 100644
> --- a/drivers/soc/qcom/llcc-qcom.c
> +++ b/drivers/soc/qcom/llcc-qcom.c
> @@ -35,6 +35,9 @@
> #define ATTR0_RES_WAYS_MASK GENMASK(15, 0)
> #define ATTR0_BONUS_WAYS_MASK GENMASK(31, 16)
> #define ATTR0_BONUS_WAYS_SHIFT 16
> +#define ATTR2_PROBE_TARGET_WAYS_SHIFT 4
> +#define ATTR2_FIXED_SIZE_SHIFT 8
> +#define ATTR2_PRIORITY_SHIFT 12
I'd be a great fan of defining these as fields with GENMASK, which you
would later fill with FIELD_PREP, so as to avoid potential leakage into
neighbouring bitfields
> #define LLCC_STATUS_READ_DELAY 100
>
> #define CACHE_LINE_SIZE_SHIFT 6
> @@ -49,6 +52,10 @@
> #define LLCC_TRP_ATTR0_CFGn(n) (0x21000 + SZ_8 * n)
> #define LLCC_TRP_ATTR1_CFGn(n) (0x21004 + SZ_8 * n)
> #define LLCC_TRP_ATTR2_CFGn(n) (0x21100 + SZ_4 * n)
> +#define LLCC_V6_TRP_ATTR0_CFGn(n) (0x41000 + SZ_64 * n)
> +#define LLCC_V6_TRP_ATTR1_CFGn(n) (0x41008 + SZ_64 * n)
> +#define LLCC_V6_TRP_ATTR2_CFGn(n) (0x41010 + SZ_64 * n)
> +#define LLCC_V6_TRP_ATTR3_CFGn(n) (0x41014 + SZ_64 * n)
>
> #define LLCC_TRP_SCID_DIS_CAP_ALLOC 0x21f00
> #define LLCC_TRP_PCB_ACT 0x21f04
> @@ -62,10 +69,22 @@
> #define LLCC_TRP_ALGO_CFG7 0x21f28
> #define LLCC_TRP_WRSC_CACHEABLE_EN 0x21f2c
> #define LLCC_TRP_ALGO_CFG8 0x21f30
> +#define LLCC_V6_TRP_SCID_DIS_CAP_ALLOC 0x42000
> +#define LLCC_V6_TRP_ALGO_CFG1 0x42008
> +#define LLCC_V6_TRP_ALGO_CFG2 0x42010
> +#define LLCC_V6_TRP_ALGO_CFG3 0x42018
> +#define LLCC_V6_TRP_ALGO_CFG4 0x42020
> +#define LLCC_V6_TRP_ALGO_CFG5 0x42028
> +#define LLCC_V6_TRP_ALGO_CFG6 0x42030
> +#define LLCC_V6_TRP_ALGO_CFG7 0x42038
> +#define LLCC_V6_TRP_ALGO_CFG8 0x42040
> +#define LLCC_V6_TRP_WRSC_EN 0x42080
> +#define LLCC_V6_TRP_WRSC_CACHEABLE_EN 0x42088
>
> #define LLCC_VERSION_2_0_0_0 0x02000000
> #define LLCC_VERSION_2_1_0_0 0x02010000
> #define LLCC_VERSION_4_1_0_0 0x04010000
> +#define LLCC_VERSION_6_0_0_0 0X06000000
>
> /**
> * struct llcc_slice_config - Data associated with the llcc slice
> @@ -3161,6 +3180,33 @@ static const struct llcc_edac_reg_offset llcc_v2_1_edac_reg_offset = {
> .drp_ecc_db_err_syn0 = 0x52120,
> };
>
> +static const struct llcc_edac_reg_offset llcc_v6_edac_reg_offset = {
> + .trp_ecc_error_status0 = 0x47448,
> + .trp_ecc_error_status1 = 0x47450,
> + .trp_ecc_sb_err_syn0 = 0x47490,
> + .trp_ecc_db_err_syn0 = 0x474d0,
> + .trp_ecc_error_cntr_clear = 0x47444,
> + .trp_interrupt_0_status = 0x47600,
> + .trp_interrupt_0_clear = 0x47604,
> + .trp_interrupt_0_enable = 0x47608,
> +
> + /* LLCC Common registers */
> + .cmn_status0 = 0x6400c,
> + .cmn_interrupt_0_enable = 0x6401c,
> + .cmn_interrupt_2_enable = 0x6403c,
> +
> + /* LLCC DRP registers */
> + .drp_ecc_error_cfg = 0x80000,
> + .drp_ecc_error_cntr_clear = 0x80004,
> + .drp_interrupt_status = 0x80020,
> + .drp_interrupt_clear = 0x80028,
> + .drp_interrupt_enable = 0x8002c,
> + .drp_ecc_error_status0 = 0x820f4,
> + .drp_ecc_error_status1 = 0x820f8,
> + .drp_ecc_sb_err_syn0 = 0x820fc,
> + .drp_ecc_db_err_syn0 = 0x82120,
> +};
> +
> /* LLCC register offset starting from v1.0.0 */
> static const u32 llcc_v1_reg_offset[] = {
> [LLCC_COMMON_HW_INFO] = 0x00030000,
> @@ -3173,6 +3219,13 @@ static const u32 llcc_v2_1_reg_offset[] = {
> [LLCC_COMMON_STATUS0] = 0x0003400c,
> };
>
> +/* LLCC register offset starting from v6.0.0 */
> +static const u32 llcc_v6_reg_offset[] = {
It's sort of weird to have some registers be version-define with a common
name and keep others with a version-in-the-macro-name
> + [LLCC_COMMON_HW_INFO] = 0x00064000,
> + [LLCC_COMMON_STATUS0] = 0x0006400c,
> +
Stray newline
> +};
> +
> static const struct qcom_llcc_config qcs615_cfg[] = {
> {
> .sct_data = qcs615_data,
> @@ -3869,6 +3922,149 @@ static int _qcom_llcc_cfg_program(const struct llcc_slice_config *config,
> return ret;
> }
>
> +static int _qcom_llcc_cfg_program_v6(const struct llcc_slice_config *config,
> + const struct qcom_llcc_config *cfg)
> +{
> + int ret;
> + u32 attr0_cfg, attr1_cfg, attr2_cfg, attr3_cfg;
> + u32 attr0_val, attr1_val, attr2_val, attr3_val;
> + u32 disable_cap_alloc, wren, wr_cache_en;
> + u32 stale_en, stale_cap_en, mru_uncap_en, mru_rollover;
> + u32 alloc_oneway_en, ovcap_en, ovcap_prio, vict_prio;
> + u32 slice_offset, reg_offset;
> + struct llcc_slice_desc *desc;
> + const struct llcc_slice_config *slice_cfg;
> + u32 sz = 0;
Reverse-Christmas-tree, please
> +
> + slice_cfg = cfg->sct_data;
This one it would make sense to initialize at declaration time
> + sz = cfg->size;
This one seems unused?
> +
> + attr0_cfg = LLCC_V6_TRP_ATTR0_CFGn(config->slice_id);
> + attr1_cfg = LLCC_V6_TRP_ATTR1_CFGn(config->slice_id);
> + attr2_cfg = LLCC_V6_TRP_ATTR2_CFGn(config->slice_id);
> + attr3_cfg = LLCC_V6_TRP_ATTR3_CFGn(config->slice_id);
> +
> + attr0_val = config->res_ways;
> + attr1_val = config->bonus_ways;
> + attr2_val = config->cache_mode;
> + attr2_val |= config->probe_target_ways << ATTR2_PROBE_TARGET_WAYS_SHIFT;
> + attr2_val |= config->fixed_size << ATTR2_FIXED_SIZE_SHIFT;
> + attr2_val |= config->priority << ATTR2_PRIORITY_SHIFT;
> +
> + attr3_val = MAX_CAP_TO_BYTES(config->max_cap);
> + attr3_val /= drv_data->num_banks;
> + attr3_val >>= CACHE_LINE_SIZE_SHIFT;
> +
> + ret = regmap_write(drv_data->bcast_regmap, attr0_cfg, attr0_val);
> + if (ret)
> + return ret;
> +
> + ret = regmap_write(drv_data->bcast_regmap, attr1_cfg, attr1_val);
> + if (ret)
> + return ret;
> +
> + ret = regmap_write(drv_data->bcast_regmap, attr2_cfg, attr2_val);
> + if (ret)
> + return ret;
> +
> + ret = regmap_write(drv_data->bcast_regmap, attr3_cfg, attr3_val);
> + if (ret)
> + return ret;
> +
> + slice_offset = config->slice_id % 32;
> + reg_offset = (config->slice_id / 32) * 4;
> +
> + if (!cfg->skip_llcc_cfg) {
Do we have about this case on any v6 platform?
> + disable_cap_alloc = config->dis_cap_alloc << slice_offset;
> + ret = regmap_write(drv_data->bcast_regmap,
> + LLCC_V6_TRP_SCID_DIS_CAP_ALLOC + reg_offset,
> + disable_cap_alloc);
> +
> + if (ret)
> + return ret;
> + }
> +
> + wren = config->write_scid_en << slice_offset;
> + ret = regmap_update_bits(drv_data->bcast_regmap,
> + LLCC_V6_TRP_WRSC_EN + reg_offset,
> + BIT(slice_offset), wren);
> + if (ret)
> + return ret;
> +
> + wr_cache_en = config->write_scid_cacheable_en << slice_offset;
> + ret = regmap_update_bits(drv_data->bcast_regmap,
> + LLCC_V6_TRP_WRSC_CACHEABLE_EN + reg_offset,
> + BIT(slice_offset), wr_cache_en);
> + if (ret)
> + return ret;
So the initial ATTRn configs are different for v6, but this part and later
are identical, bar the register offset difference. Let's try to abstract
that through cfg->reg_offset
> + stale_en = config->stale_en << slice_offset;
> + ret = regmap_update_bits(drv_data->bcast_regmap,
> + LLCC_V6_TRP_ALGO_CFG1 + reg_offset,
> + BIT(slice_offset), stale_en);
Updating these calls to use bitfields instead of opencoded shifting would
be a welcome addition as well, but perhaps that could be stuck at the end
of the series as a general/housekeeping improvement
Konrad
On 1/28/2025 6:01 AM, Konrad Dybcio wrote:
> On 13.01.2025 10:26 PM, Melody Olvera wrote:
>> Add support for LLCC V6. V6 adds several additional usecase IDs,
>> rearrages several registers and offsets, and supports slice IDs
>> over 31, so add a new function for programming LLCC V6.
>>
>> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
>> ---
>> drivers/soc/qcom/llcc-qcom.c | 212 ++++++++++++++++++++++++++++++++++++-
>> include/linux/soc/qcom/llcc-qcom.h | 8 ++
>> 2 files changed, 216 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c
>> index 56823b6a2facc4345265e29b60da24a391e3707d..4379b5baa011aa850a2b65ec20b32519d9331be4 100644
>> --- a/drivers/soc/qcom/llcc-qcom.c
>> +++ b/drivers/soc/qcom/llcc-qcom.c
>> @@ -35,6 +35,9 @@
>> #define ATTR0_RES_WAYS_MASK GENMASK(15, 0)
>> #define ATTR0_BONUS_WAYS_MASK GENMASK(31, 16)
>> #define ATTR0_BONUS_WAYS_SHIFT 16
>> +#define ATTR2_PROBE_TARGET_WAYS_SHIFT 4
>> +#define ATTR2_FIXED_SIZE_SHIFT 8
>> +#define ATTR2_PRIORITY_SHIFT 12
> I'd be a great fan of defining these as fields with GENMASK, which you
> would later fill with FIELD_PREP, so as to avoid potential leakage into
> neighbouring bitfields
Ack.
>
>> #define LLCC_STATUS_READ_DELAY 100
>>
>> #define CACHE_LINE_SIZE_SHIFT 6
>> @@ -49,6 +52,10 @@
>> #define LLCC_TRP_ATTR0_CFGn(n) (0x21000 + SZ_8 * n)
>> #define LLCC_TRP_ATTR1_CFGn(n) (0x21004 + SZ_8 * n)
>> #define LLCC_TRP_ATTR2_CFGn(n) (0x21100 + SZ_4 * n)
>> +#define LLCC_V6_TRP_ATTR0_CFGn(n) (0x41000 + SZ_64 * n)
>> +#define LLCC_V6_TRP_ATTR1_CFGn(n) (0x41008 + SZ_64 * n)
>> +#define LLCC_V6_TRP_ATTR2_CFGn(n) (0x41010 + SZ_64 * n)
>> +#define LLCC_V6_TRP_ATTR3_CFGn(n) (0x41014 + SZ_64 * n)
>>
>> #define LLCC_TRP_SCID_DIS_CAP_ALLOC 0x21f00
>> #define LLCC_TRP_PCB_ACT 0x21f04
>> @@ -62,10 +69,22 @@
>> #define LLCC_TRP_ALGO_CFG7 0x21f28
>> #define LLCC_TRP_WRSC_CACHEABLE_EN 0x21f2c
>> #define LLCC_TRP_ALGO_CFG8 0x21f30
>> +#define LLCC_V6_TRP_SCID_DIS_CAP_ALLOC 0x42000
>> +#define LLCC_V6_TRP_ALGO_CFG1 0x42008
>> +#define LLCC_V6_TRP_ALGO_CFG2 0x42010
>> +#define LLCC_V6_TRP_ALGO_CFG3 0x42018
>> +#define LLCC_V6_TRP_ALGO_CFG4 0x42020
>> +#define LLCC_V6_TRP_ALGO_CFG5 0x42028
>> +#define LLCC_V6_TRP_ALGO_CFG6 0x42030
>> +#define LLCC_V6_TRP_ALGO_CFG7 0x42038
>> +#define LLCC_V6_TRP_ALGO_CFG8 0x42040
>> +#define LLCC_V6_TRP_WRSC_EN 0x42080
>> +#define LLCC_V6_TRP_WRSC_CACHEABLE_EN 0x42088
>>
>> #define LLCC_VERSION_2_0_0_0 0x02000000
>> #define LLCC_VERSION_2_1_0_0 0x02010000
>> #define LLCC_VERSION_4_1_0_0 0x04010000
>> +#define LLCC_VERSION_6_0_0_0 0X06000000
>>
>> /**
>> * struct llcc_slice_config - Data associated with the llcc slice
>> @@ -3161,6 +3180,33 @@ static const struct llcc_edac_reg_offset llcc_v2_1_edac_reg_offset = {
>> .drp_ecc_db_err_syn0 = 0x52120,
>> };
>>
>> +static const struct llcc_edac_reg_offset llcc_v6_edac_reg_offset = {
>> + .trp_ecc_error_status0 = 0x47448,
>> + .trp_ecc_error_status1 = 0x47450,
>> + .trp_ecc_sb_err_syn0 = 0x47490,
>> + .trp_ecc_db_err_syn0 = 0x474d0,
>> + .trp_ecc_error_cntr_clear = 0x47444,
>> + .trp_interrupt_0_status = 0x47600,
>> + .trp_interrupt_0_clear = 0x47604,
>> + .trp_interrupt_0_enable = 0x47608,
>> +
>> + /* LLCC Common registers */
>> + .cmn_status0 = 0x6400c,
>> + .cmn_interrupt_0_enable = 0x6401c,
>> + .cmn_interrupt_2_enable = 0x6403c,
>> +
>> + /* LLCC DRP registers */
>> + .drp_ecc_error_cfg = 0x80000,
>> + .drp_ecc_error_cntr_clear = 0x80004,
>> + .drp_interrupt_status = 0x80020,
>> + .drp_interrupt_clear = 0x80028,
>> + .drp_interrupt_enable = 0x8002c,
>> + .drp_ecc_error_status0 = 0x820f4,
>> + .drp_ecc_error_status1 = 0x820f8,
>> + .drp_ecc_sb_err_syn0 = 0x820fc,
>> + .drp_ecc_db_err_syn0 = 0x82120,
>> +};
>> +
>> /* LLCC register offset starting from v1.0.0 */
>> static const u32 llcc_v1_reg_offset[] = {
>> [LLCC_COMMON_HW_INFO] = 0x00030000,
>> @@ -3173,6 +3219,13 @@ static const u32 llcc_v2_1_reg_offset[] = {
>> [LLCC_COMMON_STATUS0] = 0x0003400c,
>> };
>>
>> +/* LLCC register offset starting from v6.0.0 */
>> +static const u32 llcc_v6_reg_offset[] = {
> It's sort of weird to have some registers be version-define with a common
> name and keep others with a version-in-the-macro-name
I agree. There exists a version of this change which moves the offset
macros to these structs if that's preferred; I wanted some feedback
on what folks would prefer here.
>
>> + [LLCC_COMMON_HW_INFO] = 0x00064000,
>> + [LLCC_COMMON_STATUS0] = 0x0006400c,
>> +
> Stray newline
Ack.
>
>> +};
>> +
>> static const struct qcom_llcc_config qcs615_cfg[] = {
>> {
>> .sct_data = qcs615_data,
>> @@ -3869,6 +3922,149 @@ static int _qcom_llcc_cfg_program(const struct llcc_slice_config *config,
>> return ret;
>> }
>>
>> +static int _qcom_llcc_cfg_program_v6(const struct llcc_slice_config *config,
>> + const struct qcom_llcc_config *cfg)
>> +{
>> + int ret;
>> + u32 attr0_cfg, attr1_cfg, attr2_cfg, attr3_cfg;
>> + u32 attr0_val, attr1_val, attr2_val, attr3_val;
>> + u32 disable_cap_alloc, wren, wr_cache_en;
>> + u32 stale_en, stale_cap_en, mru_uncap_en, mru_rollover;
>> + u32 alloc_oneway_en, ovcap_en, ovcap_prio, vict_prio;
>> + u32 slice_offset, reg_offset;
>> + struct llcc_slice_desc *desc;
>> + const struct llcc_slice_config *slice_cfg;
>> + u32 sz = 0;
> Reverse-Christmas-tree, please
Ack.
>
>> +
>> + slice_cfg = cfg->sct_data;
> This one it would make sense to initialize at declaration time
Sure thing.
>
>> + sz = cfg->size;
> This one seems unused?
Lemme double-check; will remove if so.
>
>> +
>> + attr0_cfg = LLCC_V6_TRP_ATTR0_CFGn(config->slice_id);
>> + attr1_cfg = LLCC_V6_TRP_ATTR1_CFGn(config->slice_id);
>> + attr2_cfg = LLCC_V6_TRP_ATTR2_CFGn(config->slice_id);
>> + attr3_cfg = LLCC_V6_TRP_ATTR3_CFGn(config->slice_id);
>> +
>> + attr0_val = config->res_ways;
>> + attr1_val = config->bonus_ways;
>> + attr2_val = config->cache_mode;
>> + attr2_val |= config->probe_target_ways << ATTR2_PROBE_TARGET_WAYS_SHIFT;
>> + attr2_val |= config->fixed_size << ATTR2_FIXED_SIZE_SHIFT;
>> + attr2_val |= config->priority << ATTR2_PRIORITY_SHIFT;
>> +
>> + attr3_val = MAX_CAP_TO_BYTES(config->max_cap);
>> + attr3_val /= drv_data->num_banks;
>> + attr3_val >>= CACHE_LINE_SIZE_SHIFT;
>> +
>> + ret = regmap_write(drv_data->bcast_regmap, attr0_cfg, attr0_val);
>> + if (ret)
>> + return ret;
>> +
>> + ret = regmap_write(drv_data->bcast_regmap, attr1_cfg, attr1_val);
>> + if (ret)
>> + return ret;
>> +
>> + ret = regmap_write(drv_data->bcast_regmap, attr2_cfg, attr2_val);
>> + if (ret)
>> + return ret;
>> +
>> + ret = regmap_write(drv_data->bcast_regmap, attr3_cfg, attr3_val);
>> + if (ret)
>> + return ret;
>> +
>> + slice_offset = config->slice_id % 32;
>> + reg_offset = (config->slice_id / 32) * 4;
>> +
>> + if (!cfg->skip_llcc_cfg) {
> Do we have about this case on any v6 platform?
AFAICT no; I can remove it.
>
>> + disable_cap_alloc = config->dis_cap_alloc << slice_offset;
>> + ret = regmap_write(drv_data->bcast_regmap,
>> + LLCC_V6_TRP_SCID_DIS_CAP_ALLOC + reg_offset,
>> + disable_cap_alloc);
>> +
>> + if (ret)
>> + return ret;
>> + }
>> +
>> + wren = config->write_scid_en << slice_offset;
>> + ret = regmap_update_bits(drv_data->bcast_regmap,
>> + LLCC_V6_TRP_WRSC_EN + reg_offset,
>> + BIT(slice_offset), wren);
>> + if (ret)
>> + return ret;
>> +
>> + wr_cache_en = config->write_scid_cacheable_en << slice_offset;
>> + ret = regmap_update_bits(drv_data->bcast_regmap,
>> + LLCC_V6_TRP_WRSC_CACHEABLE_EN + reg_offset,
>> + BIT(slice_offset), wr_cache_en);
>> + if (ret)
>> + return ret;
> So the initial ATTRn configs are different for v6, but this part and later
> are identical, bar the register offset difference. Let's try to abstract
> that through cfg->reg_offset
Agreed.
>
>> + stale_en = config->stale_en << slice_offset;
>> + ret = regmap_update_bits(drv_data->bcast_regmap,
>> + LLCC_V6_TRP_ALGO_CFG1 + reg_offset,
>> + BIT(slice_offset), stale_en);
> Updating these calls to use bitfields instead of opencoded shifting would
> be a welcome addition as well, but perhaps that could be stuck at the end
> of the series as a general/housekeeping improvement
Ok; will do.
Thanks,
Melody
Hi Melody,
kernel test robot noticed the following build warnings:
[auto build test WARNING on 37136bf5c3a6f6b686d74f41837a6406bec6b7bc]
url: https://github.com/intel-lab-lkp/linux/commits/Melody-Olvera/dt-bindings-cache-qcom-llcc-Document-SM8750-LLCC-block/20250114-053146
base: 37136bf5c3a6f6b686d74f41837a6406bec6b7bc
patch link: https://lore.kernel.org/r/20250113-sm8750_llcc_master-v1-2-5389b92e2d7a%40quicinc.com
patch subject: [PATCH 2/4] soc: qcom: llcc-qcom: Add support for LLCC V6
config: mips-randconfig-r073-20250117 (https://download.01.org/0day-ci/archive/20250118/202501180248.1JzWcFb9-lkp@intel.com/config)
compiler: mips-linux-gcc (GCC) 14.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250118/202501180248.1JzWcFb9-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202501180248.1JzWcFb9-lkp@intel.com/
All warnings (new ones prefixed by >>):
drivers/soc/qcom/llcc-qcom.c: In function '_qcom_llcc_cfg_program_v6':
>> drivers/soc/qcom/llcc-qcom.c:3937:13: warning: variable 'sz' set but not used [-Wunused-but-set-variable]
3937 | u32 sz = 0;
| ^~
>> drivers/soc/qcom/llcc-qcom.c:3936:41: warning: variable 'slice_cfg' set but not used [-Wunused-but-set-variable]
3936 | const struct llcc_slice_config *slice_cfg;
| ^~~~~~~~~
drivers/soc/qcom/llcc-qcom.c: At top level:
drivers/soc/qcom/llcc-qcom.c:3223:18: warning: 'llcc_v6_reg_offset' defined but not used [-Wunused-const-variable=]
3223 | static const u32 llcc_v6_reg_offset[] = {
| ^~~~~~~~~~~~~~~~~~
drivers/soc/qcom/llcc-qcom.c:3183:42: warning: 'llcc_v6_edac_reg_offset' defined but not used [-Wunused-const-variable=]
3183 | static const struct llcc_edac_reg_offset llcc_v6_edac_reg_offset = {
| ^~~~~~~~~~~~~~~~~~~~~~~
vim +/sz +3937 drivers/soc/qcom/llcc-qcom.c
3924
3925 static int _qcom_llcc_cfg_program_v6(const struct llcc_slice_config *config,
3926 const struct qcom_llcc_config *cfg)
3927 {
3928 int ret;
3929 u32 attr0_cfg, attr1_cfg, attr2_cfg, attr3_cfg;
3930 u32 attr0_val, attr1_val, attr2_val, attr3_val;
3931 u32 disable_cap_alloc, wren, wr_cache_en;
3932 u32 stale_en, stale_cap_en, mru_uncap_en, mru_rollover;
3933 u32 alloc_oneway_en, ovcap_en, ovcap_prio, vict_prio;
3934 u32 slice_offset, reg_offset;
3935 struct llcc_slice_desc *desc;
> 3936 const struct llcc_slice_config *slice_cfg;
> 3937 u32 sz = 0;
3938
3939 slice_cfg = cfg->sct_data;
3940 sz = cfg->size;
3941
3942 attr0_cfg = LLCC_V6_TRP_ATTR0_CFGn(config->slice_id);
3943 attr1_cfg = LLCC_V6_TRP_ATTR1_CFGn(config->slice_id);
3944 attr2_cfg = LLCC_V6_TRP_ATTR2_CFGn(config->slice_id);
3945 attr3_cfg = LLCC_V6_TRP_ATTR3_CFGn(config->slice_id);
3946
3947 attr0_val = config->res_ways;
3948 attr1_val = config->bonus_ways;
3949 attr2_val = config->cache_mode;
3950 attr2_val |= config->probe_target_ways << ATTR2_PROBE_TARGET_WAYS_SHIFT;
3951 attr2_val |= config->fixed_size << ATTR2_FIXED_SIZE_SHIFT;
3952 attr2_val |= config->priority << ATTR2_PRIORITY_SHIFT;
3953
3954 attr3_val = MAX_CAP_TO_BYTES(config->max_cap);
3955 attr3_val /= drv_data->num_banks;
3956 attr3_val >>= CACHE_LINE_SIZE_SHIFT;
3957
3958 ret = regmap_write(drv_data->bcast_regmap, attr0_cfg, attr0_val);
3959 if (ret)
3960 return ret;
3961
3962 ret = regmap_write(drv_data->bcast_regmap, attr1_cfg, attr1_val);
3963 if (ret)
3964 return ret;
3965
3966 ret = regmap_write(drv_data->bcast_regmap, attr2_cfg, attr2_val);
3967 if (ret)
3968 return ret;
3969
3970 ret = regmap_write(drv_data->bcast_regmap, attr3_cfg, attr3_val);
3971 if (ret)
3972 return ret;
3973
3974 slice_offset = config->slice_id % 32;
3975 reg_offset = (config->slice_id / 32) * 4;
3976
3977 if (!cfg->skip_llcc_cfg) {
3978 disable_cap_alloc = config->dis_cap_alloc << slice_offset;
3979 ret = regmap_write(drv_data->bcast_regmap,
3980 LLCC_V6_TRP_SCID_DIS_CAP_ALLOC + reg_offset,
3981 disable_cap_alloc);
3982
3983 if (ret)
3984 return ret;
3985 }
3986
3987 wren = config->write_scid_en << slice_offset;
3988 ret = regmap_update_bits(drv_data->bcast_regmap,
3989 LLCC_V6_TRP_WRSC_EN + reg_offset,
3990 BIT(slice_offset), wren);
3991 if (ret)
3992 return ret;
3993
3994 wr_cache_en = config->write_scid_cacheable_en << slice_offset;
3995 ret = regmap_update_bits(drv_data->bcast_regmap,
3996 LLCC_V6_TRP_WRSC_CACHEABLE_EN + reg_offset,
3997 BIT(slice_offset), wr_cache_en);
3998 if (ret)
3999 return ret;
4000
4001 stale_en = config->stale_en << slice_offset;
4002 ret = regmap_update_bits(drv_data->bcast_regmap,
4003 LLCC_V6_TRP_ALGO_CFG1 + reg_offset,
4004 BIT(slice_offset), stale_en);
4005 if (ret)
4006 return ret;
4007
4008 stale_cap_en = config->stale_cap_en << slice_offset;
4009 ret = regmap_update_bits(drv_data->bcast_regmap,
4010 LLCC_V6_TRP_ALGO_CFG2 + reg_offset,
4011 BIT(slice_offset), stale_cap_en);
4012 if (ret)
4013 return ret;
4014
4015 mru_uncap_en = config->mru_uncap_en << slice_offset;
4016 ret = regmap_update_bits(drv_data->bcast_regmap,
4017 LLCC_V6_TRP_ALGO_CFG3 + reg_offset,
4018 BIT(slice_offset), mru_uncap_en);
4019 if (ret)
4020 return ret;
4021
4022 mru_rollover = config->mru_rollover << slice_offset;
4023 ret = regmap_update_bits(drv_data->bcast_regmap,
4024 LLCC_V6_TRP_ALGO_CFG4 + reg_offset,
4025 BIT(slice_offset), mru_rollover);
4026 if (ret)
4027 return ret;
4028
4029 alloc_oneway_en = config->alloc_oneway_en << slice_offset;
4030 ret = regmap_update_bits(drv_data->bcast_regmap,
4031 LLCC_V6_TRP_ALGO_CFG5 + reg_offset,
4032 BIT(slice_offset), alloc_oneway_en);
4033 if (ret)
4034 return ret;
4035
4036 ovcap_en = config->ovcap_en << slice_offset;
4037 ret = regmap_update_bits(drv_data->bcast_regmap,
4038 LLCC_V6_TRP_ALGO_CFG6 + reg_offset,
4039 BIT(slice_offset), ovcap_en);
4040 if (ret)
4041 return ret;
4042
4043 ovcap_prio = config->ovcap_prio << slice_offset;
4044 ret = regmap_update_bits(drv_data->bcast_regmap,
4045 LLCC_V6_TRP_ALGO_CFG7 + reg_offset,
4046 BIT(slice_offset), ovcap_prio);
4047 if (ret)
4048 return ret;
4049
4050 vict_prio = config->vict_prio << slice_offset;
4051 ret = regmap_update_bits(drv_data->bcast_regmap,
4052 LLCC_V6_TRP_ALGO_CFG8 + reg_offset,
4053 BIT(slice_offset), vict_prio);
4054 if (ret)
4055 return ret;
4056
4057 if (config->activate_on_init) {
4058 desc = llcc_slice_getd(config->usecase_id);
4059 if (PTR_ERR_OR_ZERO(desc))
4060 return -EINVAL;
4061
4062 ret = llcc_slice_activate(desc);
4063 }
4064
4065 return ret;
4066 }
4067
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
On Mon, Jan 13, 2025 at 01:26:41PM -0800, Melody Olvera wrote: > Add support for LLCC V6. V6 adds several additional usecase IDs, > rearrages several registers and offsets, and supports slice IDs > over 31, so add a new function for programming LLCC V6. > > Signed-off-by: Melody Olvera <quic_molvera@quicinc.com> > --- > drivers/soc/qcom/llcc-qcom.c | 212 ++++++++++++++++++++++++++++++++++++- > include/linux/soc/qcom/llcc-qcom.h | 8 ++ > 2 files changed, 216 insertions(+), 4 deletions(-) > > diff --git a/include/linux/soc/qcom/llcc-qcom.h b/include/linux/soc/qcom/llcc-qcom.h > index 8e5d78fb4847a232ab17a66c2775552dcb287752..7a69210a250c4646b7fd6cf400995e35d3f00493 100644 > --- a/include/linux/soc/qcom/llcc-qcom.h > +++ b/include/linux/soc/qcom/llcc-qcom.h These are not relevant to v6 support, move them to the platform-support patch. LGTM otherwise. > @@ -24,6 +24,7 @@ > #define LLCC_CMPTDMA 15 > #define LLCC_DISP 16 > #define LLCC_VIDFW 17 > +#define LLCC_CAMFW 18 > #define LLCC_MDMHPFX 20 > #define LLCC_MDMPNG 21 > #define LLCC_AUDHW 22 > @@ -67,6 +68,13 @@ > #define LLCC_EVCS_LEFT 67 > #define LLCC_EVCS_RIGHT 68 > #define LLCC_SPAD 69 > +#define LLCC_VIDDEC 70 > +#define LLCC_CAMOFE 71 > +#define LLCC_CAMRTIP 72 > +#define LLCC_CAMSRTIP 73 > +#define LLCC_CAMRTRF 74 > +#define LLCC_CAMSRTRF 75 > +#define LLCC_CPUSSMPAM 89 > > /** > * struct llcc_slice_desc - Cache slice descriptor > > -- > 2.46.1 > -- With best wishes Dmitry
On 1/14/2025 2:58 AM, Dmitry Baryshkov wrote: > On Mon, Jan 13, 2025 at 01:26:41PM -0800, Melody Olvera wrote: >> Add support for LLCC V6. V6 adds several additional usecase IDs, >> rearrages several registers and offsets, and supports slice IDs >> over 31, so add a new function for programming LLCC V6. >> >> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com> >> --- >> drivers/soc/qcom/llcc-qcom.c | 212 ++++++++++++++++++++++++++++++++++++- >> include/linux/soc/qcom/llcc-qcom.h | 8 ++ >> 2 files changed, 216 insertions(+), 4 deletions(-) >> >> diff --git a/include/linux/soc/qcom/llcc-qcom.h b/include/linux/soc/qcom/llcc-qcom.h >> index 8e5d78fb4847a232ab17a66c2775552dcb287752..7a69210a250c4646b7fd6cf400995e35d3f00493 100644 >> --- a/include/linux/soc/qcom/llcc-qcom.h >> +++ b/include/linux/soc/qcom/llcc-qcom.h > These are not relevant to v6 support, move them to the platform-support > patch. Will do. Melody > > LGTM otherwise. > >> @@ -24,6 +24,7 @@ >> #define LLCC_CMPTDMA 15 >> #define LLCC_DISP 16 >> #define LLCC_VIDFW 17 >> +#define LLCC_CAMFW 18 >> #define LLCC_MDMHPFX 20 >> #define LLCC_MDMPNG 21 >> #define LLCC_AUDHW 22 >> @@ -67,6 +68,13 @@ >> #define LLCC_EVCS_LEFT 67 >> #define LLCC_EVCS_RIGHT 68 >> #define LLCC_SPAD 69 >> +#define LLCC_VIDDEC 70 >> +#define LLCC_CAMOFE 71 >> +#define LLCC_CAMRTIP 72 >> +#define LLCC_CAMSRTIP 73 >> +#define LLCC_CAMRTRF 74 >> +#define LLCC_CAMSRTRF 75 >> +#define LLCC_CPUSSMPAM 89 >> >> /** >> * struct llcc_slice_desc - Cache slice descriptor >> >> -- >> 2.46.1 >>
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