1. Patchew
  2. linux
  3. [PATCH net-next v3 0/6] net: xilinx: axienet: Enable adaptive IRQ coalescing with DIM
  4. View patch

[PATCH net-next v3 5/6] net: xilinx: axienet: Get coalesce parameters from driver state

Sean Anderson posted 6 patches 1 year ago
There is a newer version of this series
[PATCH net-next v3 5/6] net: xilinx: axienet: Get coalesce parameters from driver state
Posted by Sean Anderson 1 year ago 
The cr variables now contain the same values as the control registers
themselves. Extract/calculate the values from the variables instead of
saving the user-specified values. This allows us to remove some
bookeeping, and also lets the user know what the actual coalesce
settings are.

Signed-off-by: Sean Anderson <sean.anderson@linux.dev>
Reviewed by: Shannon Nelson <shannon.nelson@amd.com>
---

(no changes since v2)

Changes in v2:
- New

 drivers/net/ethernet/xilinx/xilinx_axienet.h  |  8 ---
 .../net/ethernet/xilinx/xilinx_axienet_main.c | 70 +++++++++++++------
 2 files changed, 47 insertions(+), 31 deletions(-)

diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet.h b/drivers/net/ethernet/xilinx/xilinx_axienet.h
index 6b8e550c2155..45d8d80dbb1a 100644
--- a/drivers/net/ethernet/xilinx/xilinx_axienet.h
+++ b/drivers/net/ethernet/xilinx/xilinx_axienet.h
@@ -533,10 +533,6 @@ struct skbuf_dma_descriptor {
  *		  supported, the maximum frame size would be 9k. Else it is
  *		  1522 bytes (assuming support for basic VLAN)
  * @rxmem:	Stores rx memory size for jumbo frame handling.
- * @coalesce_count_rx:	Store the irq coalesce on RX side.
- * @coalesce_usec_rx:	IRQ coalesce delay for RX
- * @coalesce_count_tx:	Store the irq coalesce on TX side.
- * @coalesce_usec_tx:	IRQ coalesce delay for TX
  * @use_dmaengine: flag to check dmaengine framework usage.
  * @tx_chan:	TX DMA channel.
  * @rx_chan:	RX DMA channel.
@@ -615,10 +611,6 @@ struct axienet_local {
 	u32 max_frm_size;
 	u32 rxmem;
 
-	u32 coalesce_count_rx;
-	u32 coalesce_usec_rx;
-	u32 coalesce_count_tx;
-	u32 coalesce_usec_tx;
 	u8  use_dmaengine;
 	struct dma_chan *tx_chan;
 	struct dma_chan *rx_chan;
diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
index e00759012894..8ba42cebffb4 100644
--- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
+++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
@@ -223,6 +223,13 @@ static void axienet_dma_bd_release(struct net_device *ndev)
 			  lp->rx_bd_p);
 }
 
+static u64 axienet_dma_rate(struct axienet_local *lp)
+{
+	if (lp->axi_clk)
+		return clk_get_rate(lp->axi_clk);
+	return 125000000; /* arbitrary guess if no clock rate set */
+}
+
 /**
  * axienet_calc_cr() - Calculate control register value
  * @lp: Device private data
@@ -242,12 +249,9 @@ static u32 axienet_calc_cr(struct axienet_local *lp, u32 count, u32 usec)
 	 * the first packet. Otherwise leave at 0 to disable delay interrupt.
 	 */
 	if (count > 1) {
-		u64 clk_rate = 125000000; /* arbitrary guess if no clock rate set */
+		u64 clk_rate = axienet_dma_rate(lp);
 		u32 timer;
 
-		if (lp->axi_clk)
-			clk_rate = clk_get_rate(lp->axi_clk);
-
 		/* 1 Timeout Interval = 125 * (clock period of SG clock) */
 		timer = DIV64_U64_ROUND_CLOSEST((u64)usec * clk_rate,
 						XAXIDMA_DELAY_SCALE);
@@ -260,6 +264,23 @@ static u32 axienet_calc_cr(struct axienet_local *lp, u32 count, u32 usec)
 	return cr;
 }
 
+/**
+ * axienet_cr_params() - Extract coalesce parameters from the CR
+ * @lp: Device private data
+ * @cr: The control register to parse
+ * @count: Number of packets before an interrupt
+ * @usec: Idle time (in usec) before an interrupt
+ */
+static void axienet_coalesce_params(struct axienet_local *lp, u32 cr,
+				    u32 *count, u32 *usec)
+{
+	u64 clk_rate = axienet_dma_rate(lp);
+	u64 timer = FIELD_GET(XAXIDMA_DELAY_MASK, cr);
+
+	*count = FIELD_GET(XAXIDMA_COALESCE_MASK, cr);
+	*usec = DIV64_U64_ROUND_CLOSEST(timer * XAXIDMA_DELAY_SCALE, clk_rate);
+}
+
 /**
  * axienet_dma_start - Set up DMA registers and start DMA operation
  * @lp:		Pointer to the axienet_local structure
@@ -2104,11 +2125,21 @@ axienet_ethtools_get_coalesce(struct net_device *ndev,
 			      struct netlink_ext_ack *extack)
 {
 	struct axienet_local *lp = netdev_priv(ndev);
+	u32 cr;
 
-	ecoalesce->rx_max_coalesced_frames = lp->coalesce_count_rx;
-	ecoalesce->rx_coalesce_usecs = lp->coalesce_usec_rx;
-	ecoalesce->tx_max_coalesced_frames = lp->coalesce_count_tx;
-	ecoalesce->tx_coalesce_usecs = lp->coalesce_usec_tx;
+	spin_lock_irq(&lp->rx_cr_lock);
+	cr = lp->rx_dma_cr;
+	spin_unlock_irq(&lp->rx_cr_lock);
+	axienet_coalesce_params(lp, cr,
+				&ecoalesce->rx_max_coalesced_frames,
+				&ecoalesce->rx_coalesce_usecs);
+
+	spin_lock_irq(&lp->tx_cr_lock);
+	cr = lp->tx_dma_cr;
+	spin_unlock_irq(&lp->tx_cr_lock);
+	axienet_coalesce_params(lp, cr,
+				&ecoalesce->tx_max_coalesced_frames,
+				&ecoalesce->tx_coalesce_usecs);
 	return 0;
 }
 
@@ -2155,15 +2186,12 @@ axienet_ethtools_set_coalesce(struct net_device *ndev,
 		return -EINVAL;
 	}
 
-	lp->coalesce_count_rx = ecoalesce->rx_max_coalesced_frames;
-	lp->coalesce_usec_rx = ecoalesce->rx_coalesce_usecs;
-	lp->coalesce_count_tx = ecoalesce->tx_max_coalesced_frames;
-	lp->coalesce_usec_tx = ecoalesce->tx_coalesce_usecs;
-
-	cr = axienet_calc_cr(lp, lp->coalesce_count_rx, lp->coalesce_usec_rx);
+	cr = axienet_calc_cr(lp, ecoalesce->rx_max_coalesced_frames,
+			     ecoalesce->rx_coalesce_usecs);
 	axienet_update_coalesce_rx(lp, cr, ~XAXIDMA_CR_RUNSTOP_MASK);
 
-	cr = axienet_calc_cr(lp, lp->coalesce_count_tx, lp->coalesce_usec_tx);
+	cr = axienet_calc_cr(lp, ecoalesce->tx_max_coalesced_frames,
+			     ecoalesce->tx_coalesce_usecs);
 	axienet_update_coalesce_tx(lp, cr, ~XAXIDMA_CR_RUNSTOP_MASK);
 	return 0;
 }
@@ -2945,14 +2973,10 @@ static int axienet_probe(struct platform_device *pdev)
 
 	spin_lock_init(&lp->rx_cr_lock);
 	spin_lock_init(&lp->tx_cr_lock);
-	lp->coalesce_count_rx = XAXIDMA_DFT_RX_THRESHOLD;
-	lp->coalesce_count_tx = XAXIDMA_DFT_TX_THRESHOLD;
-	lp->coalesce_usec_rx = XAXIDMA_DFT_RX_USEC;
-	lp->coalesce_usec_tx = XAXIDMA_DFT_TX_USEC;
-	lp->rx_dma_cr = axienet_calc_cr(lp, lp->coalesce_count_rx,
-					lp->coalesce_usec_rx);
-	lp->tx_dma_cr = axienet_calc_cr(lp, lp->coalesce_count_tx,
-					lp->coalesce_usec_tx);
+	lp->rx_dma_cr = axienet_calc_cr(lp, XAXIDMA_DFT_RX_THRESHOLD,
+					XAXIDMA_DFT_RX_USEC);
+	lp->tx_dma_cr = axienet_calc_cr(lp, XAXIDMA_DFT_TX_THRESHOLD,
+					XAXIDMA_DFT_TX_USEC);
 
 	ret = axienet_mdio_setup(lp);
 	if (ret)
-- 
2.35.1.1320.gc452695387.dirty
Re: [PATCH net-next v3 5/6] net: xilinx: axienet: Get coalesce parameters from driver state
Posted by Simon Horman 1 year ago 
On Fri, Jan 10, 2025 at 02:26:15PM -0500, Sean Anderson wrote:
> The cr variables now contain the same values as the control registers
> themselves. Extract/calculate the values from the variables instead of
> saving the user-specified values. This allows us to remove some
> bookeeping, and also lets the user know what the actual coalesce
> settings are.
> 
> Signed-off-by: Sean Anderson <sean.anderson@linux.dev>
> Reviewed by: Shannon Nelson <shannon.nelson@amd.com>

Hi Sean,

Unfortunately this series does not appear to apply cleanly to net-next.
Which is our CI is currently unable to cope with :(

Please consider rebasing and reposting.

> ---
> 
> (no changes since v2)
> 
> Changes in v2:
> - New
> 
>  drivers/net/ethernet/xilinx/xilinx_axienet.h  |  8 ---
>  .../net/ethernet/xilinx/xilinx_axienet_main.c | 70 +++++++++++++------
>  2 files changed, 47 insertions(+), 31 deletions(-)
> 
> diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet.h b/drivers/net/ethernet/xilinx/xilinx_axienet.h
> index 6b8e550c2155..45d8d80dbb1a 100644
> --- a/drivers/net/ethernet/xilinx/xilinx_axienet.h
> +++ b/drivers/net/ethernet/xilinx/xilinx_axienet.h
> @@ -533,10 +533,6 @@ struct skbuf_dma_descriptor {
>   *		  supported, the maximum frame size would be 9k. Else it is
>   *		  1522 bytes (assuming support for basic VLAN)
>   * @rxmem:	Stores rx memory size for jumbo frame handling.
> - * @coalesce_count_rx:	Store the irq coalesce on RX side.
> - * @coalesce_usec_rx:	IRQ coalesce delay for RX
> - * @coalesce_count_tx:	Store the irq coalesce on TX side.
> - * @coalesce_usec_tx:	IRQ coalesce delay for TX
>   * @use_dmaengine: flag to check dmaengine framework usage.
>   * @tx_chan:	TX DMA channel.
>   * @rx_chan:	RX DMA channel.
> @@ -615,10 +611,6 @@ struct axienet_local {
>  	u32 max_frm_size;
>  	u32 rxmem;
>  
> -	u32 coalesce_count_rx;
> -	u32 coalesce_usec_rx;
> -	u32 coalesce_count_tx;
> -	u32 coalesce_usec_tx;
>  	u8  use_dmaengine;
>  	struct dma_chan *tx_chan;
>  	struct dma_chan *rx_chan;

> diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c

...

> @@ -260,6 +264,23 @@ static u32 axienet_calc_cr(struct axienet_local *lp, u32 count, u32 usec)
>  	return cr;
>  }
>  
> +/**
> + * axienet_cr_params() - Extract coalesce parameters from the CR

nit: axienet_coalesce_params

> + * @lp: Device private data
> + * @cr: The control register to parse
> + * @count: Number of packets before an interrupt
> + * @usec: Idle time (in usec) before an interrupt
> + */
> +static void axienet_coalesce_params(struct axienet_local *lp, u32 cr,
> +				    u32 *count, u32 *usec)
> +{
> +	u64 clk_rate = axienet_dma_rate(lp);
> +	u64 timer = FIELD_GET(XAXIDMA_DELAY_MASK, cr);
> +
> +	*count = FIELD_GET(XAXIDMA_COALESCE_MASK, cr);
> +	*usec = DIV64_U64_ROUND_CLOSEST(timer * XAXIDMA_DELAY_SCALE, clk_rate);
> +}
> +
>  /**
>   * axienet_dma_start - Set up DMA registers and start DMA operation
>   * @lp:		Pointer to the axienet_local structure
Re: [PATCH net-next v3 5/6] net: xilinx: axienet: Get coalesce parameters from driver state
Posted by Sean Anderson 1 year ago 
Hi Simon,

On 1/13/25 12:39, Simon Horman wrote:
> On Fri, Jan 10, 2025 at 02:26:15PM -0500, Sean Anderson wrote:
>> The cr variables now contain the same values as the control registers
>> themselves. Extract/calculate the values from the variables instead of
>> saving the user-specified values. This allows us to remove some
>> bookeeping, and also lets the user know what the actual coalesce
>> settings are.
>> 
>> Signed-off-by: Sean Anderson <sean.anderson@linux.dev>
>> Reviewed by: Shannon Nelson <shannon.nelson@amd.com>
> 
> Hi Sean,
> 
> Unfortunately this series does not appear to apply cleanly to net-next.
> Which is our CI is currently unable to cope with :(
> 
> Please consider rebasing and reposting.

As noted in the cover letter, this series depends on [1] (now [2]). It
will apply cleanly without rebasing once that patch is applied. So maybe
you can re-run the CI at that time.

--Sean

[1] https://lore.kernel.org/netdev/20250110190726.2057790-1-sean.anderson@linux.dev/
[2] https://lore.kernel.org/netdev/20250113163001.2335235-1-sean.anderson@linux.dev

>> ---
>> 
>> (no changes since v2)
>> 
>> Changes in v2:
>> - New
>> 
>>  drivers/net/ethernet/xilinx/xilinx_axienet.h  |  8 ---
>>  .../net/ethernet/xilinx/xilinx_axienet_main.c | 70 +++++++++++++------
>>  2 files changed, 47 insertions(+), 31 deletions(-)
>> 
>> diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet.h b/drivers/net/ethernet/xilinx/xilinx_axienet.h
>> index 6b8e550c2155..45d8d80dbb1a 100644
>> --- a/drivers/net/ethernet/xilinx/xilinx_axienet.h
>> +++ b/drivers/net/ethernet/xilinx/xilinx_axienet.h
>> @@ -533,10 +533,6 @@ struct skbuf_dma_descriptor {
>>   *		  supported, the maximum frame size would be 9k. Else it is
>>   *		  1522 bytes (assuming support for basic VLAN)
>>   * @rxmem:	Stores rx memory size for jumbo frame handling.
>> - * @coalesce_count_rx:	Store the irq coalesce on RX side.
>> - * @coalesce_usec_rx:	IRQ coalesce delay for RX
>> - * @coalesce_count_tx:	Store the irq coalesce on TX side.
>> - * @coalesce_usec_tx:	IRQ coalesce delay for TX
>>   * @use_dmaengine: flag to check dmaengine framework usage.
>>   * @tx_chan:	TX DMA channel.
>>   * @rx_chan:	RX DMA channel.
>> @@ -615,10 +611,6 @@ struct axienet_local {
>>  	u32 max_frm_size;
>>  	u32 rxmem;
>>  
>> -	u32 coalesce_count_rx;
>> -	u32 coalesce_usec_rx;
>> -	u32 coalesce_count_tx;
>> -	u32 coalesce_usec_tx;
>>  	u8  use_dmaengine;
>>  	struct dma_chan *tx_chan;
>>  	struct dma_chan *rx_chan;
> 
>> diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
> 
> ...
> 
>> @@ -260,6 +264,23 @@ static u32 axienet_calc_cr(struct axienet_local *lp, u32 count, u32 usec)
>>  	return cr;
>>  }
>>  
>> +/**
>> + * axienet_cr_params() - Extract coalesce parameters from the CR
> 
> nit: axienet_coalesce_params
> 
>> + * @lp: Device private data
>> + * @cr: The control register to parse
>> + * @count: Number of packets before an interrupt
>> + * @usec: Idle time (in usec) before an interrupt
>> + */
>> +static void axienet_coalesce_params(struct axienet_local *lp, u32 cr,
>> +				    u32 *count, u32 *usec)
>> +{
>> +	u64 clk_rate = axienet_dma_rate(lp);
>> +	u64 timer = FIELD_GET(XAXIDMA_DELAY_MASK, cr);
>> +
>> +	*count = FIELD_GET(XAXIDMA_COALESCE_MASK, cr);
>> +	*usec = DIV64_U64_ROUND_CLOSEST(timer * XAXIDMA_DELAY_SCALE, clk_rate);
>> +}
>> +
>>  /**
>>   * axienet_dma_start - Set up DMA registers and start DMA operation
>>   * @lp:		Pointer to the axienet_local structure
Re: [PATCH net-next v3 5/6] net: xilinx: axienet: Get coalesce parameters from driver state
Posted by Simon Horman 1 year ago 
On Mon, Jan 13, 2025 at 12:45:24PM -0500, Sean Anderson wrote:
> Hi Simon,
> 
> On 1/13/25 12:39, Simon Horman wrote:
> > On Fri, Jan 10, 2025 at 02:26:15PM -0500, Sean Anderson wrote:
> >> The cr variables now contain the same values as the control registers
> >> themselves. Extract/calculate the values from the variables instead of
> >> saving the user-specified values. This allows us to remove some
> >> bookeeping, and also lets the user know what the actual coalesce
> >> settings are.
> >> 
> >> Signed-off-by: Sean Anderson <sean.anderson@linux.dev>
> >> Reviewed by: Shannon Nelson <shannon.nelson@amd.com>
> > 
> > Hi Sean,
> > 
> > Unfortunately this series does not appear to apply cleanly to net-next.
> > Which is our CI is currently unable to cope with :(
> > 
> > Please consider rebasing and reposting.
> 
> As noted in the cover letter, this series depends on [1] (now [2]). It
> will apply cleanly without rebasing once that patch is applied. So maybe
> you can re-run the CI at that time.

Thanks Sean,

Sorry that I did miss the dependencies.

Unfortunately we don't have a way to re-run the CI at this time,
so it would probably be best to repost once the dependencies
are present in net-next.

> 
> --Sean
> 
> [1] https://lore.kernel.org/netdev/20250110190726.2057790-1-sean.anderson@linux.dev/
> [2] https://lore.kernel.org/netdev/20250113163001.2335235-1-sean.anderson@linux.dev

...

Patchew 2.1-devel-b67e4c2

© 2016 - 2026 Red Hat, Inc.