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[PATCH] dt-bindings: soc: Add new board description for Versal NET

Shubhrajyoti Datta posted 1 patch 11 months, 2 weeks ago 
Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
[PATCH] dt-bindings: soc: Add new board description for Versal NET
Posted by Shubhrajyoti Datta 11 months, 2 weeks ago 
The Versal NET (Networked Adaptive Compute Acceleration Platform) from
AMD/Xilinx is a next-generation adaptive platform designed for high
performance computing, networking, and AI acceleration. It is part of the
Versal ACAP (Adaptive Compute Acceleration Platform) family.

Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
---

 Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml b/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml
index 131aba5ed9f4..e0fa36be7e35 100644
--- a/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml
+++ b/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml
@@ -10,7 +10,7 @@ maintainers:
   - Michal Simek <michal.simek@amd.com>
 
 description: |
-  Xilinx boards with Zynq-7000 SOC or Zynq UltraScale+ MPSoC
+  Xilinx boards with Zynq-7000 SOC or Zynq UltraScale+ MPSoC or Versal Adaptive SoCs
 
 properties:
   $nodename:
@@ -187,6 +187,10 @@ properties:
           - const: qemu,mbv
           - const: amd,mbv
 
+      - description: Xilinx Versal NET
+        items:
+          - const: xlnx,versal-net
+
 additionalProperties: true
 
 ...
-- 
2.17.1
Re: [PATCH] dt-bindings: soc: Add new board description for Versal NET
Posted by Rob Herring 11 months, 1 week ago 
On Wed, Jan 08, 2025 at 05:03:38PM +0530, Shubhrajyoti Datta wrote:
> The Versal NET (Networked Adaptive Compute Acceleration Platform) from
> AMD/Xilinx is a next-generation adaptive platform designed for high
> performance computing, networking, and AI acceleration. It is part of the
> Versal ACAP (Adaptive Compute Acceleration Platform) family.
> 
> Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
> ---
> 
>  Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml | 6 +++++-
>  1 file changed, 5 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml b/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml
> index 131aba5ed9f4..e0fa36be7e35 100644
> --- a/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml
> +++ b/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml
> @@ -10,7 +10,7 @@ maintainers:
>    - Michal Simek <michal.simek@amd.com>
>  
>  description: |
> -  Xilinx boards with Zynq-7000 SOC or Zynq UltraScale+ MPSoC
> +  Xilinx boards with Zynq-7000 SOC or Zynq UltraScale+ MPSoC or Versal Adaptive SoCs

Perhaps make this more general instead of adding to it for each SoC.

Also, the '|' can be dropped while you are here.

>  
>  properties:
>    $nodename:
> @@ -187,6 +187,10 @@ properties:
>            - const: qemu,mbv
>            - const: amd,mbv
>  
> +      - description: Xilinx Versal NET

Above you say "Versal Adaptive", but not here?

> +        items:
> +          - const: xlnx,versal-net
> +
>  additionalProperties: true
>  
>  ...
> -- 
> 2.17.1
>
Re: [PATCH] dt-bindings: soc: Add new board description for Versal NET
Posted by Michal Simek 11 months ago 
Hi Rob,

On 1/10/25 17:00, Rob Herring wrote:
> On Wed, Jan 08, 2025 at 05:03:38PM +0530, Shubhrajyoti Datta wrote:
>> The Versal NET (Networked Adaptive Compute Acceleration Platform) from
>> AMD/Xilinx is a next-generation adaptive platform designed for high
>> performance computing, networking, and AI acceleration. It is part of the
>> Versal ACAP (Adaptive Compute Acceleration Platform) family.
>>
>> Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
>> ---
>>
>>   Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml | 6 +++++-
>>   1 file changed, 5 insertions(+), 1 deletion(-)
>>
>> diff --git a/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml b/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml
>> index 131aba5ed9f4..e0fa36be7e35 100644
>> --- a/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml
>> +++ b/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml
>> @@ -10,7 +10,7 @@ maintainers:
>>     - Michal Simek <michal.simek@amd.com>
>>   
>>   description: |
>> -  Xilinx boards with Zynq-7000 SOC or Zynq UltraScale+ MPSoC
>> +  Xilinx boards with Zynq-7000 SOC or Zynq UltraScale+ MPSoC or Versal Adaptive SoCs
> 
> Perhaps make this more general instead of adding to it for each SoC.
> 
> Also, the '|' can be dropped while you are here.

What's the way to generate documentation to see how that formatting looks like 
when | is used?

Thanks,
Michal
Re: [PATCH] dt-bindings: soc: Add new board description for Versal NET
Posted by Michal Simek 11 months ago 

On 1/10/25 17:00, Rob Herring wrote:
> On Wed, Jan 08, 2025 at 05:03:38PM +0530, Shubhrajyoti Datta wrote:
>> The Versal NET (Networked Adaptive Compute Acceleration Platform) from
>> AMD/Xilinx is a next-generation adaptive platform designed for high
>> performance computing, networking, and AI acceleration. It is part of the
>> Versal ACAP (Adaptive Compute Acceleration Platform) family.
>>
>> Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
>> ---
>>
>>   Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml | 6 +++++-
>>   1 file changed, 5 insertions(+), 1 deletion(-)
>>
>> diff --git a/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml b/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml
>> index 131aba5ed9f4..e0fa36be7e35 100644
>> --- a/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml
>> +++ b/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml
>> @@ -10,7 +10,7 @@ maintainers:
>>     - Michal Simek <michal.simek@amd.com>
>>   
>>   description: |
>> -  Xilinx boards with Zynq-7000 SOC or Zynq UltraScale+ MPSoC
>> +  Xilinx boards with Zynq-7000 SOC or Zynq UltraScale+ MPSoC or Versal Adaptive SoCs
> 
> Perhaps make this more general instead of adding to it for each SoC.
> 
> Also, the '|' can be dropped while you are here.

It should be likely AMD/Xilinx SOCs

> 
>>   
>>   properties:
>>     $nodename:
>> @@ -187,6 +187,10 @@ properties:
>>             - const: qemu,mbv
>>             - const: amd,mbv
>>   
>> +      - description: Xilinx Versal NET
> 
> Above you say "Versal Adaptive", but not here?

Family is marked as Versal Adaptive SOCs which contains couple of products.
Versal, Versal NET or Versal Gen 2.

Thanks,
Michal
Re: [PATCH] dt-bindings: soc: Add new board description for Versal NET
Posted by Krzysztof Kozlowski 11 months, 2 weeks ago 
On 08/01/2025 12:33, Shubhrajyoti Datta wrote:
>  description: |
> -  Xilinx boards with Zynq-7000 SOC or Zynq UltraScale+ MPSoC
> +  Xilinx boards with Zynq-7000 SOC or Zynq UltraScale+ MPSoC or Versal Adaptive SoCs
>  
>  properties:
>    $nodename:
> @@ -187,6 +187,10 @@ properties:
>            - const: qemu,mbv
>            - const: amd,mbv
>  
> +      - description: Xilinx Versal NET
> +        items:
> +          - const: xlnx,versal-net

It is usually too difficult to use SoCs on their own. Just too small
pins for our clumsy fingers. Therefore I don't get how this is supposed
to be used...

Anyway, provide the user for the binding (DTS).

Best regards,
Krzysztof
Re: [PATCH] dt-bindings: soc: Add new board description for Versal NET
Posted by Michal Simek 11 months, 2 weeks ago 

On 1/8/25 12:47, Krzysztof Kozlowski wrote:
> On 08/01/2025 12:33, Shubhrajyoti Datta wrote:
>>   description: |
>> -  Xilinx boards with Zynq-7000 SOC or Zynq UltraScale+ MPSoC
>> +  Xilinx boards with Zynq-7000 SOC or Zynq UltraScale+ MPSoC or Versal Adaptive SoCs
>>   
>>   properties:
>>     $nodename:
>> @@ -187,6 +187,10 @@ properties:
>>             - const: qemu,mbv
>>             - const: amd,mbv
>>   
>> +      - description: Xilinx Versal NET
>> +        items:
>> +          - const: xlnx,versal-net
> 
> It is usually too difficult to use SoCs on their own. Just too small
> pins for our clumsy fingers. Therefore I don't get how this is supposed
> to be used...
> 
> Anyway, provide the user for the binding (DTS).

ok. Let us strip our current DT from descriptions which are not upstreamed yet 
and wire one board to be also listed.

Thanks,
Michal

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