Add DT bindings for the PLL clock controller of the Amlogic T7 SoC family.
Signed-off-by: Jian Hu <jian.hu@amlogic.com>
---
.../bindings/clock/amlogic,t7-pll-clkc.yaml | 103 ++++++++++++++++++
.../dt-bindings/clock/amlogic,t7-pll-clkc.h | 57 ++++++++++
2 files changed, 160 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml
create mode 100644 include/dt-bindings/clock/amlogic,t7-pll-clkc.h
diff --git a/Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml
new file mode 100644
index 000000000000..fd0323678d37
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml
@@ -0,0 +1,103 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+# Copyright (C) 2024 Amlogic, Inc. All rights reserved
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/amlogic,t7-pll-clkc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Amlogic T7 PLL Clock Control Controller
+
+maintainers:
+ - Neil Armstrong <neil.armstrong@linaro.org>
+ - Jerome Brunet <jbrunet@baylibre.com>
+ - Jian Hu <jian.hu@amlogic.com>
+ - Xianwei Zhao <xianwei.zhao@amlogic.com>
+
+if:
+ properties:
+ compatible:
+ contains:
+ const: amlogic,t7-pll-mclk
+
+then:
+ properties:
+ clocks:
+ items:
+ - description: mclk pll input oscillator gate
+ - description: 24M oscillator input clock source for mclk_sel_0
+ - description: fix 50Mhz input clock source for mclk_sel_0
+
+ clock-names:
+ items:
+ - const: input
+ - const: mclk_in0
+ - const: mclk_in1
+
+else:
+ properties:
+ clocks:
+ items:
+ - description: pll input oscillator gate
+
+ clock-names:
+ items:
+ - const: input
+
+properties:
+ compatible:
+ enum:
+ - amlogic,t7-pll-gp0
+ - amlogic,t7-pll-gp1
+ - amlogic,t7-pll-hifi
+ - amlogic,t7-pll-pcie
+ - amlogic,t7-mpll
+ - amlogic,t7-pll-hdmi
+ - amlogic,t7-pll-mclk
+
+ reg:
+ maxItems: 1
+
+ '#clock-cells':
+ const: 1
+
+ clocks:
+ minItems: 1
+ maxItems: 3
+
+ clock-names:
+ minItems: 1
+ maxItems: 3
+
+required:
+ - compatible
+ - '#clock-cells'
+ - reg
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ apb {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ clock-controller@8080 {
+ compatible = "amlogic,t7-pll-gp0";
+ reg = <0 0x8080 0 0x20>;
+ clocks = <&scmi_clk 2>;
+ clock-names = "input";
+ #clock-cells = <1>;
+ };
+
+ clock-controller@8300 {
+ compatible = "amlogic,t7-pll-mclk";
+ reg = <0 0x8300 0 0x18>;
+ clocks = <&scmi_clk 2>,
+ <&xtal>,
+ <&scmi_clk 31>;
+ clock-names = "input", "mclk_in0", "mclk_in1";
+ #clock-cells = <1>;
+ };
+ };
diff --git a/include/dt-bindings/clock/amlogic,t7-pll-clkc.h b/include/dt-bindings/clock/amlogic,t7-pll-clkc.h
new file mode 100644
index 000000000000..e88c342028db
--- /dev/null
+++ b/include/dt-bindings/clock/amlogic,t7-pll-clkc.h
@@ -0,0 +1,57 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
+/*
+ * Copyright (c) 2024 Amlogic, Inc. All rights reserved.
+ * Author: Jian Hu <jian.hu@amlogic.com>
+ */
+
+#ifndef __T7_PLL_CLKC_H
+#define __T7_PLL_CLKC_H
+
+/* GP0 */
+#define CLKID_GP0_PLL_DCO 0
+#define CLKID_GP0_PLL 1
+
+/* GP1 */
+#define CLKID_GP1_PLL_DCO 0
+#define CLKID_GP1_PLL 1
+
+/* HIFI */
+#define CLKID_HIFI_PLL_DCO 0
+#define CLKID_HIFI_PLL 1
+
+/* PCIE */
+#define CLKID_PCIE_PLL_DCO 0
+#define CLKID_PCIE_PLL_DCO_DIV2 1
+#define CLKID_PCIE_PLL_OD 2
+#define CLKID_PCIE_PLL 3
+
+/* MPLL */
+#define CLKID_MPLL_PREDIV 0
+#define CLKID_MPLL0_DIV 1
+#define CLKID_MPLL0 2
+#define CLKID_MPLL1_DIV 3
+#define CLKID_MPLL1 4
+#define CLKID_MPLL2_DIV 5
+#define CLKID_MPLL2 6
+#define CLKID_MPLL3_DIV 7
+#define CLKID_MPLL3 8
+
+/* HDMI */
+#define CLKID_HDMI_PLL_DCO 0
+#define CLKID_HDMI_PLL_OD 1
+#define CLKID_HDMI_PLL 2
+
+/* MCLK */
+#define CLKID_MCLK_PLL_DCO 0
+#define CLKID_MCLK_PRE 1
+#define CLKID_MCLK_PLL 2
+#define CLKID_MCLK_0_SEL 3
+#define CLKID_MCLK_0_DIV2 4
+#define CLKID_MCLK_0_PRE 5
+#define CLKID_MCLK_0 6
+#define CLKID_MCLK_1_SEL 7
+#define CLKID_MCLK_1_DIV2 8
+#define CLKID_MCLK_1_PRE 9
+#define CLKID_MCLK_1 10
+
+#endif /* __T7_PLL_CLKC_H */
--
2.47.1On Wed, Jan 08, 2025 at 05:40:21PM +0800, Jian Hu wrote:
> Add DT bindings for the PLL clock controller of the Amlogic T7 SoC family.
>
> Signed-off-by: Jian Hu <jian.hu@amlogic.com>
> ---
> .../bindings/clock/amlogic,t7-pll-clkc.yaml | 103 ++++++++++++++++++
> .../dt-bindings/clock/amlogic,t7-pll-clkc.h | 57 ++++++++++
> 2 files changed, 160 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml
> create mode 100644 include/dt-bindings/clock/amlogic,t7-pll-clkc.h
>
> diff --git a/Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml
> new file mode 100644
> index 000000000000..fd0323678d37
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml
> @@ -0,0 +1,103 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +# Copyright (C) 2024 Amlogic, Inc. All rights reserved
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/amlogic,t7-pll-clkc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Amlogic T7 PLL Clock Control Controller
> +
> +maintainers:
> + - Neil Armstrong <neil.armstrong@linaro.org>
> + - Jerome Brunet <jbrunet@baylibre.com>
> + - Jian Hu <jian.hu@amlogic.com>
> + - Xianwei Zhao <xianwei.zhao@amlogic.com>
> +
> +if:
Move this after 'required' section.
Generally we put 'if' under 'allOf' because we're likely to have another
if/then schema on the next compatible added. If you don't think this
binding will ever get used on another chip, then it is fine as-is.
> + properties:
> + compatible:
> + contains:
> + const: amlogic,t7-pll-mclk
> +
> +then:
> + properties:
> + clocks:
> + items:
> + - description: mclk pll input oscillator gate
> + - description: 24M oscillator input clock source for mclk_sel_0
> + - description: fix 50Mhz input clock source for mclk_sel_0
> +
> + clock-names:
> + items:
> + - const: input
> + - const: mclk_in0
> + - const: mclk_in1
Move these to top-level and then both of these are just 'minItems: 3'.
> +
> +else:
> + properties:
> + clocks:
> + items:
> + - description: pll input oscillator gate
> +
> + clock-names:
> + items:
> + - const: input
And 'maxItems: 1' here.
> +
> +properties:
> + compatible:
> + enum:
> + - amlogic,t7-pll-gp0
> + - amlogic,t7-pll-gp1
> + - amlogic,t7-pll-hifi
> + - amlogic,t7-pll-pcie
> + - amlogic,t7-mpll
> + - amlogic,t7-pll-hdmi
> + - amlogic,t7-pll-mclk
> +
> + reg:
> + maxItems: 1
> +
> + '#clock-cells':
> + const: 1
> +
> + clocks:
> + minItems: 1
> + maxItems: 3
> +
> + clock-names:
> + minItems: 1
> + maxItems: 3
These are the 'top-level' definitions if that's not clear.
> +
> +required:
> + - compatible
> + - '#clock-cells'
> + - reg
> + - clocks
> + - clock-names
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + apb {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + clock-controller@8080 {
> + compatible = "amlogic,t7-pll-gp0";
> + reg = <0 0x8080 0 0x20>;
> + clocks = <&scmi_clk 2>;
> + clock-names = "input";
> + #clock-cells = <1>;
> + };
> +
> + clock-controller@8300 {
> + compatible = "amlogic,t7-pll-mclk";
> + reg = <0 0x8300 0 0x18>;
> + clocks = <&scmi_clk 2>,
> + <&xtal>,
> + <&scmi_clk 31>;
> + clock-names = "input", "mclk_in0", "mclk_in1";
> + #clock-cells = <1>;
> + };
> + };
> diff --git a/include/dt-bindings/clock/amlogic,t7-pll-clkc.h b/include/dt-bindings/clock/amlogic,t7-pll-clkc.h
> new file mode 100644
> index 000000000000..e88c342028db
> --- /dev/null
> +++ b/include/dt-bindings/clock/amlogic,t7-pll-clkc.h
> @@ -0,0 +1,57 @@
> +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
> +/*
> + * Copyright (c) 2024 Amlogic, Inc. All rights reserved.
> + * Author: Jian Hu <jian.hu@amlogic.com>
> + */
> +
> +#ifndef __T7_PLL_CLKC_H
> +#define __T7_PLL_CLKC_H
> +
> +/* GP0 */
> +#define CLKID_GP0_PLL_DCO 0
> +#define CLKID_GP0_PLL 1
> +
> +/* GP1 */
> +#define CLKID_GP1_PLL_DCO 0
> +#define CLKID_GP1_PLL 1
> +
> +/* HIFI */
> +#define CLKID_HIFI_PLL_DCO 0
> +#define CLKID_HIFI_PLL 1
> +
> +/* PCIE */
> +#define CLKID_PCIE_PLL_DCO 0
> +#define CLKID_PCIE_PLL_DCO_DIV2 1
> +#define CLKID_PCIE_PLL_OD 2
> +#define CLKID_PCIE_PLL 3
> +
> +/* MPLL */
> +#define CLKID_MPLL_PREDIV 0
> +#define CLKID_MPLL0_DIV 1
> +#define CLKID_MPLL0 2
> +#define CLKID_MPLL1_DIV 3
> +#define CLKID_MPLL1 4
> +#define CLKID_MPLL2_DIV 5
> +#define CLKID_MPLL2 6
> +#define CLKID_MPLL3_DIV 7
> +#define CLKID_MPLL3 8
> +
> +/* HDMI */
> +#define CLKID_HDMI_PLL_DCO 0
> +#define CLKID_HDMI_PLL_OD 1
> +#define CLKID_HDMI_PLL 2
> +
> +/* MCLK */
> +#define CLKID_MCLK_PLL_DCO 0
> +#define CLKID_MCLK_PRE 1
> +#define CLKID_MCLK_PLL 2
> +#define CLKID_MCLK_0_SEL 3
> +#define CLKID_MCLK_0_DIV2 4
> +#define CLKID_MCLK_0_PRE 5
> +#define CLKID_MCLK_0 6
> +#define CLKID_MCLK_1_SEL 7
> +#define CLKID_MCLK_1_DIV2 8
> +#define CLKID_MCLK_1_PRE 9
> +#define CLKID_MCLK_1 10
> +
> +#endif /* __T7_PLL_CLKC_H */
> --
> 2.47.1
>
Hi, Rob
Thanks for your review
On 2025/1/10 23:54, Rob Herring wrote:
> [ EXTERNAL EMAIL ]
>
> On Wed, Jan 08, 2025 at 05:40:21PM +0800, Jian Hu wrote:
>> Add DT bindings for the PLL clock controller of the Amlogic T7 SoC family.
>>
>> Signed-off-by: Jian Hu <jian.hu@amlogic.com>
>> ---
>> .../bindings/clock/amlogic,t7-pll-clkc.yaml | 103 ++++++++++++++++++
>> .../dt-bindings/clock/amlogic,t7-pll-clkc.h | 57 ++++++++++
>> 2 files changed, 160 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml
>> create mode 100644 include/dt-bindings/clock/amlogic,t7-pll-clkc.h
>>
>> diff --git a/Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml
>> new file mode 100644
>> index 000000000000..fd0323678d37
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml
>> @@ -0,0 +1,103 @@
>> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
>> +# Copyright (C) 2024 Amlogic, Inc. All rights reserved
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/clock/amlogic,t7-pll-clkc.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Amlogic T7 PLL Clock Control Controller
>> +
>> +maintainers:
>> + - Neil Armstrong <neil.armstrong@linaro.org>
>> + - Jerome Brunet <jbrunet@baylibre.com>
>> + - Jian Hu <jian.hu@amlogic.com>
>> + - Xianwei Zhao <xianwei.zhao@amlogic.com>
>> +
>> +if:
> Move this after 'required' section.
>
> Generally we put 'if' under 'allOf' because we're likely to have another
> if/then schema on the next compatible added. If you don't think this
> binding will ever get used on another chip, then it is fine as-is.
OK, I will move 'if' after 'required'. and add two 'if' for them.
>> + properties:
>> + compatible:
>> + contains:
>> + const: amlogic,t7-pll-mclk
>> +
>> +then:
>> + properties:
>> + clocks:
>> + items:
>> + - description: mclk pll input oscillator gate
>> + - description: 24M oscillator input clock source for mclk_sel_0
>> + - description: fix 50Mhz input clock source for mclk_sel_0
>> +
>> + clock-names:
>> + items:
>> + - const: input
>> + - const: mclk_in0
>> + - const: mclk_in1
> Move these to top-level and then both of these are just 'minItems: 3'.
Ok.
>> +
>> +else:
>> + properties:
>> + clocks:
>> + items:
>> + - description: pll input oscillator gate
>> +
>> + clock-names:
>> + items:
>> + - const: input
> And 'maxItems: 1' here.
Ok.
>
>> +
>> +properties:
>> + compatible:
>> + enum:
>> + - amlogic,t7-pll-gp0
>> + - amlogic,t7-pll-gp1
>> + - amlogic,t7-pll-hifi
>> + - amlogic,t7-pll-pcie
>> + - amlogic,t7-mpll
>> + - amlogic,t7-pll-hdmi
>> + - amlogic,t7-pll-mclk
>> +
>> + reg:
>> + maxItems: 1
>> +
>> + '#clock-cells':
>> + const: 1
>> +
>> + clocks:
>> + minItems: 1
>> + maxItems: 3
>> +
>> + clock-names:
>> + minItems: 1
>> + maxItems: 3
> These are the 'top-level' definitions if that's not clear.
Ok, I will put it in the top.
>> +
>> +required:
>> + - compatible
>> + - '#clock-cells'
>> + - reg
>> + - clocks
>> + - clock-names
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> + - |
>> + apb {
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> +
>> + clock-controller@8080 {
>> + compatible = "amlogic,t7-pll-gp0";
>> + reg = <0 0x8080 0 0x20>;
>> + clocks = <&scmi_clk 2>;
>> + clock-names = "input";
>> + #clock-cells = <1>;
>> + };
>> +
>> + clock-controller@8300 {
>> + compatible = "amlogic,t7-pll-mclk";
>> + reg = <0 0x8300 0 0x18>;
>> + clocks = <&scmi_clk 2>,
>> + <&xtal>,
>> + <&scmi_clk 31>;
>> + clock-names = "input", "mclk_in0", "mclk_in1";
>> + #clock-cells = <1>;
>> + };
>> + };
>> diff --git a/include/dt-bindings/clock/amlogic,t7-pll-clkc.h b/include/dt-bindings/clock/amlogic,t7-pll-clkc.h
>> new file mode 100644
>> index 000000000000..e88c342028db
>> --- /dev/null
>> +++ b/include/dt-bindings/clock/amlogic,t7-pll-clkc.h
>> @@ -0,0 +1,57 @@
>> +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
>> +/*
>> + * Copyright (c) 2024 Amlogic, Inc. All rights reserved.
>> + * Author: Jian Hu <jian.hu@amlogic.com>
>> + */
>> +
>> +#ifndef __T7_PLL_CLKC_H
>> +#define __T7_PLL_CLKC_H
>> +
>> +/* GP0 */
>> +#define CLKID_GP0_PLL_DCO 0
>> +#define CLKID_GP0_PLL 1
>> +
>> +/* GP1 */
>> +#define CLKID_GP1_PLL_DCO 0
>> +#define CLKID_GP1_PLL 1
>> +
>> +/* HIFI */
>> +#define CLKID_HIFI_PLL_DCO 0
>> +#define CLKID_HIFI_PLL 1
>> +
>> +/* PCIE */
>> +#define CLKID_PCIE_PLL_DCO 0
>> +#define CLKID_PCIE_PLL_DCO_DIV2 1
>> +#define CLKID_PCIE_PLL_OD 2
>> +#define CLKID_PCIE_PLL 3
>> +
>> +/* MPLL */
>> +#define CLKID_MPLL_PREDIV 0
>> +#define CLKID_MPLL0_DIV 1
>> +#define CLKID_MPLL0 2
>> +#define CLKID_MPLL1_DIV 3
>> +#define CLKID_MPLL1 4
>> +#define CLKID_MPLL2_DIV 5
>> +#define CLKID_MPLL2 6
>> +#define CLKID_MPLL3_DIV 7
>> +#define CLKID_MPLL3 8
>> +
>> +/* HDMI */
>> +#define CLKID_HDMI_PLL_DCO 0
>> +#define CLKID_HDMI_PLL_OD 1
>> +#define CLKID_HDMI_PLL 2
>> +
>> +/* MCLK */
>> +#define CLKID_MCLK_PLL_DCO 0
>> +#define CLKID_MCLK_PRE 1
>> +#define CLKID_MCLK_PLL 2
>> +#define CLKID_MCLK_0_SEL 3
>> +#define CLKID_MCLK_0_DIV2 4
>> +#define CLKID_MCLK_0_PRE 5
>> +#define CLKID_MCLK_0 6
>> +#define CLKID_MCLK_1_SEL 7
>> +#define CLKID_MCLK_1_DIV2 8
>> +#define CLKID_MCLK_1_PRE 9
>> +#define CLKID_MCLK_1 10
>> +
>> +#endif /* __T7_PLL_CLKC_H */
>> --
>> 2.47.1
>>
On Fri 10 Jan 2025 at 09:54, Rob Herring <robh@kernel.org> wrote:
> On Wed, Jan 08, 2025 at 05:40:21PM +0800, Jian Hu wrote:
>> Add DT bindings for the PLL clock controller of the Amlogic T7 SoC family.
>>
>> Signed-off-by: Jian Hu <jian.hu@amlogic.com>
>> ---
>> .../bindings/clock/amlogic,t7-pll-clkc.yaml | 103 ++++++++++++++++++
>> .../dt-bindings/clock/amlogic,t7-pll-clkc.h | 57 ++++++++++
>> 2 files changed, 160 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml
>> create mode 100644 include/dt-bindings/clock/amlogic,t7-pll-clkc.h
>>
>> diff --git
>> a/Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml
>> b/Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml
>> new file mode 100644
>> index 000000000000..fd0323678d37
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml
>> @@ -0,0 +1,103 @@
>> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
>> +# Copyright (C) 2024 Amlogic, Inc. All rights reserved
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/clock/amlogic,t7-pll-clkc.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Amlogic T7 PLL Clock Control Controller
>> +
>> +maintainers:
>> + - Neil Armstrong <neil.armstrong@linaro.org>
>> + - Jerome Brunet <jbrunet@baylibre.com>
>> + - Jian Hu <jian.hu@amlogic.com>
>> + - Xianwei Zhao <xianwei.zhao@amlogic.com>
>> +
>> +if:
>
> Move this after 'required' section.
>
> Generally we put 'if' under 'allOf' because we're likely to have another
> if/then schema on the next compatible added. If you don't think this
> binding will ever get used on another chip, then it is fine as-is.
>
>> + properties:
>> + compatible:
>> + contains:
>> + const: amlogic,t7-pll-mclk
>> +
>> +then:
>> + properties:
>> + clocks:
>> + items:
>> + - description: mclk pll input oscillator gate
>> + - description: 24M oscillator input clock source for mclk_sel_0
>> + - description: fix 50Mhz input clock source for mclk_sel_0
The rate is whatever the clock will actually be. Better not to mention
it in this doc.
>> +
>> + clock-names:
>> + items:
one being "input" and other suffixed "_in" looks really odd
>> + - const: input
>> + - const: mclk_in0
>> + - const: mclk_in1
or just in0, in1, in2 if you are going with Rob's suggestion.
Having "mclk_" in the top level would be confusing.
>
> Move these to top-level and then both of these are just 'minItems: 3'.
>
>> +
>> +else:
>> + properties:
>> + clocks:
>> + items:
>> + - description: pll input oscillator gate
>> +
>> + clock-names:
>> + items:
>> + - const: input
>
> And 'maxItems: 1' here.
>
>> +
>> +properties:
>> + compatible:
>> + enum:
>> + - amlogic,t7-pll-gp0
>> + - amlogic,t7-pll-gp1
>> + - amlogic,t7-pll-hifi
>> + - amlogic,t7-pll-pcie
>> + - amlogic,t7-mpll
>> + - amlogic,t7-pll-hdmi
>> + - amlogic,t7-pll-mclk
>> +
>> + reg:
>> + maxItems: 1
>> +
>> + '#clock-cells':
>> + const: 1
>> +
>> + clocks:
>> + minItems: 1
>> + maxItems: 3
>> +
>> + clock-names:
>> + minItems: 1
>> + maxItems: 3
>
> These are the 'top-level' definitions if that's not clear.
>
>> +
>> +required:
>> + - compatible
>> + - '#clock-cells'
>> + - reg
>> + - clocks
>> + - clock-names
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> + - |
>> + apb {
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> +
>> + clock-controller@8080 {
>> + compatible = "amlogic,t7-pll-gp0";
>> + reg = <0 0x8080 0 0x20>;
>> + clocks = <&scmi_clk 2>;
>> + clock-names = "input";
>> + #clock-cells = <1>;
>> + };
>> +
>> + clock-controller@8300 {
>> + compatible = "amlogic,t7-pll-mclk";
>> + reg = <0 0x8300 0 0x18>;
>> + clocks = <&scmi_clk 2>,
>> + <&xtal>,
>> + <&scmi_clk 31>;
>> + clock-names = "input", "mclk_in0", "mclk_in1";
>> + #clock-cells = <1>;
>> + };
>> + };
>> diff --git a/include/dt-bindings/clock/amlogic,t7-pll-clkc.h b/include/dt-bindings/clock/amlogic,t7-pll-clkc.h
>> new file mode 100644
>> index 000000000000..e88c342028db
>> --- /dev/null
>> +++ b/include/dt-bindings/clock/amlogic,t7-pll-clkc.h
>> @@ -0,0 +1,57 @@
>> +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
>> +/*
>> + * Copyright (c) 2024 Amlogic, Inc. All rights reserved.
>> + * Author: Jian Hu <jian.hu@amlogic.com>
>> + */
>> +
>> +#ifndef __T7_PLL_CLKC_H
>> +#define __T7_PLL_CLKC_H
>> +
>> +/* GP0 */
>> +#define CLKID_GP0_PLL_DCO 0
>> +#define CLKID_GP0_PLL 1
>> +
>> +/* GP1 */
>> +#define CLKID_GP1_PLL_DCO 0
>> +#define CLKID_GP1_PLL 1
>> +
>> +/* HIFI */
>> +#define CLKID_HIFI_PLL_DCO 0
>> +#define CLKID_HIFI_PLL 1
>> +
>> +/* PCIE */
>> +#define CLKID_PCIE_PLL_DCO 0
>> +#define CLKID_PCIE_PLL_DCO_DIV2 1
>> +#define CLKID_PCIE_PLL_OD 2
>> +#define CLKID_PCIE_PLL 3
>> +
>> +/* MPLL */
>> +#define CLKID_MPLL_PREDIV 0
>> +#define CLKID_MPLL0_DIV 1
>> +#define CLKID_MPLL0 2
>> +#define CLKID_MPLL1_DIV 3
>> +#define CLKID_MPLL1 4
>> +#define CLKID_MPLL2_DIV 5
>> +#define CLKID_MPLL2 6
>> +#define CLKID_MPLL3_DIV 7
>> +#define CLKID_MPLL3 8
>> +
>> +/* HDMI */
>> +#define CLKID_HDMI_PLL_DCO 0
>> +#define CLKID_HDMI_PLL_OD 1
>> +#define CLKID_HDMI_PLL 2
>> +
>> +/* MCLK */
>> +#define CLKID_MCLK_PLL_DCO 0
>> +#define CLKID_MCLK_PRE 1
>> +#define CLKID_MCLK_PLL 2
>> +#define CLKID_MCLK_0_SEL 3
>> +#define CLKID_MCLK_0_DIV2 4
>> +#define CLKID_MCLK_0_PRE 5
>> +#define CLKID_MCLK_0 6
>> +#define CLKID_MCLK_1_SEL 7
>> +#define CLKID_MCLK_1_DIV2 8
>> +#define CLKID_MCLK_1_PRE 9
>> +#define CLKID_MCLK_1 10
>> +
>> +#endif /* __T7_PLL_CLKC_H */
>> --
>> 2.47.1
>>
--
Jerome
Hi, Jerome Thanks for your review. On 2025/1/14 1:50, Jerome Brunet wrote: > [ EXTERNAL EMAIL ] > > On Fri 10 Jan 2025 at 09:54, Rob Herring <robh@kernel.org> wrote: > >> On Wed, Jan 08, 2025 at 05:40:21PM +0800, Jian Hu wrote: >>> Add DT bindings for the PLL clock controller of the Amlogic T7 SoC family. >>> >>> Signed-off-by: Jian Hu <jian.hu@amlogic.com> >>> --- >>> .../bindings/clock/amlogic,t7-pll-clkc.yaml | 103 ++++++++++++++++++ >>> .../dt-bindings/clock/amlogic,t7-pll-clkc.h | 57 ++++++++++ >>> 2 files changed, 160 insertions(+) >>> create mode 100644 Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml >>> create mode 100644 include/dt-bindings/clock/amlogic,t7-pll-clkc.h >>> >>> diff --git >>> a/Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml >>> b/Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml >>> new file mode 100644 >>> index 000000000000..fd0323678d37 >>> --- /dev/null >>> +++ b/Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml >>> @@ -0,0 +1,103 @@ >>> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause >>> +# Copyright (C) 2024 Amlogic, Inc. All rights reserved >>> +%YAML 1.2 >>> +--- >>> +$id: http://devicetree.org/schemas/clock/amlogic,t7-pll-clkc.yaml# >>> +$schema: http://devicetree.org/meta-schemas/core.yaml# >>> + >>> +title: Amlogic T7 PLL Clock Control Controller >>> + >>> +maintainers: >>> + - Neil Armstrong <neil.armstrong@linaro.org> >>> + - Jerome Brunet <jbrunet@baylibre.com> >>> + - Jian Hu <jian.hu@amlogic.com> >>> + - Xianwei Zhao <xianwei.zhao@amlogic.com> >>> + >>> +if: >> Move this after 'required' section. >> >> Generally we put 'if' under 'allOf' because we're likely to have another >> if/then schema on the next compatible added. If you don't think this >> binding will ever get used on another chip, then it is fine as-is. >> >>> + properties: >>> + compatible: >>> + contains: >>> + const: amlogic,t7-pll-mclk >>> + >>> +then: >>> + properties: >>> + clocks: >>> + items: >>> + - description: mclk pll input oscillator gate >>> + - description: 24M oscillator input clock source for mclk_sel_0 >>> + - description: fix 50Mhz input clock source for mclk_sel_0 > The rate is whatever the clock will actually be. Better not to mention > it in this doc. OK, I will remove the rate here. >>> + >>> + clock-names: >>> + items: > one being "input" and other suffixed "_in" looks really odd > >>> + - const: input >>> + - const: mclk_in0 >>> + - const: mclk_in1 > or just in0, in1, in2 if you are going with Rob's suggestion. > Having "mclk_" in the top level would be confusing. Ok, I will use in0/in1/in2 for them. > -- > 2.47.1 > > -- > Jerome
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